Prosecution Insights
Last updated: October 02, 2026
Application No. 17/721,675

CAPACITOR STRUCTURE, SEMICONDUCTOR STRUCTURE, AND METHOD FOR MANUFACTURING THEREOF

Final Rejection §103
Filed
Apr 15, 2022
Priority
Apr 28, 2017 — nonprovisional of PCTJP2017016977 +5 more
Examiner
SLUTSKER, JULIA
Art Unit
2891
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Ap Memory Technology Corporation
OA Round
2 (Final)
77%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
843 granted / 1097 resolved
+8.8% vs TC avg
Moderate +13% lift
Without
With
+12.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
30 currently pending
Career history
1129
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
50.0%
+10.0% vs TC avg
§102
22.2%
-17.8% vs TC avg
§112
20.8%
-19.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1097 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 2, 5, 6, 9, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Hwang (US 2017/0019024) in view of Ramachandran (US 2016/0095221). Regarding claim 1, Hwang discloses a capacitor structure, comprising: a substrate (Fig. 4, numeral 310) having a first surface and a second surface opposite to the first surface,; a middle-of-line (MEOL) structure (340) over the first surface of the substrate (301), wherein the MEOL structure (340) comprises a dielectric material (330) and a capacitor (340) embedded in the dielectric material (330), and the capacitor comprises a bottom plate (341) and a top plate (343) over the bottom plate (341); a metallization structure (291) over the MEOL structure (340); wherein the substrate (310) further comprises a plurality of first through vias (372) extending from the second surface of the substrate to the bottom plate (341). Hwang does not disclose that wherein the substrate is a semiconductor substrate or a glass substrate. Ramachandran however discloses the substrate is a semiconductor substrate (Fig.1, numeral 104; [0029]). It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Hwang with Ramachandran to have the substrate as a semiconductor substrate because the semiconductor substrates are typically used im fabrication of electronic circuit components (Ramachandran, Abstract). Regarding claim 2, Hwang discloses wherein the MEOL structure further comprises: a plurality of first metal contacts (Fig.7, numeral 573) extending from the top plate (543) of the capacitor to the metallization structure (582); and a plurality of second metal contacts (572) extending from the capacitor bottom plate (541) of the capacitor to the metallization structure; wherein the plurality of first metal contacts and the plurality of second metal contacts are in contact with a first metal layer (M1) (582); (581) of the metallization structure. Regarding claim 5, Hwang discloses a feed-through connection structure extending from the second surface of the substrate to the metallization structure (Fig. 4, numeral 371). Regarding claim 6, Hwang does not disclose a redistribution layer on the second surface and in contact with the plurality of first through vias. Ramachandran however discloses a redistribution layer on the second surface and in contact with the plurality of first through vias ([0038]). It would have been therefore obvious to one ordinary skill in the art at the time the invention was filed to modify Ichiyanagi with Ramachandran to have a redistribution layer on the second surface and in contact with the plurality of first through vias for the purpose of forming an integration circuit. Regarding claim 9, Hwang discloses a semiconductor structure, comprising: a package substrate (Fig. 4, numeral 310); a first capacitor structure (340) bonded over the package substrate (310), wherein the first capacitor structure comprises: a substrate (310), a middle-of-line (MEOL) structure (340) over the substrate (310), wherein the MEOL structure comprises a dielectric material (330) and a capacitor (340) embedded in the dielectric material (330); a plurality of first through vias (372) extending through the substrate (310), wherein the package substrate (310)is electrically connected to the capacitor (240) of the first capacitor structure through the plurality of first through vias (372); (373) and a semiconductor device (Fig.3) bonded over the first capacitor structure ([0051]). Hwang does not disclose wherein the substrate is a semiconductor substrate or a glass substrate. Ramachandran however discloses the substrate is a semiconductor substrate (Fig.1, numeral 104; [0029]). It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Hwang with Ramachandran to have the substrate as a semiconductor substrate because the semiconductor substrates are typically used im fabrication of electronic circuit components (Ramachandran, Abstract). Regarding claim 11, Hwang discloses wherein the first capacitor structure further comprises a first feed-through connection structure (Fig.4, numerals 371, 373) adjacent to the capacitor (340) and the first through vias (372). Claim(s) 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hwang in view of Ramachandran as applied to claim 1 above, and further in view of Ichiyanagi (US 2010/0300740). Regarding claim 7, Hwang does not disclose wherein each of the plurality of first through vias comprises a narrower end in proximity to the second surface of the substrate. Ichiyanagi however discloses wherein each of the plurality of first through vias comprises a narrower end in proximity to the second surface of the substrate(Fig. 1, numeral 43). It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Hwang with Ichiyanagi to have each of the plurality of first through vias comprises a narrower end in proximity to the second surface of the substrate because this one of the typical shapes of vias. Regarding claim 8, Hwang does not disclose wherein each of the plurality of first through vias comprises a narrower end in proximity to the bottom plate of the capacitor. Ichiyanagi discloses wherein each of the plurality of first through vias (43) comprises a narrower end in proximity to the bottom plate (122) of the capacitor (101) (Fig.1). It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Hwang with Ichiyanagi to have each of the plurality of first through vias comprises a narrower end in proximity to the second surface of the substrate because this one of the typical shapes of vias. Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hwang in view of Ramachandran as applied to claim 9 above, and further in view of Pandey (US 2017/0256490). Regarding claim 15, Hwang does not disclose wherein each of the plurality of first through vias are laterally surrounded by an oxide liner. Pandey however discloses wherein each of the plurality of first through vias are laterally surrounded by an oxide liner ([0051]). It would have been thereof obvious to one of ordinary skill in the art at the time the invention was filed to modify Ichiyanagi with Pandey to have each of the plurality of first through vias are laterally surrounded by an oxide liner for the purpose of forming through vias with targeted capacitance (Pandey, [0054]). Allowable Subject Matter Claims 3, 4, 10, 12-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The search of the prior art does not disclose or reasonably suggest wherein the MEOL structure further comprises: a relay metal leveled with the bottom plate; and a plurality of third metal contacts extending from the relay metal to the metallization structure as required by claim 3. The search of the prior art does not disclose or reasonably suggest a top plate over the bottom plate, wherein a planar area of the top plate is less than a planar area of the bottom metal plate from a top view perspective; and a plurality of capacitor cells between the bottom plate and the top plate; wherein the plurality of first through vias are in contact with a bottom surface of the bottom plate as required by claim 10. The search of the prior art does not disclose or reasonably suggest a relay metal leveling with the bottom plate; a second through via extending from the relay metal to a backside of the first capacitor structure; and a plurality of metal contacts landing on the relay metal as required by claim 12. Response to Arguments Applicant’s arguments with respect to claim(s) 1, 2, 5-9, 11, and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JULIA SLUTSKER whose telephone number is (571)270-3849. The examiner can normally be reached Monday-Friday, 9 am-6 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JULIA SLUTSKER/ Primary Examiner, Art Unit 2891
Read full office action

Prosecution Timeline

Apr 15, 2022
Application Filed
Apr 23, 2026
Non-Final Rejection mailed — §103
Jul 22, 2026
Response Filed
Sep 08, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
77%
Grant Probability
90%
With Interview (+12.9%)
2y 5m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1097 resolved cases by this examiner. Grant probability derived from career allowance rate.

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