DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I (claims 1-15) in the reply filed on 09/02/2025 is acknowledged. The traversal is on the ground(s) that a single search and examination can be conducted without imposing a significant burden on the Examiner. This is not found persuasive because as stated in the previse Office Action, the inventions have acquired a separate status in the art in view of their different classification (note the separate classifications above); the inventions have acquired a separate status in the art due to their recognized divergent subject matter (note the classification scheme itself here is evidence that the inventions have acquired a separate status in the art due to their recognized divergent subject matter, here methods vs. the devices); the inventions require a different field of search (for example, searching different classes/subclasses or electronic resources, or employing different search queries); the prior art applicable to one invention would not likely be applicable to another invention (note it is especially likely there will be prior art applicable to the method claims which will not be likely to be applicable to the device claims and vice versa in this instance).
The requirement is still deemed proper and is therefore made FINAL.
Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 09/02/2025.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5, 7-11, and 14 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Ichiyanagi (US 2010/0300740).
Regarding claim 1, Ichiyanagi discloses a capacitor structure, comprising: a substrate (Fig. 1, numeral 34) having a first surface and a second surface opposite to the first surface; a middle-of-line (MEOL) structure (101) over the first surface of the substrate (34), the MEOL structure comprises a capacitor (101) ([0034]), and the capacitor comprises a bottom plate (122) and a top plate (111) over the bottom plate (122); a metallization structure (44), (45), (46) over the MEOL structure (101); wherein the substrate (34) further comprises a plurality of first through vias (43) extending from the second surface of the substrate (34) to the bottom plate (122).
Regarding claim 2, Ichiyanagi discloses wherein the MEOL structure further comprises: a plurality of first metal contacts (43) extending from the top plate (111) of the capacitor (101) to the metallization structure (44), (45), (46); and a plurality of second metal contacts (131) (Fig.2) extending from the capacitor bottom plate (111) of the capacitor to the metallization structure (44), (45), (46); wherein the plurality of first metal contacts and the plurality of second metal contacts are in contact with a first metal layer (M1) (47) of the metallization structure.
Regarding claim 5, Ichiyanagi discloses a feed-through connection structure (Fig.1, numeral 16) extending from the second surface of the substrate (34) to the metallization structure (47).
Regarding claim 7, Ichiyanagi discloses wherein each of the plurality of first through vias comprises a narrower end in proximity to the second surface of the substrate (Fig. 1, numeral 43).
Regarding claim 8, Ichiyanagi discloses wherein each of the plurality of first through vias (43) comprises a narrower end in proximity to the bottom plate (122) of the capacitor (101) (Fig.1).
Regarding claim 9, Ichiyanagi discloses a semiconductor structure, comprising: a package substrate (Fig.1, numeral 34); a first capacitor structure (101) bonded over the package substrate (34), wherein the first capacitor structure comprises a capacitor (101), and the package substrate (34) is electrically connected to the first capacitor (101) structure through a plurality of first through vias (43) extending from the capacitor (101) to a backside of the first capacitor structure (122); and a semiconductor device (21) bonded over the first capacitor structure (101).
Regarding claim 10, Ichiyanagi discloses, wherein the capacitor comprises: a bottom plate (Fig. 1m numeral 122); a top plate (111) over the bottom plate (122), wherein a planar area of the top plate (111) is less than a planar area of the bottom metal plate (122) from a top view perspective (Fig. 1); and a plurality of capacitor cells (Fig. 1, numerals 142, 141, 105) between the bottom plate (122) and the top plate (111); wherein the plurality of first through vias (131, 132) are in contact with a bottom surface (122) of the bottom plate.
Regarding claim 11, Ichiyanagi discloses wherein the first capacitor structure further comprises a first feed-through connection structure (Fig.1, numeral 16) adjacent to the capacitor (101) and the first through vias (131).
Regarding claim 14, Ichiyanagi discloses wherein the first feed-through connection structure (16) in the first capacitor structure (101) is isolated from the capacitor (101) (Fig.1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 4, 12, and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ichiyanagi as applied to claims 1, 9 above, and further in view of Hattori (US 2016/0372265).
Regarding claim 3, Ichiyanagi discloses a plurality of third metal contacts (16) extending from the metal (41) to the metallization structure (42).
Ichiyanagi does not disclose the metal layer is a relay metal leveled with the bottom plate.
Hattori however discloses wherein the MEOL structure further comprises: a relay metal leveled (Fig.2, numerals 24a) with the bottom plate (22).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Ichiyanagi with Hattori to have the metal layer as a relay metal leveled with the bottom plate for the purpose of forming connection terminals (Hattori, [0099]).
Regarding claim 4, Hattori discloses wherein the substrate further comprises a second through via (Fig. 2A, numeral 26B) extending from the second surface of the substrate to the relay metal (24a).
Regarding claim 12, Sinani discloses a second through via (Fig.1, numeral 16) extending from the metal (41) to the backside of the first capacitor structure and a plurality of metal contacts (16) landing on the metal (41).
Ichiyanagi does not disclose that the metal is a relay metal and a relay metal leveling with the bottom plate.
Hattori discloses wherein the metal is relay metal (24a) leveling with the bottom plate (22).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Ichiyanagi with Hattori to have the metal layer as a relay metal leveled with the bottom plate for the purpose of forming connection terminals (Hattori, [0099]).
Regarding claim 13, Ichiyanagi discloses wherein a length of the second through via (16) is identical to a length of the first through via (16) (Fig.1).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ichiyanagi as applied to claim 1 above, and further in view of Ramachandran (US 2016/0095221).
Regarding claim 6, Ichiyanagi does not disclose a redistribution layer on the second surface and in contact with the plurality of first through vias.
Ramachandran however discloses a redistribution layer on the second surface and in contact with the plurality of first through vias ([0038]).
It would have been therefore obvious to one ordinary skill in the art at the time the invention was filed to modify Ichiyanagi with Ramachandran to have a redistribution layer on the second surface and in contact with the plurality of first through vias for the purpose of forming an integration circuit.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ichiyanagi as applied to claim 9 above, and further in view of Pandey (US 2017/0256490).
Regarding claim 15, Ichiyanagi does not disclose wherein each of the plurality of first through vias are laterally surrounded by an oxide liner.
Pandey however discloses wherein each of the plurality of first through vias are laterally surrounded by an oxide liner ([0051]).
It would have been thereof obvious to one of ordinary skill in the art at the time the invention was filed to modify Ichiyanagi with Pandey to have each of the plurality of first through vias are laterally surrounded by an oxide liner for the purpose of forming through vias with targeted capacitance (Pandey, [0054]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JULIA SLUTSKER whose telephone number is (571)270-3849. The examiner can normally be reached Monday-Friday, 9 am-6 pm.
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/JULIA SLUTSKER/Primary Examiner, Art Unit 2891
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