Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a Final Office action based on application 17/721,723 in response to reply filed June 23, 2026. Claims 1-2, 4-10, 12-22 are currently pending and have been considered below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai (Pre-Grant Publication 2021/0125875) in view of Lin (Pre-Grant Publication 2021/0367059).
Regarding claim 16, Tsai discloses a semiconductor device comprising:
a substrate having a base (Fig. 18b, 20), a first semiconductor fin structure (24), and a second semiconductor fin structure (24) over the base;
an isolation structure (22) over the base, wherein the first semiconductor fin structure and the second semiconductor fin structure are partially in the isolation structure;
a dielectric fin structure (25) partially embedded in the isolation structure and between the first semiconductor fin structure and the second semiconductor fin structure;
a first gate stack (94) wrapping around the first semiconductor fin structure and over a first side of the dielectric fin structure;
a second gate stack (94) wrapping around the second semiconductor fin structure and over a second side of the dielectric fin structure; and
a gate cut isolation structure (60) over the dielectric fin structure, wherein the dielectric fin structure and the gate cut isolation structure electrically insulate the first gate stack from the second gate stack, wherein a top surface of the dielectric fin structure is level with top surfaces of the first and second semiconductor fin structures, wherein the gate cut isolation structure (60) is spaced apart from the isolation structure (22) (Paragraph [0021]).
Tsai does not disclose a top surface of the gate cut isolation structure is wider than a bottom surface of the gate cut isolation structure. However Lin discloses a semiconductor device comprising:
A gate cut isolation region (Fig. 11b, 52) formed over a dummy fin (25’) wherein the gate cut isolation structure can be formed with slanted sidewalls wherein a top surface of the gate cut can be wider than a bottom surface (Fig. 25).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the gate cut isolation structure having a wider upper surface because it will widen the gate distance between the replacement gates thereby enhancing the isolation properties of the gate cut isolation structures.
Regarding claim 17, Tsai further discloses:
the dielectric fin structure has an upper portion between the first gate stack and the second gate stack, and a sum of a first thickness of the upper portion and a second thickness of the gate cut isolation structure is greater than a third thickness of the first gate stack (Fig. 18b).
Regarding claim 18-20, Tsai further discloses:
A gate cut isolation structure opening (Fig. 12, 56) to be filled by dielectric material (60’) and a dielectric fin (25) wherein the bottom portion of the gate cut isolation structure extends into the dielectric fin structure and the top portion of the dielectric fin extends into the bottom portion of the gate cut isolation structure.
Tsai further discloses the dielectric fin (25) extends through isolation material (22) (Paragraph [0021]).
Allowable Subject Matter
Claims 1-2, 4-10, 12-15 & 21-22 allowed.
The following is an examiner’s statement of reasons for allowance: Claim 1 is allowed because none of the prior art either alone or in combination discloses a semiconductor structure comprising: a gate cut isolation structure over the dielectric fin structure and between the first gate stack and the second gate stack, wherein the gate cut isolation structure comprises a protection layer and a fill layer over the protection layer, and the protection layer and the fill layer are made of different materials, wherein the protection layer of the gate cut isolation structure comprises an upper portion and a lower portion wider than the upper portion, in combination with the other limitations of claim 1. Claims 2, 4-8, & 21 are also allowed based on their dependency from claim 1.
Claim 9 is allowed because none of the prior art either alone or in combination discloses a semiconductor structure comprising: an interlayer dielectric layer over the source/drain feature, wherein the protection layer includes a first portion between the fill layer and the interlayer dielectric layer and a second portion between the fill layer and the first gate stack, the first portion of the protection layer has a first thickness as measured in a first horizontal direction, the second portion of the protection layer has a second thickness as measured in a second horizontal direction perpendicular to the first horizontal direction, and the first thickness is greater than the second thickness, in combination with the other limitations of claim 9. Claims 10, 12-15 & 22 are also allowed based on their dependency from claim 9.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON C FOX whose telephone number is (571)270-5016. The examiner can normally be reached M-F 9:00AM-6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRANDON C FOX/Examiner, Art Unit 2818
/DAVID VU/Primary Examiner, Art Unit 2818
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