Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Requirement for Information 37 CFR 1.105
The applicant notes “the request from the Office. Applicants respectfully submit that Applicants have provided all relevant information as required by the duty to disclose in 37 C.F.R. 1.56, and will continue to provide information when and if such information is identified, e.g., by Office Action in non-US jurisdictions, to the extent that this information is deemed relevant to patentability of the current application.” The examiner notes this is a requirement not a request.
In response to this requirement, please provide the title, citation and copy of each publication that any of the inventors relied upon to develop the disclosed subject matter that describes the invention, particularly as to developing the ferroelectric memory with a back gate. For each publication, please provide a concise explanation of the reliance placed on that publication in the development of the disclosed subject matter.
The applicant is reminded that the reply to this requirement must be made with candor and good faith under 37 CFR 1.56. Where the applicant does not have or cannot readily obtain an item of required information, a statement that the item is unknown or cannot be readily obtained may be accepted as a complete reply to the requirement for that item.
This requirement is an attachment of the enclosed Office action. A complete reply to the enclosed Office action must include a complete reply to this requirement. The time period for reply to this requirement coincides with the time period for reply to the enclosed Office action.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “transition region” must be shown in figures 2A and 2B (current figures 2A and 2B only show DTa or DTa1 or DTa2, which the specification describes as the transition distance) or the feature(s) canceled from the claim(s). No new matter should be entered.
Regarding claim 18, the drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “TAFE1>TTR” must be shown in or the feature(s) canceled from the claim(s). No new matter should be entered.
Regarding claim 19, the drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “TAFE1<TTR” must be shown in or the feature(s) canceled from the claim(s). No new matter should be entered.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “transition region” must be shown in figures 2A and 2B (current figures 2A and 2B only show DTa or DTa1 or DTa2, which the specification describes as the transition distance) or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1,2, 4-20 have been considered but are moot because the new 112a and 112b rejections presented below.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 2, 4-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The applicant’s original claim 1, filed 4/15/22, did not disclose “a transition region… and the transition region has a different atomic ratio of at least one of the atomic components”.
The applicant’s original claim 8, filed 4/15/22, did not disclose “a transition region… and the transition region has a different atomic ratio of at least one of the atomic components”.
The applicant’s original claim 14, filed 4/15/22, did not disclose “a transition region… and the transition region has a different atomic ratio of at least one of the atomic components”.
The applicant amended “a transition region” into claims 1, 8 and 14 on 9/26/25.
The applicant amended “and the transition region has a different atomic ratio of at least one of the atomic components” into claims 1, 8 and 14 on 4/8/25
The applicant alleges support for the amend can be found in paragraph [0030] and [0031] in the original specification, in the remarks filed 4/8/26. The applicant specifically alleges:
Support for this amendment is found at least in paragraph [0030] of the originally filed specification, which explicitly states that "the first anti-ferroelectric layer 110A, the ferroelectric layer 108, and, if present, the second anti-ferroelectric layer 110B, include the same atomic components. The atomic/molar ratios of those atomic components, however, differ between the first and second anti-ferroelectric layers 110A, 110B and the ferroelectric layer 108." Specification, paragraph [0030]. Additional support is found at least in paragraph [0031], which describes the transition distance (DTa) where "the concentration changing from that of the first anti- ferroelectric layer 110A to that of the ferroelectric layer 108." Specification, paragraph [0031].
Neither paragraph [0030] nor [0031] describe a transition region.
Paragraph [0031] does disclose a transition distance, but does not describe or define the transition distance as a “transition region”.
The Federal Circuit has held:
As we explained in Ariad, the written description inquiry looks to "the four corners of the specification" to discern the extent to which the inventor(s) had possession of the invention as broadly claimed. Ariad, 598 F.3d at 1351 ; see also Lockwood v. Am. Airlines, Inc., 107 F.3d 1565 , 1571 (Fed. Cir. 1997) ("It is the disclosures of the applications that count."). The knowledge of ordinary artisans may be used to inform what is actually in the specification, see Lockwood, 107 F.3d at 1571 , but not to teach limitations that are not in the specification, even if those limitations would be rendered obvious by the disclosure in the specification. Id. at 1571-72 .
Rivera v. Int'l Trade Comm'n, 857 F.3d 1315, 1322 (Fed. Cir. 2017)
In this case, it might be obvious that the transition distance would give support to the claimed transition region, but the specification as filed fails to teach the transition distance is the same as the transition region.
The examiner is not clear if the transition distance disclosed in para [0031] is larger than, smaller than or equal to the claimed “transition region”. Paragraph [0036] explicitly describes the transition region, but fails to define the transition distance is the “transition region”. The Federal Circuit has held “[t]he written description requirement is not met when… the specification provides at best disparate disclosures that an artisan might have been able to combine in order to make the claimed invention. Ariad Pharms., 598 F.3d at 1352“. Flash Control, LLC v. Intel Corp., No. 2020-2141, 2021 BL 262867, at *5, 2021 U.S.P.Q.2d 754 (Fed. Cir. July 14, 2021).
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 2, 4-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
MPEP 2173.01 discloses:
The first step to examining a claim to determine if the language is definite is to fully understand the subject matter of the invention disclosed in the application and to ascertain the boundaries of that subject matter encompassed by the claim. During examination, a claim must be given its broadest reasonable interpretation consistent with the specification as it would be interpreted by one of ordinary skill in the art. Because the applicant has the opportunity to amend claims during prosecution, giving a claim its broadest reasonable interpretation will reduce the possibility that the claim, once issued, will be interpreted more broadly than is justified. In re Yamamoto, 740 F.2d 1569, 1571, 222 USPQ 934, 936 (Fed. Cir. 1984); In re Zletz, 893 F.2d 319, 321, 13 USPQ2d 1320, 1322 (Fed. Cir. 1989)
The examiner is not clear if the transition distance (TDA) disclosed in para [0031] is larger than, smaller than or equal to the claimed “transition region”. The applicant has not defined the transition distance (TDA) as the “transition region”.
Paragraph [0036] explicitly describes the transition region, but fails to define the transition distance is the “transition region”.
The examiner will not address the amended limitation “forming a transition region between the buffer layer and the memory layer, wherein the transition region has substantially a same material as at least one of the buffer layer and the memory layer include the same atomic components, and the transition region includes the same atomic components as the buffer layer and the memory layer, and the transition region has a different concentration atomic ratio of at least one component of the atomic components relative to both the buffer layer and the memory layer” with respect to the prior art. MPEP 2173.06 discloses “[a]s stated in In reSteele, 305 F.2d 859, 134 USPQ 292 (CCPA 1962), a rejection under 35 U.S.C. 103 should not be based on considerable speculation about the meaning of terms employed in a claim or assumptions that must be made as to the scope of the claims.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, and 4 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Sharma et al. (US 2020/0091274).
Regarding claim 1, Sharma et al. disclose forming a back gate structure (105) on a substrate (101); forming a memory layer (107, bottom portion)[0036 discloses “the gate dielectric layer 107 may include multiple sublayers e.g., a first sublayer and a second sublayer, where the first sublayer or the second sublayer”] over the back gate structure gate structure; forming a buffer layer (top portion of 107) over the memory layer; forming a conductive channel (109) over the buffer layer; and forming source/drain (111/113) regions over the conductive channel (fig. 1).
Regarding claim 2, Sharma et al. disclose forming the buffer layer comprises depositing an anti-ferroelectric layer [0036, top portion of 107]; and forming the memory layer comprises depositing a ferroelectric layer [0036, bottom portion of 107].
Regarding claim 4, Sharma et al. disclose depositing the anti-ferroelectric layer further comprises depositing a first compound including hafnium, oxygen, and a first dopant selected from the group consisting of zirconium, silicon, and mixtures thereof (HfSiO)[0036, top portion of 107]; and depositing the ferroelectric layer further comprises depositing a second compound including hafnium, oxygen, and a second dopant selected from the group consisting of zirconium, silicon, and mixtures thereof (HfSiO)[0036, bottom portion of 107].
Claim Rejections - 35 USC § 102/Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharma et al. (US 2020/0091274) as applied to claim 4 above in view of Sharangpani et al. (US 2021/0050372).
Sharma disclose the invention supra.
Sharma fails to explicitly disclose depositing the first compound further comprises depositing the first dopant at a first concentration CD1; and depositing the second compound further comprises depositing the second dopant at a second concentration CD2, wherein an expression CD1> CD2 is satisfied.
Sharangpani et al. disclose the depositing the first compound further comprises depositing the first dopant at a first concentration CD1 [0204]( HfySi1-yO2, where 0<y<94) ; and depositing the second compound further comprises depositing the second dopant at a second concentration CD2[0204] (HfxSi1-xO2, where 0.94<x<0.97), wherein an expression CD1> CD2 is satisfied.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to combine the teachings of Sharma and Sharangpani et al. because the alternating stack of one or more antiferroelectric layers and one or more ferroelectric layers can generate a polarization-voltage curve having a greater hysteresis area than a single ferroelectric layer including the same amount of a ferroelectric material as the alternating stack [Sharangpani et al., 0197] and a broad range of hysteresis curves can be engineered for specific applications by tuning the thicknesses, materials, composition, number of layers, and process (e.g., anneal) conditions of the alternating stack of antiferroelectric layers and ferroelectric material layers [Sharangpani et al., 0199].
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharma et al. (US 2020/0091274) as applied to claim 4 above in view of Sharangpani et al. (US 2021/0050372).
Sharma disclose the invention supra.
Sharma fails to explicitly disclose depositing the first compound further comprises depositing the first dopant at a first concentration CD1; and depositing the second compound further comprises depositing the second dopant at a second concentration CD2, wherein a ratio of CD1: CD2 is at between 3:2 and 3:1.
Sharangpani et al. disclose the depositing the first compound further comprises depositing the first dopant at a first concentration CD1 [0204]( HfySi1-yO2, where 0<y<94) ; and depositing the second compound further comprises depositing the second dopant at a second concentration CD2[0204] (HfxSi1-xO2, where 0.94<x<0.97), wherein an expression CD1> CD2 is satisfied.
In this case, if x is .95 then the Si content would be .05 in the CD2, and the range of CD1 is HfySi1-yO2, where y is 0<y<94. The y is 0<y<94 would disclose compositions of .86=y to .89=y and result in Si cotent of .14 to .11 for CD1, which would disclose the ratio of CD1: CD2 is at between 3:2 and 3:1.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to form a ratio of CD1: CD2 is at between 3:2 and 3:1, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In Re Aller, 105 USPQ 233.
Moreover, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to combine the teachings of Sharma and Sharangpani et al. because the alternating stack of one or more antiferroelectric layers and one or more ferroelectric layers can generate a polarization-voltage curve having a greater hysteresis area than a single ferroelectric layer including the same amount of a ferroelectric material as the alternating stack [Sharangpani et al., 0197] and a broad range of hysteresis curves can be engineered for specific applications by tuning the thicknesses, materials, composition, number of layers, and process (e.g., anneal) conditions of the alternating stack of antiferroelectric layers and ferroelectric material layers [Sharangpani et al., 0199].
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharma et al. (US 2020/0091274) as applied to claim 4 above in view of Sharangpani et al. (US 2021/0050372).
Sharma disclose the invention supra.
Sharma fails to explicitly disclose depositing the first compound further comprises depositing the first dopant at a first concentration CD1sufficient to produce an anti-ferroelectric material; and depositing the second compound further comprises depositing the second dopant at a second concentration CD2 sufficient to produce a ferroelectric material.
Sharangpani et al. disclose the depositing the first compound further comprises depositing the first dopant at a first concentration CD1 [0204](antiferroelectric, HfySi1-yO2, where 0<y<94) ; and depositing the second compound further comprises depositing the second dopant at a second concentration CD2 [0204] (ferroelectric, HfxSi1-xO2, where 0.94<x<0.97), wherein an expression CD1> CD2 is satisfied.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to combine the teachings of Sharma and Sharangpani et al. because the alternating stack of one or more antiferroelectric layers and one or more ferroelectric layers can generate a polarization-voltage curve having a greater hysteresis area than a single ferroelectric layer including the same amount of a ferroelectric material as the alternating stack [Sharangpani et al., 0197] and a broad range of hysteresis curves can be engineered for specific applications by tuning the thicknesses, materials, composition, number of layers, and process (e.g., anneal) conditions of the alternating stack of antiferroelectric layers and ferroelectric material layers [Sharangpani et al., 0199].
Claim(s) 8 is/are rejected under 35 U.S.C. 102(a1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Sharma et al. (US 2020/0091274) in view of Sharangpani et al. (US 2021/0050372).
Sharma et al. disclose forming a back gate structure (105) on a substrate(101); forming a first buffer layer (107, bottom portion. The examiner understands layer 107 could be divided into a top portion a middle portion and a bottom portion)[0036 discloses “the gate dielectric layer 107 may include multiple sublayers”] over the back gate structure; forming a memory layer over the first buffer layer(107 middle portion); forming a second buffer layer over the memory layer(107 top portion); forming a conductive channel (109) over the second buffer layer; and forming source/drain regions (111/113) over the conductive channel.
Ad arguendo, Sharma et al. fails to explicitly disclose forming a first buffer layer forming a memory layer over the first buffer layer; forming a second buffer layer over the memory layer.
The examiner submits layer 107 could be divided into a top portion a middle portion and a bottom portion (first buffer layer)[0036 discloses “the gate dielectric layer 107 may include multiple sublayers”] over the back gate structure; forming a memory layer (middle layer of 107)over the first buffer layer; forming a second buffer layer (top layer of 107) over the memory layer.
Moreover, in view of Sharangpani et al. disclose forming a first buffer layer forming a memory layer over the first buffer layer; forming a second buffer layer over the memory layer [0203-0206](fig 20B).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to combine the teachings of Sharma and Sharangpani et al. because the alternating stack of one or more antiferroelectric layers and one or more ferroelectric layers can generate a polarization-voltage curve having a greater hysteresis area than a single ferroelectric layer including the same amount of a ferroelectric material as the alternating stack [Sharangpani et al., 0197] and a broad range of hysteresis curves can be engineered for specific applications by tuning the thicknesses, materials, composition, number of layers, and process (e.g., anneal) conditions of the alternating stack of antiferroelectric layers and ferroelectric material layers [Sharangpani et al., 0199].
The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art embodiment.
One of ordinary skill in the art could have combined the elements as claimed by known methods (i.e. using three sublayers instead of two), and that in combination, each element merely performs the same function as it does separately.
One of ordinary skill in the art would have recognized that the results of the combination were predictable. (The third sublayer would provide a diffusion barrier between the ferroelectric material and the back gate.)
Claim(s) 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharma et al. (US 2020/0091274) as applied to claim 8 above in view of Sharangpani et al. (US 2021/0050372).
Sharma et al. and Sharangpani et al. disclose the invention supra.
Sharma fails to explicitly disclose forming the first buffer layer comprises depositing a first anti-ferroelectric layer; forming the memory layer comprises depositing a ferroelectric layer; and forming the second buffer layer comprises depositing a second anti-ferroelectric layer.
Sharangpani et al. disclose disclose forming the first buffer layer comprises depositing a first anti-ferroelectric layer (154A); forming the memory layer comprises depositing a ferroelectric layer (154F); and forming the second buffer layer comprises depositing a second anti-ferroelectric layer (154A) (fig 20B).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to combine the teachings of Sharma and Sharangpani et al. because the alternating stack of one or more antiferroelectric layers and one or more ferroelectric layers can generate a polarization-voltage curve having a greater hysteresis area than a single ferroelectric layer including the same amount of a ferroelectric material as the alternating stack [Sharangpani et al., 0197] and a broad range of hysteresis curves can be engineered for specific applications by tuning the thicknesses, materials, composition, number of layers, and process (e.g., anneal) conditions of the alternating stack of antiferroelectric layers and ferroelectric material layers [Sharangpani et al., 0199].
Regarding claim 10, Sharangpani et al. disclose depositing the first anti-ferroelectric layer further comprises depositing a first compound including hafnium, oxygen, and a first dopant selected from the group consisting of zirconium, silicon, and mixtures thereof (154A) [0204](antiferroelectric, HfySi1-yO2,); depositing the ferroelectric layer further comprises depositing a second compound including hafnium, oxygen, and a second dopant selected from the group consisting of zirconium, silicon, and mixtures thereof (154F) [0204] (ferroelectric, HfxSi1-xO2); and depositing the second anti-ferroelectric layer further comprises depositing a third compound including hafnium, oxygen, and a third dopant selected from the group consisting of zirconium, silicon, and mixtures thereof (154A)[0204](antiferroelectric, HfySi1-yO2,) (fig 20B).
Regarding claim 11, Sharangpani et al. disclose depositing the first compound further comprises depositing the first dopant at a first concentration CD1 (154A)[0204](antiferroelectric, HfySi1-yO2, where 0<y<94) ;depositing the second compound further comprises depositing the second dopant at a second concentration CD2 (154F) (ferroelectric, HfxSi1-xO2, where 0.94<x<0.97); and depositing the third compound further comprises depositing the third dopant at a third concentration CD3(154A)[0204](antiferroelectric, HfySi1-yO2, where 0<y<94); wherein a first expression CD1> CD2and a second expression CD3> CD2 are satisfied (fig. 20B).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharma et al. (US 2020/0091274) as applied to claim 10 above in view of Sharangpani et al. (US 2021/0050372).
Sharma et al. and Sharangpani et al. disclose the invention supra.
Sharma et al. and Sharangpani et al. fail to explicitly disclose depositing the first compound further comprises depositing the first dopant at a first concentration CD1; depositing the second compound further comprises depositing the second dopant at a second concentration CD2; and depositing the third compound further comprises depositing the third dopant at a third concentration CD3, wherein a first ratio of CD1:CD2 is between 3:2 and 3:1 and a second ratio of CD3:CD2 is between 3:2 and 3:1.
Sharangpani et al. disclose depositing the first compound further comprises depositing the first dopant at a first concentration CD1 (154A)[0204](antiferroelectric, HfySi1-yO2, where 0<y<94) ;depositing the second compound further comprises depositing the second dopant at a second concentration CD2 (154F) (ferroelectric, HfxSi1-xO2, where 0.94<x<0.97); and depositing the third compound further comprises depositing the third dopant at a third concentration CD3(154A)[0204](antiferroelectric, HfySi1-yO2, where 0<y<94); wherein a first expression CD1> CD2and a second expression CD3> CD2 are satisfied (fig. 20B).
In this case, if x is .95 then the Si content would be .05 in the CD2, and the range of CD1 and CD3 is HfySi1-yO2, where y is 0<y<94. The y is 0<y<94 would disclose compositions of .86=y to .89=y and result in Si cotent of .14 to .11 for CD1, which would disclose the ratio of CD1: CD2 is at between 3:2 and 3:1.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to form a first ratio of CD1:CD2 is between 3:2 and 3:1 and a second ratio of CD3:CD2 is between 3:2 and 3:1, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In Re Aller, 105 USPQ 233.
Moreover, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to combine the teachings of Sharma and Sharangpani et al. because the alternating stack of one or more antiferroelectric layers and one or more ferroelectric layers can generate a polarization-voltage curve having a greater hysteresis area than a single ferroelectric layer including the same amount of a ferroelectric material as the alternating stack [Sharangpani et al., 0197] and a broad range of hysteresis curves can be engineered for specific applications by tuning the thicknesses, materials, composition, number of layers, and process (e.g., anneal) conditions of the alternating stack of antiferroelectric layers and ferroelectric material layers [Sharangpani et al., 0199].
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharma et al. (US 2020/0091274) as applied to claim 10 above in view of Sharangpani et al. (US 2021/0050372).
Sharma et al. and Sharangpani et al. disclose the invention supra.
Sharma et al. and Sharangpani et al. fail to explicitly disclose depositing the first compound further comprises forming a first layer thickness of TC1;depositing the second compound further comprises forming a second layer thickness of TC2; and depositing the third compound further comprises forming a third layer thickness of TC3, wherein a first ratio of TC1: TC2 is between 1:100 and 1:8 and wherein a second ratio of TC3 : TC2 is between 1:100 and 1:8.
Sharangpani et al. discloses each antiferroelectric layer can have a thickness that is 10% of the thickness of each ferroelectric layer [0197,0206]. The examiner submits TC1 and TC3 would be the antiferroelectric layer.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to form a first ratio of TC1: TC2 is between 1:100 and 1:8 and wherein a second ratio of TC3 : TC2 is between 1:100 and 1:8., since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In Re Aller, 105 USPQ 233.
Moreover, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to combine the teachings of Sharma and Sharangpani et al. because the alternating stack of one or more antiferroelectric layers and one or more ferroelectric layers can generate a polarization-voltage curve having a greater hysteresis area than a single ferroelectric layer including the same amount of a ferroelectric material as the alternating stack [Sharangpani et al., 0197] and a broad range of hysteresis curves can be engineered for specific applications by tuning the thicknesses, materials, composition, number of layers, and process (e.g., anneal) conditions of the alternating stack of antiferroelectric layers and ferroelectric material layers [Sharangpani et al., 0199].
Claim(s) 14 is/are rejected under 35 U.S.C. 102(a1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Sharma et al. (US 2020/0091274) in view of Sharangpani et al. (US 2021/0050372).
Sharma et al. disclose forming a back gate structure (105) on a substrate(101); forming a first buffer layer (107, bottom portion. The examiner understands layer 107 could be divided into a top portion a middle portion and a bottom portion)[0036 discloses “the gate dielectric layer 107 may include multiple sublayers”] over the back gate structure; forming a memory layer over the first buffer layer (107 middle portion); forming a second buffer layer over the memory layer (107 top portion); forming a conductive channel (109) over the second buffer layer; and forming source/drain regions (111/113) over the conductive channel.
Ad arguendo, Sharma et al. fails to explicitly disclose forming a first buffer layer forming a memory layer over the first buffer layer; forming a second buffer layer over the memory layer.
The examiner submits layer 107 could be divided into a top portion a middle portion and a bottom portion (first buffer layer)[0036 discloses “the gate dielectric layer 107 may include multiple sublayers”] over the back gate structure; forming a memory layer (middle layer of 107)over the first buffer layer; forming a second buffer layer (top layer of 107) over the memory layer.
Moreover, in view of Sharangpani et al. disclose forming a first buffer layer forming a memory layer over the first buffer layer; forming a second buffer layer over the memory layer [0203-0206](fig 20B).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to combine the teachings of Sharma and Sharangpani et al. because the alternating stack of one or more antiferroelectric layers and one or more ferroelectric layers can generate a polarization-voltage curve having a greater hysteresis area than a single ferroelectric layer including the same amount of a ferroelectric material as the alternating stack [Sharangpani et al., 0197] and a broad range of hysteresis curves can be engineered for specific applications by tuning the thicknesses, materials, composition, number of layers, and process (e.g., anneal) conditions of the alternating stack of antiferroelectric layers and ferroelectric material layers [Sharangpani et al., 0199].
The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art embodiment.
One of ordinary skill in the art could have combined the elements as claimed by known methods (i.e. using three sublayers instead of two), and that in combination, each element merely performs the same function as it does separately.
One of ordinary skill in the art would have recognized that the results of the combination were predictable. (The third sublayer would provide a diffusion barrier between the ferroelectric material and the back gate.)
Regarding claim 17, Sharangpani et al. disclose the first anti-ferroelectric layer further comprises an antiferroelectric first compound including hafnium, oxygen, and a first dopant selected from the group consisting of zirconium, silicon, and mixtures thereof (154A) [0204](antiferroelectric, HfySi1-yO2,); the ferroelectric layer further comprises depositing a second compound including hafnium, oxygen, and a second dopant selected from the group consisting of zirconium, silicon, and mixtures thereof (154F) [0204] (ferroelectric, HfxSi1-xO2).
Regarding claim 18, Sharangpani et al. disclose a first transition region between the first anti-ferroelectric layer and the ferroelectric layer has a thickness TTR wherein an expressionTAFE1>TTR is satisfied [0206, 0209]. Paragraph [0206] discloses one ferroelectric material layer 154F can be 5 nm and one antiferroelectric material layer 154A may have a thickness of 0.5 nm. Paragraph [0209] discloses 154B can be formed by a conformal deposition process such as chemical vapor deposition, and can have a thickness of 1 nm. (Element 154B is the transition region as shown in figure 20D.)
Regarding claim 19, Sharangpani et al. disclose a first transition region between the first anti-ferroelectric layer and the ferroelectric layer has a thickness TTR wherein an expressionTAFE1<TTR is satisfied [0206, 0209]. Paragraph [0206] discloses one ferroelectric material layer 154F can be 15 nm and one antiferroelectric material layer 154A may have a thickness of 3 nm. Paragraph [0209] discloses 154B can be formed by a conformal deposition process such as chemical vapor deposition, and can have a thickness of 1 nm. (Element 154B is the transition region as shown in figure 20D.)
Claim(s) 15-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharma et al. (US 2020/0091274) as applied to claim 14 above in view of Sharangpani et al. (US 2021/0050372).
Sharma et al. and Sharangpani et al. disclose the invention supra.
Sharma et al. and Sharangpani et al. fail to explicitly disclose a first anti-ferroelectric layer having a first thickness TAFE1; and the memory layer comprises a ferroelectric layer having a second thickness TFE, wherein a ratio of TAFE1 : TFE is between 1:100 and 1:8.
Sharangpani et al. discloses each antiferroelectric layer can have a thickness that is 10% of the thickness of each ferroelectric layer [0197, 0206]. The examiner submits TAFE1 would be the antiferroelectric layer.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to form disclose a first anti-ferroelectric layer having a first thickness TAFE1; and the memory layer comprises a ferroelectric layer having a second thickness TFE, wherein a ratio of TAFE1 : TFE is between 1:100 and 1:8., since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In Re Aller, 105 USPQ 233.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to combine the teachings of Sharma and Sharangpani et al. because the alternating stack of one or more antiferroelectric layers and one or more ferroelectric layers can generate a polarization-voltage curve having a greater hysteresis area than a single ferroelectric layer including the same amount of a ferroelectric material as the alternating stack [Sharangpani et al., 0197] and a broad range of hysteresis curves can be engineered for specific applications by tuning the thicknesses, materials, composition, number of layers, and process (e.g., anneal) conditions of the alternating stack of antiferroelectric layers and ferroelectric material layers [Sharangpani et al., 0199].
Regarding claim 16, Sharangpani et al. discloses each antiferroelectric layer can have a thickness that is 10% of the thickness of each ferroelectric layer [0197, 0206]. The examiner submits both ferroelectric layers (TAFE1 and TAFE2) would be the same thickness (i.e. 1:1) which would be between 1:3 and 3:1.
Regarding claim 17, Sharangpani et al. disclose the first anti-ferroelectric layer further comprises an antiferroelectric first compound including hafnium, oxygen, and a first dopant selected from the group consisting of zirconium, silicon, and mixtures thereof (154A) [0204](antiferroelectric, HfySi1-yO2,); the ferroelectric layer further comprises depositing a second compound including hafnium, oxygen, and a second dopant selected from the group consisting of zirconium, silicon, and mixtures thereof (154F) [0204] (ferroelectric, HfxSi1-xO2).
Regarding claim 18, Sharangpani et al. disclose a first transition region between the first anti-ferroelectric layer and the ferroelectric layer has a thickness TTR wherein an expressionTAFE1>TTR is satisfied [0206, 0209]. Paragraph [0206] discloses one ferroelectric material layer 154F can be 5 nm and one antiferroelectric material layer 154A may have a thickness of 0.5 nm. Paragraph [0209] discloses 154B can be formed by a conformal deposition process such as chemical vapor deposition, and can have a thickness of 1 nm. (Element 154B is the transition region as shown in figure 20D.)
Regarding claim 19, Sharangpani et al. disclose a first transition region between the first anti-ferroelectric layer and the ferroelectric layer has a thickness TTR wherein an expression TAFE1<TTR is satisfied [0206, 0209]. Paragraph [0206] discloses one ferroelectric material layer 154F can be 15 nm and one antiferroelectric material layer 154A may have a thickness of 3 nm. Paragraph [0209] discloses 154B can be formed by a conformal deposition process such as chemical vapor deposition, and can have a thickness of 1 nm. (Element 154B is the transition region as shown in figure 20D.)
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharma et al. (US 2020/0091274) as applied to claim 17 above in view of Sharangpani et al. (US 2021/0050372).
Sharma et al. and Sharangpani et al. disclose the invention supra.
Sharma et al. and Sharangpani et al. fail to explicitly disclose the first compound comprises a first dopant concentration CD1; and the second compound comprises a second dopant concentration CD2, wherein CD1 is no greater than 70 at.% and CD2 is no greater than 30 at% and further wherein a first ratio of CD1 : CD2 is between 3:2 and 3:1.
Sharangpani et al. disclose depositing the first compound further comprises depositing the first dopant at a first concentration CD1 (154A)[0204](antiferroelectric, HfySi1-yO2, where 0<y<94) ;depositing the second compound further comprises depositing the second dopant at a second concentration CD2 (154F) (ferroelectric, HfxSi1-xO2, where 0.94<x<0.97); and depositing the third compound further comprises depositing the third dopant at a third concentration CD3(154A)[0204](antiferroelectric, HfySi1-yO2, where 0<y<94); wherein a first expression CD1> CD2and a second expression CD3> CD2 are satisfied (fig. 20B).
In this case, if x is .95 then the Si content would be .05 in the CD2, and the range of CD1 and CD3 is HfySi1-yO2, where y is 0<y<94. The y is 0<y<94 would disclose compositions of .86=y to .89=y and result in Si cotent of .14 to .11 for CD1, which would disclose the ratio of CD1: CD2 is at between 3:2 and 3:1 and CD1 is no greater than 70 at.% and CD2 is no greater than 30 at%.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to form a first ratio of CD1:CD2 is between 3:2 and 3:1 and CD1 is no greater than 70 at.% and CD2 is no greater than 30 at%, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In Re Aller, 105 USPQ 233.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to combine the teachings of Sharma and Sharangpani et al. because the alternating stack of one or more antiferroelectric layers and one or more ferroelectric layers can generate a polarization-voltage curve having a greater hysteresis area than a single ferroelectric layer including the same amount of a ferroelectric material as the alternating stack [Sharangpani et al., 0197] and a broad range of hysteresis curves can be engineered for specific applications by tuning the thicknesses, materials, composition, number of layers, and process (e.g., anneal) conditions of the alternating stack of antiferroelectric layers and ferroelectric material layers [Sharangpani et al., 0199].
Conclusion
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/BRADLEY SMITH/Primary Examiner, Art Unit 2817
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