Prosecution Insights
Last updated: October 02, 2026
Application No. 17/722,302

INTERCONNECT STRUCTURE AND METHODS OF FORMING THE SAME

Final Rejection §102§103§112
Filed
Apr 16, 2022
Priority
Jan 12, 2022 — provisional 63/298,792
Examiner
KHALIFA, MOATAZ
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
5 (Final)
91%
Grant Probability
Favorable
6-7
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
60 granted / 66 resolved
+22.9% vs TC avg
Minimal +2% lift
Without
With
+2.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
36 currently pending
Career history
112
Total Applications
across all art units

Statute-Specific Performance

§103
74.2%
+34.2% vs TC avg
§102
18.7%
-21.3% vs TC avg
§112
4.6%
-35.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 66 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Remarks The 06/04/2026 amendments of claims 16, 21 and 29 have been noted and entered. Response to Arguments Applicant’s arguments, see Remarks pages 6-10, filed 06/04/2026, with respect to the rejection(s) of claim(s) 16-35 under 35 U.S.C. 102 and 103 have been fully considered and are persuasive in light of the newly added amendments. However, upon further consideration, a new ground(s) of rejection is made in view of Lee et al, US 20170229372 A1 (Lee ‘372). New Grounds of Rejection The new grounds of rejection, prior art references Lee et al, US 20170229372 A1 (Lee ‘372) appears below. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 23 recites the limitations: " the first portion of the first conductive layer " (emphasis added) in lines 1-2 of the claim and “the second portion of the first conductive layer” (emphasis added) in lines 2-3 of the claim. There is insufficient antecedent basis for these limitations in the claim. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al, US 20170229372 A1 (Lee ‘372) Regarding claim 16; Lee ‘372 teaches a method, comprising: forming a first dielectric layer (Lee ‘372: Annotated Fig (2E) shared in this OA: 108) over a second dielectric layer (104), wherein a first conductive feature (102b) and a second conductive feature (102a) are formed in the second dielectric layer (104); forming first (112B+110B) and second (112A+110A) openings in the first dielectric layer (108), wherein the first (112B+110B) and second (112A+110A) openings have different bottom critical dimensions (bottom dimensions of 112B+110B and 112A+110A as seen in Fig (2E)); forming a first conductive layer (202) on the first conductive feature (102b) in the first opening (112B) and on the first dielectric layer (108) in the second opening (112A), wherein the first conductive layer (202) comprises a two-dimensional material ([0039]: “… In some embodiments, the material and formation method of the barrier layer 202 are similar to or the same as those of the barrier layer 114.” In combination with [0025]: “ In some embodiments, the barrier layer 114 is made of titanium nitride (TiN), tantalum nitride (TaN), Ta, Ti, TiW, another suitable material, or a combination thereof. The glue layer may be made of Ta, Ti, another suitable material, or a combination thereof.” It is noted that TiN and TiW are considered two-dimensional materials); forming a second conductive layer (206+204A+204B) on the first conductive layer (202), wherein the second conductive layer (206+204A+204B) extends across a top of the first opening from a first end to a second end opposite the first end (see annotated Fig (2E) shared in this OA), and the second conductive layer (206+204A+204B) is a conformal layer in the second opening (112A+110A); and forming a third conductive layer (208) on the second conductive layer (206), wherein the third conductive layer (208) ([0042]: “As shown in FIG. 2E, a conductive layer 208 is deposited.”) is formed over the first opening (112B+110B) and fills the second opening (112A+110A). PNG media_image1.png 554 732 media_image1.png Greyscale Regarding claim 17; Lee ‘372 teaches all the limitations of the method of claim 16. Further, Lee ‘372 teaches wherein forming the first conductive layer (Lee ‘372: Annotated Fig (2E) shared in this OA: 202) comprises forming a plurality of two-dimensional material layers ([0039]: “… In some embodiments, the material and formation method of the barrier layer 202 are similar to or the same as those of the barrier layer 114.” In combination with [0024]: “….the barrier layer 114 includes multiple sub-layers…” It is noted that TiN and TiW are considered two-dimensional materials). Regarding claim 18; Lee ‘372 teaches all the limitations of the method of claim 17. Further, Lee ‘372 teaches wherein forming the first (Lee ‘372: Annotated Fig (2E) shared in this OA: 112B+110B) and second (112A+110A) openings in the first dielectric layer (108) exposes a first (102b) and second (102a) conductive features disposed in the second dielectric layer (104), respectively. Regarding claim 19; Lee ‘372 teaches all the limitations of the method of claim 18. Further, Lee ‘372 teaches wherein the plurality of two-dimensional material layers (Lee ‘372: Annotated Fig (2E) shared in this OA: 202) are selectively formed on dielectric surfaces of the first dielectric layer (108). Regarding claim 20; Lee ‘372 teaches all the limitations of the method of claim 16. Further, Lee ‘372 teaches wherein the second conductive layer (Lee ‘372: Annotated Fig (2E) shared in this OA: 206+204A+204B, [0028] and [0040]-[0041]) and the third conductive layer (208, [0032] and [0042]) are formed by different processes. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s). Claims 21-22, 24, and 26-28 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al, US 20170229372 A1 (Lee ‘372) in view of Lee et al, US 20220068805 A1 (Lee ‘805). Regarding claim 21; Lee ‘372 teaches a method, comprising: depositing a dielectric layer (Lee ‘372: Annotated Fig (2E) shared in this OA: 108) over a first conductive feature (102b) and a second conductive feature (102a); forming first (112B+110B) and second (112A+110A) openings in the dielectric layer (108) to expose the first (102b) and second (102a) conductive features, respectively; forming a first conductive layer (202) on the first conductive feature (102b) in the first opening (112B+110A) and on the dielectric layer (108) in the second opening (112A+110A), wherein the first conductive layer (202) comprises a two-dimensional material ([0039]: “… In some embodiments, the material and formation method of the barrier layer 202 are similar to or the same as those of the barrier layer 114.” In combination with paragraph [0025]: “ In some embodiments, the barrier layer 114 is made of titanium nitride (TiN), tantalum nitride (TaN), Ta, Ti, TiW, another suitable material, or a combination thereof. The glue layer may be made of Ta, Ti, another suitable material, or a combination thereof.” It is noted that TiN and TiW are considered two-dimensional materials), and a first thickness of a first portion of the first conductive layer formed on the first conductive feature is less than a second thickness of a second portion of the first conductive layer formed on a sidewall of the dielectric layer; depositing a second conductive layer (206+204A+204B) on the first conductive layer (202) in the first (112B+110B) and second (112A+110A) openings, wherein the second conductive layer (206+204A+204B) extends across a top of the first opening (112B+110B) from a first end to a second end opposite the first end (see annotated Fig (2E) shared in this OA), and depositing a third conductive layer (208) on the second conductive layer (206), wherein the third conductive layer (208) is formed over the first opening (112B+110B) and fills the second opening (112A+110A). Lee ‘372 does not teach a first thickness of a first portion of the first conductive layer formed on the first conductive feature is less than a second thickness of a second portion of the first conductive layer formed on a sidewall of the dielectric layer. However, Lee ‘805 teaches a first thickness T2 of a first portion (Lee “805: Fig (26): lower portion of (BAP2) in the via) of the first conductive layer (BAP2) formed on the first conductive feature (FM2) is less than a second thickness T5 of a second portion (side portion of BPA2) of the first conductive layer (BPA2) formed on a sidewall of the dielectric layer (BAP1, [0083] and [0127]). Lee ‘372 and Lee ‘805 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lee ‘372 by introducing the reduced thickness of the first conductive layer on the first conductive feature as disclosed in Lee ‘805 to establish a better electrical connection with first conductive feature. PNG media_image2.png 920 623 media_image2.png Greyscale Regarding claim 22; Lee ‘372 in view of Lee ‘805 teach all the limitations of the method of claim 21. Lee ‘372 does not teach wherein the first thickness is less than half of the second thickness. However, Lee ‘805 does suggest adjusting thickness to achieve a desired voltage (Lee “805: [0042]). Lee ‘372 and Lee ‘805 are considered analogous art. Therefore, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art before the invention was filed to adjust the thickness of the conductive layer of Lee ‘372 in order to achieve a desired voltage, as suggested by Lee ‘805 ([0042]). Regarding claim 24; Lee ‘372 in view of Lee ‘805 teach all the limitations of the method of claim 21. Further, Lee ‘372 teaches wherein the first conductive layer (Lee ‘372: Annotated Fig (2E): 202) comprises a plurality of two-dimensional material layers ([0039]: “… In some embodiments, the material and formation method of the barrier layer 202 are similar to or the same as those of the barrier layer 114.” In combination with [0025]: “In some embodiments, the barrier layer 114 is made of titanium nitride (TiN), tantalum nitride (TaN), Ta, Ti, TiW, another suitable material, or a combination thereof. The glue layer may be made of Ta, Ti, another suitable material, or a combination thereof.” It is noted that TiN and TiW are considered two-dimensional materials). Regarding claim 26; Lee ‘372 in view of Lee ‘805 teach all the limitations of the method of claim 21. Further, Lee ‘372 teaches wherein the second conductive layer (Lee ‘372: Annotated Fig (2E): 206+204A+204B) is deposited by atomic layer deposition ([0041]: “As shown in FIG. 2D, a catalyst layer 206 is deposited over the sidewalls and bottoms of the trenches 112A and 112B, in accordance with some embodiments. In some embodiments, the material and formation method of the catalyst layer 206 are similar to or the same as those of the catalyst layer 116.” in combination [0028]: “… In some embodiments, the catalyst layer 116 includes copper (Cu), nickel (Ni), platinum (Pt), cobalt (Co), ruthenium (Ru), another suitable material, or a combination thereof. In some other embodiments, the catalyst layer 116 is made of Cu, Ni, Pt, Co, Ru, another suitable material, or a combination thereof. In some embodiments, the catalyst layer 116 is deposited using a PVD process, a CVD process, an electroplating process, an electroless plating process, an ALD process, another applicable process, or a combination thereof.”) Regarding claim 27; Lee ‘372 in view of Lee ‘805 teach all the limitations of the method of claim 26. Further, Lee ‘372 teaches wherein the third conductive layer (Lee ‘372: Annotated Fig (2E): 208) is deposited by physical vapor deposition or electro-chemical plating ([0042]: “… In some embodiments, the material and formation method of the conductive layer 208 are similar to or the same as those of the conductive layer 118.” In combination with [0032]: “In some embodiments, the conductive layer 118 is deposited using a CVD process, an ALD process, an electroplating process, an electroless plating process, a PVD process, another applicable process, or a combination thereof.”). Regarding claim 28; Lee ‘372 in view of Lee ‘805 teach all the limitations of the method claim 21. Further, Lee ‘372 teaches wherein the first (Lee ‘372: Annotated Fig (2E): 112B+110B) and second (112A+110A) openings have different bottom critical dimensions (bottom dimensions of 112A+110A and 112B+110B in Fig (2E)). Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al, US 20170229372 A1 (Lee ‘372) in view of Lee et al, US 20220068805 A1 (Lee ‘805) in further view of Yang Gao, Yang Liu, “Zheng Liu, Controllable growth of two-dimensional materials on noble metal substrates”, iScience, Volume 24, Issue 12, 2021, 103432, ISSN 2589-0042 (Gao) Regarding claim 23; Lee ‘372 in view of Lee ‘805 teach all the limitations of the method of claim 21. Lee ‘372 in view of Lee ‘805 does not teach wherein a growth rate of the first portion of the first conductive layer is slower than a growth rate of the second portion of the first conductive layer. Gao teaches wherein a growth rate of the first portion of the first conductive layer (Gao: Fig (6I) : dielectric materials SiO2) is lower than a growth rate of the second portion (Au) of the first conductive layer (Gao: Page 8 Lines: 36-41: “Au substrates have also been used to grow large area single-crystal WSe2 domains (Figure 6I) and show the unique ability to speed up the growth rate of WSe2 by several orders of magnitude faster than those of conventional growth of 2D TMDCs on SiO2/Si and other nonmetal substrates (Gao et al., 2017). Although the WSe2 grows on Au is up to ~26 µms-1 at 950 C⁰, the extract carrier mobility ~143 cm2V-1s-1 indicates that the quality is not sacrificed even after the growth at a remarkably high rate”). Lee ‘372 in view of Lee ‘805 and Gao are considered analogous art given that they both describe in some aspects the growth of a 2D material layer on different surfaces. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, that the growth rate of the 2D material on the metal surface is slower than on the dielectric surface given the interactions and strong binding between the metal atoms and the 2D material atoms slowing down the spread and organization of the 2D atoms into a structured monolayer as disclosed in Gao. Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al, US 20170229372 A1 (Lee ‘372) in view of Lee et al, US 20220068805 A1 (Lee ‘805) in further view of Sharma, US 20210090991 A1 (Sharma) Regarding claim 25; Lee ‘372 in view of Lee ‘805 teach all the limitations of the method of claim 24. Lee ‘372 in view of Lee ‘685 does not teach wherein the plurality of two-dimensional material layers comprises three to six two-dimensional material layers. Sharma teaches wherein the plurality of two-dimensional material layers comprises three to six two-dimensional material layers (Sharma: [0041]: “In one embodiment, the 2D crystalline liner 160 is a monolayer. In one embodiment, the 2D crystalline liner 160 has a thickness of less than 5 nanometers.”). Lee ‘372 in view of Lee ‘805 and Sharma are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to one of ordinary skill in the art at the time of filing this application to modify Lee ‘372 in view of Lee ‘805 by introducing the thickness of the 2D material disclosed in Sharma to optimize the resistivity of the 2D stack of layers to be at its minimum. Claims 29-31 and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al, US 20170229372 A1 (Lee ‘372) in view of Yang et al, US 20210082829 A1 (Yang). Regarding claim 29; Lee ‘372 teaches a method, comprising: depositing a first dielectric layer (Lee ‘372: Annotated Fig (2E) shared in this OA: 104) over a first conductive feature (102b), a second conductive feature (102a), and a second dielectric layer (108); forming first (112B+110B) and second openings (112A+110A) in the dielectric layer (108), wherein the first conductive feature (102b) is exposed in the first opening (112B+110B), and the second conductive feature (102a) and a portion of the second dielectric layer (108) are exposed in the second opening (112A+110A); forming a first conductive layer (202) on the first conductive feature (102b) in the first opening (112B+110B) and on the first dielectric layer (104) in the second opening (112A+110A), wherein the first conductive layer (202) comprises a two-dimensional material ([0039]: “… In some embodiments, the material and formation method of the barrier layer 202 are similar to or the same as those of the barrier layer 114.” In combination with [0025]: “In some embodiments, the barrier layer 114 is made of titanium nitride (TiN), tantalum nitride (TaN), Ta, Ti, TiW, another suitable material, or a combination thereof. The glue layer may be made of Ta, Ti, another suitable material, or a combination thereof.” It is noted that TiN and TiW are considered two-dimensional materials), the first conductive layer (202) is disposed on the exposed portion of the second dielectric layer (108) and edge portions of the second conductive feature, and a center portion of the second conductive feature (102a) is exposed; depositing a second conductive layer (206+204A+204B) on the first conductive layer (202) in the first (112B+110B) and second (112A+110A) openings, wherein the second conductive layer (206+204A+204B) is deposited on the exposed center portion of the second conductive feature (102a) and extends across a top of the first opening (112B+110B) from a first end to a second end opposite the first end; and depositing a third conductive layer (208) on the second conductive layer (206+204A+204B), wherein the third conductive layer (208) fills the second opening (112A+110A). Lee ‘372 does not teach the first conductive layer covering the edge portions of the second conductive feature. However, Yang teaches the first conductive layer (Yang: Fig (8): 226) covering the edge portions of the second conductive feature (bottom part of 221). Lee ‘372 and Yang are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lee ‘372 by introducing the 2D material covering the edges of the second conductive feature as disclosed in Yang to improve the connection between the 2D material and the conductive feature. PNG media_image3.png 654 797 media_image3.png Greyscale Regarding claim 30; Lee ‘372 in view of Yang teaches all the limitations of the method of claim 29. Further, Lee ‘372 teaches further comprising depositing an etch stop layer (Lee ‘372: Annotated Fig (2E) shared in this OA: 106) on the first conductive feature (102b), the second conductive feature (102a), and the second dielectric layer (108), and the first dielectric layer (104) is deposited on the etch stop layer (106). Regarding claim 31; Lee ’372 in view of Yang teaches all the limitations of the method of claim 30. Further, Lee ‘372 teaches wherein the first (Lee ‘372: Annotated Fig (3E) shared in this OA: 112B+110B) and second (112A+110A) openings are formed in the etch stop layer (106). Regarding claim 35; Lee ’372 in view of Yang teach all the limitations of the method of claim 29. Further, Lee ‘372 teaches wherein the second (Lee ‘372: Annotated Fig (2E) shared in this OA: 206+204A+204B) and third (208) conductive layers comprise different materials ([0042]: “… In some embodiments, the material and formation method of the conductive layer 208 are similar to or the same as those of the conductive layer 118.” In combination with [0032]: “ In some embodiments, the conductive layer 118 includes graphene, doped graphene, graphene oxide, graphene-containing compound, transition-metal chalcogenide, boron nitride, another suitable material, or a combination thereof. In some other embodiments, the conductive layer 118 is made of graphene, doped graphene, graphene oxide, graphene-containing compound, transition-metal chalcogenide, boron nitride, another suitable material, or a combination thereof.”, see also [0041]: “… In some embodiments, the material and formation method of the catalyst layer 206 are similar to or the same as those of the catalyst layer 116.” [0028]: “In some embodiments, the catalyst layer 116 is electrically conductive. In some embodiments, the catalyst layer 116 is made of a material that is different from that of the conductive layer 118. In some embodiments, the catalyst layer 116 includes copper (Cu), nickel (Ni), platinum (Pt), cobalt (Co), ruthenium (Ru), another suitable material, or a combination thereof. In some other embodiments, the catalyst layer 116 is made of Cu, Ni, Pt, Co, Ru, another suitable material, or a combination thereof.”). The different embodiments disclosed in Lee ‘372 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify the first embodiment of Lee ‘372 by making the first and second conductive layers of different materials to enhance their binding ability and reduce their contact resistance leading to a more efficient device in terms of power consumption and performance. Claims 32 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al, US 20170229372 A1 (Lee ‘372) in view of Yang et al, US 20210082829 A1 (Yang) in further view of Empante et al, “Chemical Vapor Deposition Growth of Few-Layer MoTe2 in the 2H, 1T′, and 1T Phases: Tunable Properties of MoTe2 Films”, ACS Nano 2017, 11, 1, 900–905 (Empante). Regarding claim 32; Lee ’372 in view of Yang teach all the limitations of the method of claim 29. Lee ‘372 teaches wherein the first conductive layer (Lee ‘372: Annotated Fig (2E): 202) further comprises CrSe2, CrTe2, VS2, VSe2, VTe2, TaS2, TaSe2, TaTe2, MoS2, MoSe2, MoTe2, NbS2, NbSe2, NbTe2, WS2, WSe2, WTe2, TiS2, TiSe2, or TiTe2. However, Lee ‘372 teaches the use of conductive layer ([0039: “… In some embodiments, the material and formation method of the barrier layer 202 are similar to or the same as those of the barrier layer 114.” In combination with [0025]: “In some embodiments, the barrier layer 114 is made of titanium nitride (TiN), tantalum nitride (TaN), Ta, Ti, TiW, another suitable material, or a combination thereof. The glue layer may be made of Ta, Ti, another suitable material, or a combination thereof.” It is noted that TiN and TiW are considered two-dimensional materials). But Lee ‘372 in view of Yang does not teach the specific materials disclosed above. Empante describes the desirable characteristics of MoTe2 (Empante: Conclusion section of Empante: “CVD growth of MoTe2 can provide a material with tunable semiconducting and metallic properties. Hybrid/mixed phases can yield low-resistance gateable semiconducting 2D films.”, therefore suggesting it can be used for conductive layer). Lee ‘372 in view of Yang and Empante are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lee ‘372 in view of Yang by using MoTe2 as the material used in constructing the first conductive layer to utilize the tunable nature of the material leading to a lower resistance layer which would lead to a more efficient device. Claims 33 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al, US 20170229372 A1 (Lee ‘372) in view of Yang et al, US 20210082829 A1 (Yang) in further view of Kim et al, KR 20200142612 A (Kim). Regarding claim 33; Lee ’372 in view of Yang teaches all the limitations of claim 29. Lee ‘372 teaches wherein the first conductive layer (Lee ‘372: Annotated Fig (2E): 202) further comprises S, Se, Te, FeS, FeSe, BP, Mo2C, Si, Ge, or Sn. However, Lee ‘372 teaches the use of conductive layer ([0039]: “… In some embodiments, the material and formation method of the barrier layer 202 are similar to or the same as those of the barrier layer 114.” In combination with [0025]: “In some embodiments, the barrier layer 114 is made of titanium nitride (TiN), tantalum nitride (TaN), Ta, Ti, TiW, another suitable material, or a combination thereof. The glue layer may be made of Ta, Ti, another suitable material, or a combination thereof.” It is noted that TiN and TiW are considered two-dimensional materials). But Lee ‘372 in view of Yang does not teach the specific materials disclosed above. Kim teaches teach wherein the first conductive layer (Kim: Fig (13): 121) further comprises Sn (see Page: 6 Lines:9-12 of the translation of the specification of Kim attached to this OA: “"In some other embodiments, the via conductive layer is, for example, carbon (C), silver (Ag), cobalt (Co), tantalum (Ta), indium (In), tin (Sn), zinc (Zn), manganese ( At least one of Mn), titanium (Ti), magnesium (Mg), chromium (Cr), germanium (Ge), strontium (Sr), platinum (Pt), magnesium (Mg), aluminum (Al), or zirconium (Zr)".). Lee ‘372 in view of Yang and Kim are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lee ‘372 in view of Yang by using Sn disclosed in Kim to lower the resistivity of the conductive layer leading to a more efficient device. Claim 34 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al, US 20170229372 A1 (Lee ‘372) in view of Yang et al, US 20210082829 A1 (Yang) in further view of Zope et al, US 20190067094 A1 (Zope) Regarding claim 34; Lee ‘372 in view of Yang teaches all the limitations of the method of claim 29. Lee ‘372 teaches wherein the first conductive layer (Lee ‘372: 202) further comprises graphene. However, Lee ‘372 teaches a first conductive layer (202, [0039]: “… In some embodiments, the material and formation method of the barrier layer 202 are similar to or the same as those of the barrier layer 114.” In combination with [0025]: “In some embodiments, the barrier layer 114 is made of titanium nitride (TiN), tantalum nitride (TaN), Ta, Ti, TiW, another suitable material, or a combination thereof. The glue layer may be made of Ta, Ti, another suitable material, or a combination thereof.” It is noted that TiN and TiW are considered two-dimensional materials sharing this property with graphene which makes it a possibility to use graphene for layer 202 as “another suitable material”) further comprises graphene, and first conductive layer is deposited by a water-assisted chemical vapor deposition process Yang teaches the first conductive layer (Yang: Fig (8): 226) comprises graphene. Lee ‘372 and Yang are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lee ‘372 by constructing the first conductive layer out of graphene as disclosed in Yang to improve the conductivity and reduce the resistivity of the first conductive layer leading to a more efficient device. Lee ‘372 in view of Yang does not teach the first conductive layer is deposited by a water-assisted chemical vapor deposition process. However, Zope teaches the first conductive layer is deposited by a water-assisted chemical vapor deposition process (Zope: [0084]: “In embodiments wherein the nucleation film comprises an oxide, such as, for example, a silicon oxide or a molybdenum oxide, the second vapor phase reactant may comprise an oxygen precursor. In such embodiments of the disclosure, the oxygen precursor comprises at least one of water (H.sub.2O), hydrogen peroxide (H.sub.2O.sub.2), ozone (O.sub.3), or oxides of nitrogen, such as, for example, nitrogen monoxide (NO), nitrous oxide (N.sub.2O), or nitrogen dioxide (NO.sub.2).”). Lee ‘372 in view of Yang and Zope are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lee ‘372 in view of Yang by introducing the water-assisted chemical vapor deposition process disclosed in Zope to improve the quality of the deposited films thus leading to a better performing device. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Moataz Khalifa whose telephone number is (703)756-1770. The examiner can normally be reached Monday - Friday (8:30 am - 5:00). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /M.K./Examiner, Art Unit 2817 /NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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Prosecution Timeline

Show 6 earlier events
May 16, 2025
Response after Non-Final Action
Jun 06, 2025
Request for Continued Examination
Jun 10, 2025
Response after Non-Final Action
Sep 24, 2025
Non-Final Rejection mailed — §102, §103, §112
Dec 22, 2025
Response Filed
Mar 05, 2026
Non-Final Rejection mailed — §102, §103, §112
Jun 04, 2026
Response Filed
Aug 11, 2026
Final Rejection mailed — §102, §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12740200
DISPLAY DEVICE
3y 11m to grant Granted Sep 15, 2026
Patent 12727295
MOUNTING ARRANGEMENTS FOR SEMICONDUCTOR PACKAGES AND RELATED METHODS
4y 5m to grant Granted Sep 01, 2026
Patent 12721239
ELECTRONIC DEVICES AND METHODS OF MANUFACTURING ELECTRONIC DEVICES
4y 1m to grant Granted Aug 25, 2026
Patent 12696754
INTERCONNECT STRUCTURE HAVING DIFFERENT DIMENSIONS FOR CONNECTED CIRCUIT BLOCKS IN INTEGRATED CIRCUIT
4y 1m to grant Granted Jul 28, 2026
Patent 12660435
DISPLAY SUBSTRATE AND DISPLAY DEVICE
3y 11m to grant Granted Jun 16, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

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Prosecution Projections

6-7
Expected OA Rounds
91%
Grant Probability
93%
With Interview (+2.3%)
3y 5m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 66 resolved cases by this examiner. Grant probability derived from career allowance rate.

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