DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 21, 2026 has been entered.
Election/Restrictions
Newly submitted claims 18-20 are directed to an invention that is independent or distinct from the invention originally claimed for the following reasons:
I. Original claims 9-24, and 28-31, drawn to a method that requires the second recesses be filled with the second insulating layer to form a plurality of insulating structures, classified in H10W 20/077.
II. Newly amended claims 18-20, drawn to a method that requires the second recesses be filled with the bonding wire, classified in H10W 20/056.
The inventions are independent or distinct, each from the other because:
Inventions I and II are directed to related methods for forming a conductive structure. The related inventions are distinct if: (1) the inventions as claimed are either not capable of use together or can have a materially different design, mode of operation, function, or effect; (2) the inventions do not overlap in scope, i.e., are mutually exclusive; and (3) the inventions as claimed are not obvious variants. See MPEP § 806.05(j).
In the instant case, the inventions as claimed the two methods as claimed are mutually exclusive because it is not possible to fill the second recesses with the second insulating layer if they have already been filled with the bonding wire. Furthermore, the inventions as claimed do not encompass overlapping subject matter and there is nothing of record to show them to be obvious variants.
Restriction for examination purposes as indicated is proper because all the inventions listed in this action are independent or distinct for the reasons given above and there would be a serious search and/or examination burden if restriction were not required because one or more of the following reasons apply: the inventions would require different search strategies, the searching of different terms and keywords, and the inventions would require different determination of allowability.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 18-20 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Response to Amendment
This Office Action is in response to Applicant's amendments filed January 21, 2026. Claims 9, 11-12, 18, and 20 have been amended. No claims have been added. No claims have been canceled. Claims 18-20 stand withdrawn. Currently, claims 9-17, 21-24, and 28-31 are pending.
Response to Arguments
Applicant's arguments filed January 21, 2026 have been fully considered but they are not persuasive.
The Applicant asserts that the combination of references applied in the previous Office Action fail to disclose the limitations of newly amended claim 9. Specifically, that “Choi fails to teach or suggest that the first conductive feature (124C) comprises a plurality of protrusions disposed over a top surface of the first conductive feature (124C) and between the second recesses (202A)” because “the alleged second recesses (202A, 202B) are removed to form the alleged first conductive feature (124C)”.
The Examiner respectfully disagrees with the assertion that Choi fails to disclose the first conductive feature comprises a plurality of protrusions disposed over a top surface of the first conductive feature and between the second recesses. The claim limitations requires removing a portion of the conductive material to form a first conductive feature, wherein the first conductive feature comprises a plurality of protrusions disposed over a top surface of the first conductive feature and between the second recesses. Choi discloses, in Figs. 1-2, removing a portion of the conductive material (Fig. 1, conductive metal 124, ¶ [0043]) to form a first conductive feature (Fig. 2, interconnect structures 124A, ¶ [0046]),
wherein the first conductive feature (124A) comprises a plurality of protrusions (Fig. 2, elevated section of 124A between voids 202A) disposed over a top surface of the first conductive feature (124A) and between the second recesses (Fig. 2, voids 202A, ¶ [0046]). Fig. 2 of Choi shows the protrusions between the voids “over a top surface of the first conductive feature” in the same way as 13B of the instant application.
Therefore, the Examiner asserts that the Choi still discloses the limitations of newly amended claim 9. The rejection is maintained as appropriate and presented in full herein.
The Applicant further asserts that “Bhosale fails to teach or suggest that the first conductive feature (330) comprises a plurality of protrusions disposed over a top surface of first conductive feature (330) and between the second recesses” because “Bhosale is silent with a plurality of protrusions disposed over a top surface of the first conductive feature (330)”.
The Examiner respectfully disagrees with the assert that Bhosale fails to disclose the first conductive feature comprises a plurality of protrusions disposed over a top surface of the first conductive feature and between the second recesses. The claim limitations requires removing a portion of the conductive material to form a first conductive feature, wherein the first conductive feature comprises a plurality of protrusions disposed over a top surface of the first conductive feature and between the second recesses. In Figs. 19-20, Bhosale discloses removing a portion of the conductive material (Fig. 19, first conductive material layer 329, ¶ [0081]) to form a first conductive feature (Fig. 20, interconnect structure 128 (labeled as 328 in Fig. 20), super via 330, ¶ [0049] and [0083]),
wherein the first conductive feature (328, 330) comprises a plurality of protrusions (Fig. 20, 330 are protrusions) disposed over a top surface of the first conductive feature (124A) and between the second recesses (Fig. 20 recesses between 330).
Therefore, the Examiner asserts that the Bhosale still discloses the limitations of newly amended claim 9. The rejection is maintained as appropriate and presented in full herein.
Applicant’s arguments with respect to claim 18 have been considered but are moot. Claim 18 has been withdrawn from consideration because the claim as amended is drawn to a different species as outlined above.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “protrusions disposed over a top surface of the first conductive feature” of claim 1 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "131" and "R" have both been used to designate first recess in Figs. 8-9.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: “R” in Fig. 9, “R1” and “R2” in Figs. 12B-12C.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: “232” in ¶ [0057].
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
In ¶ [0021], line 12: “the firs layer 112” should read --the first layer 112--.
In ¶ [0057], line 3: “the first and second CMP operations 232” should read -- the first and second CMP operations 233--.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 9-17 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 9, the claim recites the limitation “wherein the first conductive feature comprises a plurality of protrusions disposed over a top surface of the first conductive feature” (emphasis added), which does not have support in the disclosure. The Applicant points to Fig. 13B as supporting this amendment. However, Fig. 13B shows the protrusions as being coplanar with the top surface of the first conductive feature, rather than over a top of surface of the first conductive feature as recited by the claim.
Claims 10-17 depend upon claim 9 and do not rectify the problem. Therefore, claims 10-17 are rejected on at least the same basis as claim 9.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 20200343131 A1) herein after “Choi in view of Wang et al. (Copper voids improvement for the copper dual damascene interconnection process, Journal of Physics and Chemistry of Solids, Volume 69, Issues 2–3, 2008, Pages 566-571) herein after “Wang” and Yao et al. (US 20130207273 A1) herein after “Yao”.
Regarding claim 9, Figs. 1-13 of Choi disclose a method for forming a conductive feature, comprising:
forming a first insulating layer (Fig. 1, ILD 120, ¶ [0043]) over a substrate (Fig. 1, substrate 102, ¶ [0042]);
patterning the first insulating layer (120) to form a first recess (“Interconnect trenches (not shown) have been formed in the ILD 120”, ¶ [0043]) in the first insulating layer (120);
filling the first recess (“Interconnect trenches”) with a conductive material (Fig. 1, “Interconnect trenches (not shown) have been formed in the ILD 120 and the cap 114 then filled with a liner/barrier layer 122 and a conductive metal 124”, ¶ [0043]);
forming a plurality of second recesses (Fig. 2, voids 202A, ¶ [0046]) in the conductive material (124) over the first recess (“Interconnect trenches”),
wherein each of the second recess (202A) overlaps the first recess (“Interconnect trenches”); and
removing a portion of the conductive material (Fig. 1, conductive metal 124, ¶ [0043]) to form a first conductive feature (Fig. 2, interconnect structures 124A, ¶ [0046]),
wherein the first conductive feature (124A) comprises a plurality of protrusions (Fig. 2, elevated section of 124A between voids 202A) disposed over a top surface of the first conductive feature (124A) and between the second recesses (Fig. 2, voids 202A, ¶ [0046]) (Fig. 2 of Choi shows the protrusions between the voids “over a top surface of the first conductive feature” in the same way as 13B of the instant application).
Choi expressly states the recesses (202A) are undesired products (¶32-33) following a first CMP process, where these recesses “disrupt electrical connections, thus reducing yield, performance and quality” (¶ [0046]).
Choi does not disclose wherein a ratio of a sum of opening areas of the second recesses to an opening area of the first recess is less than 1%,
wherein at least two of the second recesses have a substantially same shape from a top view.
In the similar field of endeavor interconnection formation, Wang discloses (pg. 569-570, Table 1) use of corrosion inhibitor BTA mixed into CMP slurries combined with reduced grain size of the conductive fill to minimize the size of undesirable CMP-produced recesses.
It would have been obvious to one of ordinary skill in the art at the time of filing to minimize surface area of these recesses using decreased grain sizes and corrosion inhibitors of Wang in the method of Choi.
It is evident that Choi, as modified by Wang, discloses that sizes of the second recesses are parameters that are result effective variables since varying it affects electrical connections, yield, performance and quality (see Choi, ¶ [0046]).
One would have been motivated to make a ratio of a sum of opening areas of the second recesses to an opening area of the first recess is less than 1% as Choi recognizes that optimization of the second recesses relative to first recess is a known result effective variable as explained above.
MPEP §2144.05-II (A) states "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.).
Furthermore, MPEP §2144.05-II (B) describes that it is considered to be prima facie obvious when there is a motivation to optimize result-effective variables, i.e., a variable which achieves a recognized result.
Wang does not disclose wherein at least two of the second recesses have a substantially same shape from a top view.
In the same field of endeavor of interconnect structures, Figs. 6A and 8 of Yao disclose wherein at least two of the second recesses (Fig. 6A, trenches 136, 138, and 140, ¶ [0015]) have a substantially same shape from a top view (Fig. 8, showing these same recesses filled with metal, labeled in fig. 8 as 236, 238, 240, ¶ [0019], where features labeled 236 have the same rectangular shape when viewed from the top view).
It would have been obvious to one of ordinary skill in the art at the time of filing to form second recesses of Choi with the same shape as disclosed by Yao, to improve production (see Yang, ¶ [0024]) and/or because changes in size and shape are prima facie obvious absent persuasive evidence that the particular configuration is significant (MPEP 2144.04(IV)).
Regarding claim 10, Choi, Wang and Yao disclose the method of claim 9 as applied above, and Figs. 2-3 of Choi further disclose comprising:
performing a first CMP operation prior to the forming of the second recesses (Fig. 2, “a first CMP operation has been applied to the conductive metal 124”, ¶ [0046]); and
performing a second CMP operation after the forming of the second recesses (“the robust planarization process includes using known fabrication operations to recess the interconnect structures 124A, 124B (shown in FIG. 2) to a level that is below the voids 202A, 202B”, “The robust planarization process further includes using known fabrication operations to perform a post-recess second selective-CMP operation”, ¶ [0047] and [0050]).
Regarding claim 11, Choi, Wang and Yao together disclose the method of claim 10 as applied above, and Fig. 3 of Choi further discloses a depth of each second recess (202A) is reduced during the second CMP operation (“the robust planarization process includes using known fabrication operations to recess the interconnect structures 124A, 124B (shown in FIG. 2) to a level that is below the voids 202A, 202B”, ¶ [0047]) (The recesses are removed entirely; therefore the depth is reduced to zero).
Regarding claim 12, Choi, Wang and Yao together disclose the method of claim 9 as applied above, and Fig. 3 of Choi further discloses wherein a depth of each second recess (202A) is less than a thickness of the first conductive feature (124).
Regarding claim 13, Choi, Wang and Yao together disclose the method of claim 10 as applied above, and Figs. 8 and 12 of Choi further disclose forming a second insulating layer (Fig. 8, additional ILD region 802, ¶ [0053]) over the first conductive feature (124C); and
forming a second conductive structure (Fig. 12, contact 1204B, ¶ [0058]) in the second insulating layer (802).
Claims 9, 10, and 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Bhosale et al. (US 20230178474 A1) herein after “Bhosale in view of Park et al. (US 20230178421 A1) herein after “Park” and Yao (US 20130207273 A1).
Regarding claim 9, Figs. 1, 16-22 of Bhosale disclose a method for forming a conductive feature comprising:
forming a first insulating layer (Fig. 16, ILD layer 308, ILD layer 312, ¶ [0079-0080]) over a substrate (Fig. 16, substrate 302, ¶ [0077]);
patterning the first insulating layer (308, 312) to form a first recess (Fig. 18, portion 307, ¶ [0081]) in the first insulating layer (308, 312);
filling the first recess (307) with a conductive material (Fig. 19, first conductive material layer 329, ¶ [0081]);
forming a plurality of second recesses (Fig. 20, recesses between 330) in the conductive material (329) over the first recess (307), wherein each of the second recess overlaps the first recess (307); and
removing a portion of the conductive material (329) to form a first conductive feature (Fig. 20, interconnect structure 128 (labeled as 328 in Fig. 20), super via 330, ¶ [0049] and [0083]),
wherein the first conductive feature (328, 330) comprises a plurality of protrusions (Fig. 20, 330 are protrusions) disposed over a top surface of the first conductive feature (124A) and between the second recesses (Fig. 20 recesses between 330).
Bhosale does not disclose wherein a ratio of a sum of opening areas of the second recesses to an opening area of the first recess is less than 1%,
wherein at least two of the second recesses have a substantially same shape from a top view.
In the same field of endeavor of semiconductor structures, Park discloses (¶ [0002]) placement of millions of devices on a single substrate, where individual packages can include 7 or more conductive layers connected by vias. Park further discloses decrease in via pitch spacing, increasing the number of conductive features per unit area in the device.
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the method of Bhosale to reduce the spacing between conductive features as disclosed by Park. The decreased distance between conductive features can be optimized such that the recess area between features occupies less than 1% of the total area, providing increased speed and efficiency of the semiconductor device.
MPEP §2144.05-II (A) states "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%.).
Furthermore, MPEP §2144.05-II (B) describes that it is considered to be prima facie obvious when there is a motivation to optimize result-effective variables, i.e., a variable which achieves a recognized result.
Park does not disclose wherein at least two of the second recesses have a substantially same shape from a top view.
In the same field of endeavor of interconnect structures, Figs. 6A and 8 of Yao disclose wherein at least two of the second recesses (136, 138, and 140) have a substantially same shape from a top view (Fig. 8, showing these same recesses filled with metal, labeled in fig. 8 as 236, 238, 240, ¶ [0019], where features labeled 236 have the same rectangular shape when viewed from the top view).
It would have been obvious to one of ordinary skill in the art at the time of filing to form second recesses of Choi with the same shape as disclosed by Yao, to improve production (see Yang, ¶ [0024]) and/or because changes in size and shape are prima facie obvious absent persuasive evidence that the particular configuration is significant (MPEP 2144.04(IV)).
Regarding claim 10, Bhosale, Park and Yao together disclose the method of claim 9 as applied above, and Figs. 16-22 of Bhosale further disclose comprising:
performing a first CMP operation prior to the forming of the second recesses ( “The interconnect structure 128 may be formed of Cu, or another suitable material, and may have a width (in direction X-X′) that is approximately the same as the width of the contact 126. The interconnect structure 128 can be formed according to a dual damascene processing including lithography and etching”, ¶ [0054]); and
performing a second CMP operation after the forming of the second recesses (Fig. 21, “the hard mask is removed in S3007 using any suitable wet and/or dry technique”, ¶ [0084]).
Regarding claim 13, Bhosale, Park and Yao together disclose the method of claim 10 as applied above, and Fig. 22 of Bhosale further discloses comprising:
forming a second insulating layer (Fig. 22, ILD via layer 322, ¶ [0085]) over the first conductive feature (328, 330); and
forming a second conductive structure (Fig. 22, contact 333, ¶ [0086]) in the second insulating layer (322).
Regarding claim 14, Bhosale, Park and Yao together disclose the method of claim 13 as applied above, and Fig. 22 of Bhosale further discloses wherein the second recesses (area around 330) are filled with the second insulating layer (322) to form a plurality of insulating structures.
Regarding claim 15, Bhosale, Park and Yao together disclose the method of claim 14 as applied above, and Fig. 22 of Bhosale further discloses wherein the first conductive feature (328, 330) comprises a central region and a peripheral region area surrounding the central region (see Annotation 1, Fig. 22 of Bhosale, where a central region marked with a dashed line and peripheral regions marked with a dotted line).
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Annotation 1, Fig. 22 of Bhosale
Regarding claim 16, Bhosale, Park and Yao together disclose the method of claim 14 as applied above, and Fig. 22 of Bhosale further discloses wherein the insulating structures further comprises:
a plurality of first features (322, 335, ¶85, 89) disposed in the central region (indicated in examiner annotated fig. 22 with dashed line) of the first conductive feature (330 ¶83, 85); and
a plurality of second features (322, 335, ¶85, 89) disposed in the peripheral region (indicated in examiner annotated fig. 22 with dotted line) of the first conductive feature (330).
Allowable Subject Matter
Claims 21-24, and 29-31 are allowed.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance:
Regarding claim 21, the prior art of record alone or in combination fails to disclose or fairly suggest “forming a second insulating layer over the first conductive feature, wherein the plurality of recesses are filled with the second insulating layer to form a plurality of insulating structures over the first conductive feature, wherein an area ratio of a sum of surface areas of the plurality of insulating structures to a surface area of the first conductive feature is less than 1%” in combination with the other limitations of claim 21.
Choi in view of Wang and Yao disclose minimization of the area of recesses to less than 1%, but these recesses are of a conductive layer and are completely removed by additional CMP processes before additional insulating layers are deposited.
Bhosale in view of Park and Yao discloses many of the same elements of the disclosed invention, but do not, individually or combined, anticipate or render obvious the distinct feature of an area ratio of a sum of surface areas of the plurality of insulating structures to a surface area of the first conductive feature is less than 1%.
Claims 22-24, and 29-31 depend upon claim 21 and are allowed for at least the same reasons as claim 21.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/C.A.N./ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
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