DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR
1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/22/2026 has been entered.
Response to Amendment
The Amendment filed on 04/22/2026 has been entered. Claims 11-40 are withdrawn. Claims 1-
40 are pending.
Response to Arguments
Applicant’s arguments "Applicant Arguments/Remarks Made in an Amendment"
with the "Amendment/Req. Reconsideration-After Final Reject" filed on 04/22/2026, have been fully considered, the arguments are not persuasives and some of them are moot because do not apply to new ground of rejections with a new reference, US 20230331944 A1 to Saito, being used in the current rejection, see detail below.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 5, 7-10 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Yu et al. (US 2021/0028145 A1, hereinafter Yu, of the record) in view of Saito et al. (US 20230331944 A1, hereinafter Saito).
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Regarding independent Claim 1, Yu discloses an electronic package ([0010], Fig. 8D), comprising:
Yu’s Figure 8D-Annotated.
a circuit structure (140 a redistribution layer structure including conductive features 144 and dielectric layer 142 in [0019], Fig. 8D) provided with a redistribution layer (144 conductive feature including metal lines 144a and metal vias 144b in [0019], Fig. 8D) and having a first surface (first a surface of 140 that is closer to 110 in Fig. 8D) and a second surface (second a surface of 140 that is further away from 110 in Fig. 8D) opposite to each other (in Fig. 8D);
at least one electronic element (110 a logic dies in [0016], Fig. 8D) disposed on the first surface (first) of the circuit structure (144) and electrically connected to the redistribution layer (144) via a plurality of conductive bumps (112 connectors in [0017], Fig. 8D);
an encapsulation layer (114, 130 an epoxy polymer 114 and a polymer material 130, encapsulating the circuit 110, in [0017-0018], Fig. 8D) covering and in contact (Fig. 8D) with the at least one electronic element (110, in [0017], Fig. 8D) and the plurality of conductive bumps (112);
a first organic material substrate (190 a redistribution layer structure including 192 made of polyimide in [0025], Fig. 8D) disposed on the second surface (second) of the circuit structure (140) and having a first circuit layer (194 conductive feature including metal lines 194a and metal vias 194b in [0025], Fig. 8D); and
at least one second organic material substrate (200 a redistribution layer structure including 202 made of polyimide in [0027-0028], Fig. 8D, being a PCB substrate, wherein the redistribution layer structure 200 is formed by the process such as LDI to manufacture a PCB, having good rigidity in [0030]) having a second circuit layer (204 conductive feature including metal lines 204a and metal vias 204b in [0027], Fig. 8D), wherein the first organic material substrate (190) is stacked on the at least one second organic material substrate (200) via a plurality of supporting bodies (194b metal vias in [0025], Fig. 8D), such that the redistribution layer (144) is electrically connected (Fig. 8D) to the second circuit layer (204) via the first circuit layer (194), and
wherein a line width and a line spacing of the redistribution layer (144) of the circuit structure (140) is smaller (the line spacing of 144a are smaller than the line spacing of 194a and 204a, Fig. 8D, Annotated) than a line width and a line spacing of the first circuit layer (194) of the first organic material substrate (190) and a line width and a line spacing of the second circuit layer (204) of the at least one second organic material substrate (200),
wherein the line width or line spacing of the redistribution layer (144) of the circuit structure (140) is in line (a diagonal line connecting 144 and bump 112, wherein 112 connects the electronic element 110, in [0016], Fig. 8D, Annotated) with a line width or line spacing of an integrated circuit of the electronic element (110).
Yu does not expressly disclose at least one second organic material substrate being a Substrate Like PCB (SLP).
However, in the same semiconductor device field of endeavor, Saito discloses a Substrate Like PCB (SLP) (substrate a printed circuit boards (PCBs) manufactured as a substrate-like PCB in [0006]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Saito’s feature of being a Substrate Like PCB (SLP) to Yu’s device for miniaturization of conductor wiring, multilayering of conductor wiring layers, thinning, and improvement in performance such as mechanical properties ([0006], Saito).
Regarding Claim 2, Yu modified by Saito discloses the electronic package of claim 1, wherein a width of the circuit structure (140, Yu) is smaller than (as showed in Fig. 8D, Yu) a width of the first organic material substrate (190, Yu).
Regarding Claim 5, Yu modified by Saito discloses the electronic package of claim 1, wherein a number of layers of the redistribution layer (144, Yu) of the circuit structure (140, Yu) is smaller than (144 including two layers and 200 including three layers, Fig. 8D, Annotated, Yu) a number of layers of the second circuit layer (204, Yu) of the at least one second organic material substrate (200, Yu).
Regarding Claim 7, Yu modified by Saito discloses the electronic package of claim 1, further comprising a heat sink (240 a heat sink in [0047], Fig. 8D, Yu) disposed on (240 is disposed on 190 in [0047], Fig. 8D, Yu) the first organic material substrate (190, Yu).
Regarding Claim 8, Yu modified by Saito discloses the electronic package of claim 1, wherein the plurality of supporting bodies (194b metal vias in [0025], Fig. 8D, Yu) are electrically connected (Fig. 8D, Yu) to the first organic material substrate (190, Yu) and the at least one second organic material substrate (200, Yu).
Regarding Claim 9, Yu modified by Saito discloses the electronic package of claim 1, further comprising a circuit board (additional circuit board in [0034], Yu), wherein the at least one second organic material substrate (200, Yu) is stacked on the circuit board (additional circuit board, Yu) via a plurality of conductive elements (210 conductive terminals in [0034], Fig. 8D, Yu).
Regarding Claim 10, Yu modified by Saito discloses the electronic package of claim 9, wherein the plurality of conductive elements (210, Yu) are electrically connected (in [0034], Yu) to the circuit board (additional circuit board, Yu) and the at least one second organic material substrate (200, Yu).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Saito and further in view of Tseng et al. (US 2022/0122909 A1, hereinafter Tseng, of the record).
Regarding Claim 3, Yu modified by Saito discloses the electronic package of claim 1,
Yu modified by Saito does not expressly disclose wherein the first organic material substrate (190, Yu) is stacked with a plurality of the second organic material substrates, and the line width or line spacing of each of the plurality of the second organic material substrates increases in a direction away from the circuit structure.
However, in the same semiconductor device field of endeavor, Tseng discloses
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wherein the first organic material substrate (110 a redistribution structure in [0021], Fig. 2H) is stacked with a plurality of the second substrates (206, 208 redistribution structures in [0037], Fig. 2H), and the line width or line spacing of each of the plurality of the second substrates (206, 208) increases in a direction away (the line spacing from 206 to 208 is increasing in Fig. 2H, Annotated) from the circuit structure (108 a redistribution structure in [0021], Fig. 2H).
Tseng’s Figure 2H-Annotated.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Tseng’s feature wherein a number of layers of the first circuit layer of the first organic material substrate is equal to a number of layers of the second circuit layer of the at least one second organic material substrate to the combination of Yu and Saito to increase the yield and decrease costs ([0010], Tseng).
The combination of Yu, Saito and Tseng results wherein the first organic material substrate (190’s Yu) is stacked with a plurality of the second organic material substrates (200’s Yu/Saito modified by 206,208 from Tseng), and the line width or line spacing of each of the plurality of the second organic material substrates (200’s Yu modified by 206,208 from Tseng) increases (Fig. 2H, Annotated) in a direction away from the circuit structure (140’s Yu).
Claims 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Saito and further in view of Jiang et al. (US 2020/0328142 A1, hereinafter Jiang, of the record).
Regarding Claim 4, Yu modified by Saito discloses the electronic package of claim 1,
Yu modified by Saito does not expressly disclose wherein the first organic material substrate (190, Yu) is stacked with a plurality of the second organic material substrates, and a coefficient of thermal expansion of each of the plurality of the second organic material substrates increases in a direction away from the circuit structure.
However, in the same semiconductor device field of endeavor, Jiang discloses
a plurality of the second organic material substrates (22 a plurality of second organic material substrate in [0043], Fig. 3), and a coefficient of thermal expansion (coefficient of thermal expansion (CTE) in [0005]) of each of the plurality of the second organic material substrates (22) increases in (the CTEs change gradually from top to bottom in [0055]) a direction away from the circuit structure (21’ a first circuit portion in [0036], Fig. 2E).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Jiang’s wherein a plurality of the second organic material substrates, and a coefficient of thermal expansion of each of the plurality of the second organic material substrates increases in a direction away from the circuit structure to the combination of Yu and Saito to prevent the warpage due to mass changing of a thermal stress ([0027], Jiang).
The combination of Yu, Saito and Jiang results wherein the first organic material substrate (190’s Yu) is stacked with a plurality of the second organic material substrates (200’s Yu/Saito modified by Jiang’s 22), and a coefficient of thermal expansion of each of the plurality of the second organic material substrates (200’s Yu/Saito modified by Jiang’s 22) increases (in [0055], Fig. 3, Jiang) in a direction away from the circuit structure (140’s Yu).
Regarding Claim 6, Yu modified by Saito discloses the electronic package of claim 1,
Yu modified by Saito does not expressly disclose wherein a number of layers of the first circuit layer (194, Yu) of the first organic material substrate (190, Yu) is equal to a number of layers of the second circuit layer (204, Yu) of the at least one second organic material substrate (200, Yu).
However, in the same semiconductor device field of endeavor, Jiang discloses
wherein a number of layers of the first circuit layer (21’ a first circuit portion in [0036], Fig. 2E) of the first organic material substrate (21 a first organic material substrate in [0036], Fig. 2E) is equal (21′ and 22′ have the same layer number of circuit layers in [0062]) to a number of layers of the second circuit layer (22’ a second circuit portion in [0043], Fig. 2E) of the at least one second organic material substrate (22 a second organic material substrate in [0043], Fig. 2E).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Jiang’s feature wherein a number of layers of the first circuit layer of the first organic material substrate is equal to a number of layers of the second circuit layer of the at least one second organic material substrate to the combination of Yu and Saito to increase the fabrication yield and reduce the fabrication cost effectively ([0026], Jiang).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA MILENA RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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