DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Status of claim(s) to be treated in this office action:
Independent: 1, 11, 21 and 31.
Pending: 1-40.
Withdrawn: 11-40.
Response to Amendment
The Amendment filed on 12/22/2025 has been entered.
Response to Arguments
Applicant’s arguments "Applicant Arguments/Remarks Made in an Amendment"
with the "Amendment/Req. Reconsideration-After Non-Final Reject" filed on 12/22/2025, have been fully considered, the Applicant’s arguments describe that in the Yu’s device (US 20210028145 A1), "…fails to disclose, teach or suggest, the technical feature of wherein a line width and a line spacing of the redistribution layer of the circuit structure are smaller than a line width and a line spacing of the first circuit layer of the first organic material substrate and a line width and a line spacing of the second circuit layer of the at least one second organic material substrate, as recited in the amended claim 1". However, the Applicant’s arguments are not persuasive because the Yu’s describes wherein a line width and a line spacing of the redistribution layer (144) of the circuit structure (140) is smaller (the line spacing of 144a are smaller than a line spacing of 194a and 204a, Fig. 8D, Annotated) than a line width and a line spacing of the first circuit layer (194) of the first organic material substrate (190) and a line width and a line spacing of the second circuit layer (204) of the at least one second organic material substrate (200), see below rejection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that
form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1-2, 5, 7-10 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Yu et al. (US 2021/0028145 A1, hereinafter Yu, of the record).
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Regarding independent Claim 1, Yu teaches an electronic package ([0010], Fig. 8D), comprising:
Yu’s Figure 8D-Annotated.
a circuit structure (140 a redistribution layer structure including conductive features 144 and dielectric layer 142 in [0019], Fig. 8D) provided with a redistribution layer (144 conductive feature including metal lines 144a and metal vias 144b in [0019], Fig. 8D) and having a first surface (first a surface of 140 that is closer to 110 in Fig. 8D) and a second surface (second a surface of 140 that is further away from 110 in Fig. 8D) opposite to each other (in Fig. 8D);
at least one electronic element (110 a logic dies in [0016], Fig. 8D) disposed on the first surface (first) of the circuit structure (144) and electrically connected to the redistribution layer (144) via a plurality of conductive bumps (112 connectors in [0017], Fig. 8D);
an encapsulation layer (114, 130 an epoxy polymer 114 and a polymer material 130, encapsulating the circuit 110, in [0017-0018], Fig. 8D) covering and in contact (Fig. 8D) with the at least one electronic element (110, in [0017], Fig. 8D) and the plurality of conductive bumps (112);
a first organic material substrate (190 a redistribution layer structure including 192 made of polyimide in [0025], Fig. 8D) disposed on the second surface (second) of the circuit structure (140) and having a first circuit layer (194 conductive feature including metal lines 194a and metal vias 194b in [0025], Fig. 8D); and
at least one second organic material substrate (200 a redistribution layer structure including 202 made of polyimide in [0027-0028], Fig. 8D) having a second circuit layer (204 conductive feature including metal lines 204a and metal vias 204b in [0027], Fig. 8D), wherein the first organic material substrate (190) is stacked on the at least one second organic material substrate (200) via a plurality of supporting bodies (194b metal vias in [0025], Fig. 8D), such that the redistribution layer (144) is electrically connected (Fig. 8D) to the second circuit layer (204) via the first circuit layer (194), and
wherein a line width and a line spacing of the redistribution layer (144) of the circuit structure (140) is smaller (the line spacing of 144a are smaller than the line spacing of 194a and 204a, Fig. 8D, Annotated) than a line width and a line spacing of the first circuit layer (194) of the first organic material substrate (190) and a line width and a line spacing of the second circuit layer (204) of the at least one second organic material substrate (200),
wherein the line width or line spacing of the redistribution layer (144) of the circuit structure (140) is in line (a diagonal line connecting 144 and bump 112, wherein 112 connects the electronic element 110, in [0016], Fig. 8D, Annotated) with a line width or line spacing of an integrated circuit of the electronic element (110).
Regarding Claim 2, Yu discloses the electronic package of claim 1, wherein a width of the circuit structure (140) is smaller than (as showed in Fig. 8D) a width of the first organic material substrate (190).
Regarding Claim 5, Yu discloses the electronic package of claim 1, wherein a number of layers of the redistribution layer (144) of the circuit structure (140) is smaller than (144 including two layers and 200 including three layers, Fig. 8D, Annotated) a number of layers of the second circuit layer (204) of the at least one second organic material substrate (200).
Regarding Claim 7, Yu discloses the electronic package of claim 1, further comprising a heat sink (240 a heat sink in [0047], Fig. 8D) disposed on (240 is disposed on 190 in [0047], Fig. 8D) the first organic material substrate (190).
Regarding Claim 8, Yu discloses the electronic package of claim 1, wherein the plurality of supporting bodies (194b metal vias in [0025], Fig. 8D) are electrically connected (Fig. 8D) to the first organic material substrate (190) and the at least one second organic material substrate (200).
Regarding Claim 9, Yu discloses the electronic package of claim 1, further comprising a circuit board (additional circuit board in [0034]), wherein the at least one second organic material substrate (200) is stacked on the circuit board (additional circuit board) via a plurality of conductive elements (210 conductive terminals in [0034], Fig. 8D).
Regarding Claim 10, Yu discloses the electronic package of claim 9, wherein the plurality of conductive elements (210) are electrically connected (in [0034]) to the circuit board (additional circuit board) and the at least one second organic material substrate (200).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all
obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. in view of Tseng et al. (US 2022/0122909 A1, hereinafter Tseng, of the record).
Regarding Claim 3, Yu discloses the electronic package of claim 1,
Yu does not expressly disclose wherein the first organic material substrate (190) is stacked with a plurality of the second organic material substrates, and the line width or line spacing of each of the plurality of the second organic material substrates increases in a direction away from the circuit structure.
However, in the same semiconductor device field of endeavor, Tseng discloses
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wherein the first organic material substrate (110 a redistribution structure in [0021], Fig. 2H) is stacked with a plurality of the second substrates (206, 208 redistribution structures in [0037], Fig. 2H), and the line width or line spacing of each of the plurality of the second substrates (206, 208) increases in a direction away (the line spacing from 206 to 208 is increasing in Fig. 2H, Annotated) from the circuit structure (108 a redistribution structure in [0021], Fig. 2H).
Tseng’s Figure 2H-Annotated.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Tseng’s feature wherein a number of layers of the first circuit layer of the first organic material substrate is equal to a number of layers of the second circuit layer of the at least one second organic material substrate to Yu’s device to increase the yield and decrease costs ([0010], Tseng).
The combination of Yu and Tseng results wherein the first organic material substrate (190’s Yu) is stacked with a plurality of the second organic material substrates (200’s Yu modified by 206,208 from Tseng), and the line width or line spacing of each of the plurality of the second organic material substrates (200’s Yu modified by 206,208 from Tseng) increases (Fig. 2H, Annotated) in a direction away from the circuit structure (140’s Yu).
Claims 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. in view of Jiang et al. (US 2020/0328142 A1, hereinafter Jiang, of the record).
Regarding Claim 4, Yu discloses the electronic package of claim 1,
Yu does not expressly disclose wherein the first organic material substrate (190) is stacked with a plurality of the second organic material substrates, and a coefficient of thermal expansion of each of the plurality of the second organic material substrates increases in a direction away from the circuit structure.
However, in the same semiconductor device field of endeavor, Jiang discloses
a plurality of the second organic material substrates (22 a plurality of second organic material substrate in [0043], Fig. 3), and a coefficient of thermal expansion (coefficient of thermal expansion (CTE) in [0005]) of each of the plurality of the second organic material substrates (22) increases in (the CTEs change gradually from top to bottom in [0055]) a direction away from the circuit structure (21’ a first circuit portion in [0036], Fig. 2E).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Jiang’s wherein a plurality of the second organic material substrates, and a coefficient of thermal expansion of each of the plurality of the second organic material substrates increases in a direction away from the circuit structure to Yu’s device to prevent the warpage due to mass changing of a thermal stress ([0027], Jiang).
The combination of Yu and Jiang results wherein the first organic material substrate (190’s Yu) is stacked with a plurality of the second organic material substrates (200’s Yu modified by Jiang’s 22), and a coefficient of thermal expansion of each of the plurality of the second organic material substrates (200’s Yu modified by Jiang’s 22) increases (in [0055], Fig. 3, Jiang) in a direction away from the circuit structure (140’s Yu).
Regarding Claim 6, Yu discloses the electronic package of claim 1,
Yu does not expressly disclose wherein a number of layers of the first circuit layer (194) of the first organic material substrate (190) is equal to a number of layers of the second circuit layer (204) of the at least one second organic material substrate (200).
However, in the same semiconductor device field of endeavor, Jiang discloses
wherein a number of layers of the first circuit layer (21’ a first circuit portion in [0036], Fig. 2E) of the first organic material substrate (21 a first organic material substrate in [0036], Fig. 2E) is equal (21′ and 22′ have the same layer number of circuit layers in [0062]) to a number of layers of the second circuit layer (22’ a second circuit portion in [0043], Fig. 2E) of the at least one second organic material substrate (22 a second organic material substrate in [0043], Fig. 2E).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Jiang’s feature wherein a number of layers of the first circuit layer of the first organic material substrate is equal to a number of layers of the second circuit layer of the at least one second organic material substrate to Yu’s device to increase the fabrication yield and reduce the fabrication cost effectively ([0026], Jiang).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Hsu et al. (US 11557533 B2) teaches “PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF”.
England (US 2019/0237430 A1) teaches “3D IC PACKAGE WITH RDL INTERPOSER AND RELATED METHOD”.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA MILENA RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898