DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Prior objection to claim 9 is withdrawn in view of amendments to the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 9-10 and 13-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 2017/0207200 A1, of record).
Re Claim 9, Lin teaches a package structure (Fig. 17), comprising: a first package, comprising:
a first insulating encapsulant (51, Figs. 13 and 17, para [0080]);
a chip stacking structure (21+22+25+27+223+273, Figs. 4, 7, 12 and 17, paras [0067] – [0070]) embedded in the first insulating encapsulant (51, see Fig. 17), and the chip stacking structure comprising stacked semiconductor dies (22+27, Fig. 7);
a heat sink (39, see Figs. 12 and 17, para [0076]) embedded in the first insulating encapsulant (51, Figs. 13 and 17), the heat sink being (39) stacked over and thermally coupled (see Figs. 13 and 17) to the stacked semiconductor dies (22+27) of the chip stacking structure (21+22+25+27+223+273), wherein the heat sink extends across the chip stacking structure continuously (see Figs. 12 and 17);
a conductive through via (327, see Figs. 8 and 17, para [0072]) disposed aside the chip stacking structure (21+22+25+27+223+273) and the heat sink (39), wherein a first minimum lateral distance (marked “L1” in annotated Fig. 17 below) between the conductive through via (327) and the heat sink (39) is smaller than a second minimum lateral distance (marked “L2” in annotated Fig. 17 below) between the conductive through via (327) and the chip stacking structure (21+22+25+27+223+273, where L1 is smaller than L2); and
a redistribution circuit structure (36, Fig. 17, para [0074]) disposed over the first insulating encapsulant (51) and the heat sink (39); and
a second package (61, Fig. 17, para [0084]) disposed over the redistribution circuit structure (36), wherein the second package (61) comprises electrical connectors (connection bumps 71 on bottom surface of 61) electrically connected to the redistribution circuit structure (36, see Fig. 17), and at least one first electrical connector (marked “71a” in annotated Fig. 17 below) among the electrical connectors (71) is located above the heat sink (“71a” is located above the heat sink 39).
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Re Claim 10, Lin teaches the package structure of claim 9 further comprising a first attachment film (35, see Figs. 12 and 17, para [0073]) disposed between the heat sink (39) and the redistribution circuit structure (36), wherein a first lateral dimension of the first attachment film (horizonal width of 35) is greater (see Fig. 12) than a second lateral dimension of the chip stacking structure (horizonal width of 21+22+25+27+223+273).
Re Claim 13, Lin teaches the package structure of claim 9, wherein second electrical connectors (marked “71b” in annotated Fig. 17 above) among the electrical connectors (connection bumps 71) are electrically connected to the redistribution circuit structure (36), and the second electrical connectors are not located above the heat sink (39, see annotated Fig. 17 above).
Re Claim 14, Lin teaches the package structure of claim 13, wherein the at least one first electrical connector (marked “71a” in annotated Fig. 17 above) is surrounded by the second electrical connectors (marked “71b” in annotated Fig. 17 above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Koopmans et al. (US 2015/0279828 A1, newly cited), and further in view of Yu’865 et al. (US 2015/0206865 A1, newly cited) and Yu’939 et al. (US 2015/0294939 A1, newly cited).
Re Claim 1, Koopmans teaches a package structure (Fig. 2), comprising:
a chip stacking structure (stack of 202b dies, Fig. 2, para [0019]);
a thermal enhance component (202a, Fig. 2, para [0019]) stacked over and thermally coupled to the chip stacking structure (stack of 202b dies), wherein the thermal enhance component (202a) extends across the chip stacking structure continuously (stack of 202b dies, see Fig. 2);
a conductive through via (140, Fig. 2, para [0010]) disposed aside the chip stacking structure (stack of 202b dies) and the thermal enhance component (202a), wherein a first minimum lateral distance (marked “L1a” in annotated Fig. 2 below) between the conductive through via (140) and the thermal enhance component (202a) is smaller than a second minimum lateral distance (marked “L2a” in annotated Fig. 2 below) between the conductive through via (140) and the chip stacking structure (stack of 202b dies);
a redistribution circuit structure (120, Fig. 2, para [0014], also see examiner comment’s regarding “redistribution circuit structure” below) disposed over the thermal enhance component (202a), the conductive through via (140); and
a first attachment film (marked “attachment film” in annotated Fig. 2 below), wherein the thermal enhance component (202a) is attached to the redistribution circuit structure (120) through the first attachment film (“attachment film”).
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Regarding the “redistribution structure”, Koopmans discloses that the interposer 120 (Fig. 2, para [0014]), can be used to electrically couple the die stacks and vias, thus performing the same functionality as a redistributing structure. However, it is not explicitly shown in the embodiment of Fig. 2. In another embodiment, in Fig. 3, the interposer 120 is shown to have a dedicated redistribution network 327 (Fig. 3, para [0023]). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, that the interposer 120 in the embodiment of Fig. 2 of Koopmans can include a redistribution network as taught by the embodiment of Fig. 3.
Additionally, Koopmans does not disclose a first insulating encapsulant laterally encapsulating the thermal enhance component, the conductive through via and the chip stacking structure, and that the redistribution circuit structure is disposed over a surface of the first insulating encapsulant.
Related art, Yu’865 teaches a first insulating encapsulant (128, Fig. 8, para [0020]), that encapsulates the stacked dies (102+104) and vias (126, see Fig. 8). The encapsulant provides mechanical support and protects the inner components from any mechanical damage, thus improving the longevity of the device.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, that the inner gap within the device in Fig. 2 of Koopmans can be filled with an encapsulant as taught by Yu’865, because the encapsulant provides mechanical support and protects the inner components from any mechanical damage, thus improving the longevity of the device.
Thus, Koopmans modified by Yu’865 would teach a first insulating encapsulant (128, Fig. 8, Yu’865, also marked as “first encapsulant” in annotated Fig. 2 of Koopmans above) would be laterally encapsulating the thermal enhance component (202a, Fig. 2, Koopmans), the conductive through via (140, Fig. 2, Koopmans) and the chip stacking structure (stack of 202b dies, Fig. 2, Koopmans), and the redistribution circuit structure (120, Fig. 2, Koopmans) is disposed over a surface of the first insulating encapsulant (see annotated Fig. 2 above).
Regarding, the first attachment film (marked “attachment film” in annotated Fig. 2 of Koopmans above), Koopmans does not explicitly identify the element in the text but is disclosed in Fig. 2.
Related art, Yu’939 discloses an insulating attachment film (112, Fig. 1) between the substrate (104, Fig. 1, para [0016]) and the interconnect structure (140, Fig. 1, para [0019]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, that the “attachment film” shown in Fig. 2 of Koopmans is an insulating attachment film as disclosed by Yu’939, which not only provides adhesion but also provides an insulating layer between the different active components.
Re Claim 6, Koopmans modified by Yu’865 and Yu’939 teaches the package structure of claim 1, wherein the thermal enhance component (202a, Koopmans) comprises a semiconductor substrate (202a die is a semiconductor substrate, para [0017], Koopmans) or a conductive substrate, the semiconductor substrate or the conductive substrate is attached to the redistribution circuit structure (120, Fig. 2, Koopmans) through the first attachment film (“attachment film”, Koopmans), and a top surface of the first attachment film is substantially level with the surface of the first insulating encapsulant (“first encapsulant”, see annotated Fig. 2 of Koopmans above).
Re Claim 7, Koopmans modified by Yu’865 and Yu’939 teaches the package structure of claim 1, wherein a top surface of the first attachment film (“attachment film”, Koopmans) is substantially level with the surface of the first insulating encapsulant (“first encapsulant”, see annotated Fig. 2 of Koopmans above).
Re Claim 8, Koopmans modified by Yu’865 and Yu’939 teaches the package structure of claim 1 further comprising:
a second attachment film (underfill 117, Fig. 2, para [0016], Koopmans) disposed between the chip stacking structure (stack of 202b dies, Fig. 2) and the thermal enhance component (202a, Fig. 2), wherein the chip stacking structure is thermally coupled to the thermal enhance component through the second attachment film (see Fig. 2, Koopmans).
Allowable Subject Matter
Claims 15-17 and 19-20 are allowed as explained in the Office Action dated 10/01/2025.
Claims 2-3, 5 and 11-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Re Claim 2, Koopmans et al. (US 2015/0279828 A1, newly cited) teaches that the chip stacking structure (stack of 202b dies, Fig. 2) comprises:
a first semiconductor die (bottommost 202b, Fig. 2),
a second semiconductor die (topmost 202b, Fig. 2) electrically connected to the first semiconductor die (bottommost 202b), wherein the second semiconductor die (topmost 202b) is disposed between the first semiconductor die (bottommost 202b) and the thermal enhance component (202a, Fig. 2), the thermal enhance component has a continuous top surface with a first width in a direction (width of 202a along horizontal direction), the second semiconductor die (topmost 202b) has a second width in the direction (width of 202b along horizontal direction), and the second width is smaller than the first width (width of 202b is smaller than then the width of 202a);
a second insulating encapsulant (117, Fig. 2) laterally encapsulating the second semiconductor die (topmost 202b);
a first bonding structure disposed on a back surface of the first semiconductor die (interconnects 108, contacting the top surface of bottommost 202b, Fig. 2)
a second bonding structure disposed on a front surface of the second semiconductor die (interconnects 108, contacting the bottom surface of topmost 202b, Fig. 2), wherein the first bonding structure and the second bonding structure are disposed between the first semiconductor die and the second semiconductor die (see Fig. 2);
Koopmans fails to teach “a third insulating encapsulant laterally encapsulating the first semiconductor die, wherein sidewalls of the third insulating encapsulant are substantially aligned with sidewalls of the second insulating encapsulant.” The prior art of record taken either single or in combination fails to teach or reasonably suggest the above limitation when taken in context of the independent claim 1, as a whole.
Claims 3 and 5 depend from claim 2 and are allowable for at least the reasons above.
Claim 11 is allowable for at least the reasons of, “further comprising a second attachment film disposed between the heat sink and the chip stacking structure, wherein the first lateral dimension of the first attachment film is greater than a third lateral dimension of the second attachment film”. The prior art of record taken either single or in combination fails to teach or reasonably suggest the above limitation when taken in context of the independent claim 9 and intervening claim 10, as a whole.
Claims 12 depends from claim 11 and is allowable for at least the reasons above.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claims 1 and 9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Regarding claim 9, applicant argued that the newly amended claim is not taught by Lin et al. (US 2017/0207200 A1, of record). Examiner respectfully disagrees with the applicant, as is explained in the rejection of claim 9 above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898