DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9/10/2025 has been entered.
Claim Status
Previous rejection: claims 1, 2, 4 through 16, 21, 23, 24 and 25 are rejected, claims 3 is objected, claims 17 through 20 and 22 are cancelled
Current rejection: claims 1, 2 4 through 6 11 through 16, 21 and 25 are rejected, claims 3 7 10 23 and 24 are objected, claims 17 through 20 and 22 are cancelled.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4, 5, 6, 8, and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2020/0135473) in view of Yeo (US 2018/0151683)
Regarding claim 1, Park teaches
a semiconductor device, comprising; a fin (fig 16,17:103a [para 0020]) protruding from a substrate (fig 16:102 [para 0020]); a first gate structure (fig 16:1 [para 0019]) and a second gate structure (fig 16:2 [para 0019]) over the fin (fig 16,17:103a [para 0020]); a dielectric structure (fig 19:113 [para 0026]), wherein, in a cross-sectional view of the semiconductor device along a lengthwise direction of the fin (fig 19:103a [para 0024]), the dielectric structure (fig 19:113 [para 0026]) is disposed between the first (fig 16:1 [para 0019]) and second gate structures (fig 16:102 [para 0019]),
wherein the dielectric structure (fig 19:113 [para 0026]) is spaced apart from the fin (fig 19:103a [para 0020]), and wherein the dielectric structure (fig 11:113 [para 0026]) extends further from the substrate (fig 11:102 [para 0023]) than a first gate electrode (fig 11:108 [para 0030]) of the first gate structure (fig 11:1 [para 0030]) and a second gate electrode (fig 11:108 [para 0030]) of the second gate structure (fig 11:2 [para 0030]); […]; and a conductive feature (fig 1:120 [para 0028]) sandwiched by the first (fig 19:1 [para 0019]) and second (fig 19:2 [para 0019]) gate structures, wherein the conductive feature (fig 17:120 [para 0029]) is divided by the dielectric structure (fig 17:113 [para 0029]) into a first segment (fig 17:120b [para 0029]) and a second segment (fig 17:120c [para 0029]), and wherein the first segment (fig 17:120b [para 0029]) of the conductive feature (fig 17:120 [para 0029]) is above and electrically coupled to a source/drain region (fig 1 [para 0020]) of the fin (fig 1:103a [para 0020]).
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Park does not teach a liner a surrounding the dielectric structure.
Yeo teaches a liner layer (fig 6c:150 [para 0068]) surrounding the dielectric structure (fig 6c:160 [para 0068]) in a top view (fig 6c).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a liner to provide an etch stop during processing (Yeo [para 0068])
Regarding claim 2, Park in view of Yeo teaches the semiconductor device of claim 1
Park teaches a dielectric layer (fig 11:111 [para 0027]) over and contacting the first gate electrode (fig 11:108 [para 0026]) and the second gate electrode (fig 11:108 [para 0026]), wherein a top surface of the dielectric layer (fig 11:111 [para 0027]) is level with a top surface of the dielectric structure (fig 11:113 [para 0027]).
Regarding claim 4, Park in view of Yeo teaches the semiconductor device of claim 1.
Yeo teaches the liner layer (fig 7:150 [para 0090]) is a first liner layer, further comprising: a second liner layer (fig 7:202 [para 0091]) surrounding each of the first (fig 7:200 [para 0083]) and second (fig 7:201 [para 0091]) segments of the conductive feature in the top view (fig 6c).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a second liner around the conductive feature in order to prevent diffusion of conductive material into the surrounding dielectric.
Regarding claim 5, Park in view of Yeo teaches the semiconductor device of claim 4.
Yeo teaches the first liner layer (fig 7:150 [para 0090]) is thicker than the second liner layer (fig 7:202 [para 0091]).
Regarding claim 6, Park in view Yeo teaches the semiconductor device of claim 4.
Yeo teaches the first liner layer (fig 7:150 [para 0090]) is in contact with the second liner layer (fig 7:202 [para 0091]).
Regarding claim 8, Park in view of Yeo teaches the semiconductor device of claim 1.
Yeo teaches a portion of the liner layer (fig 6c:150 [para 0068]) is directly under the dielectric structure (fig 6c:160 [para 0068]) and separates the dielectric structure (fig 6c:160 [para 0068])] from contacting the substrate (fig 7:50 [para 0030]).
Regarding claim 9, Park in view of Yeo teaches the semiconductor device of claim 1.
Yeo teaches the dielectric structure (fig 6c:160 [para 0068]) includes a bottom dielectric layer (fig 7:150 [para 0068]) and a top dielectric layer (fig 7:160 [para 0068] over the bottom dielectric layer (fig 7:150 [para 0068]), and wherein compositions of the bottom dielectric layer (fig 7:150 [para 0068]) and the top dielectric layer (fig 7:150 [para 0068]) are different ( [para 0068]).
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Claim(s) 11, 12, 13, 14, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2020/0135473) in view of Yeo (US 2018/0151683).
Regarding claim 11.
Park teaches
A semiconductor device, comprising: a metal gate (fig 16,1 [para 0019]) over a channel region (fig 16:103a,103b [para 0020]) of the semiconductor device, wherein the metal gate (fig 16,17:1 [para 0019])extends lengthwise in a first direction; a gate spacer (fig 16:112 [para 0024]) on sidewalls of the metal gate (fig 16,16:108 [para 0024]); […]; a dielectric feature (fig 19:113 [para 0026])[…], wherein a top surface of the dielectric feature (fig 11:113 [para 0026]) is above a gate electrode (fig 11:108 [para 0024]) of the metal gate (fig 11:1 [para 0019]), wherein the dielectric feature (fig 11:113 [para 0026]) extends lengthwise in the first direction (annotated fig 19); and a conductive feature (fig 19:120 [para 0028] divided by the dielectric feature (fig 11:113 [para 0026]) into a first segment (fig 19:120b [para 0029] over and in electrical coupling with a first source/drain region of the semiconductor device and a second segment (fig 19:120c [para 0029]) over and in electrical coupling with a second source/drain region of the semiconductor device (fig 19 [para 0020]).
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Park does not teach a liner surrounding the dielectric feature
Yeo teaches a first liner layer (fig 6c:150 [para 0068]) on sidewalls of the gate spacer (fig 6c,7:24 [para 0048]); a dielectric feature (fig 6c:160 [para 0068]) surrounded by the first liner layer (fig 7:150 [para 0068]) in a top view (fig 6c).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a liner surrounding the dielectric feature in order to serve an etch stop during processing (Yeo [para 0068])
Regarding claim 12, Park in view of Yeo teaches the semiconductor device of claim 11.
Park teaches the channel region (fig 17:103a [para 0020]) and the first source/drain region are parts of a same transistor, and wherein the second source/drain region is a part of another transistor (fig 16,19 [para 0020]).
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Regarding claim 13, Park in view of Yeo teaches the semiconductor device of claim 11.
Yeo teaches a second liner layer (fig 7:202 [para 0083] contacting the first liner layer (fig 7:150 [para 0068]), wherein the conductive feature (fig 7:200 [para 0083]) is surrounded by the second liner layer (fig 7:202 [para 0083]) in the top view (fig 6c).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a second liner around the conductive feature in order to prevent diffusion of conductive material into the surrounding dielectric.
Regarding claim 14, Park in view of Yeo teaches the semiconductor device of claim 13.
Yeo teaches the first liner layer (fig 7:150 [para 0068]) is thicker than the second liner layer (fig 7:202 [para 0083]).
Regarding claim 15, Park in view of Yeo teaches the semiconductor device of claim 13.
Yeo teaches the first liner layer (fig 7:150 [para 0068]) and the second liner layer (fig 7:202 [para 0083]) include different compositions.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2020/0135473) in view of Yeo (US 2018/0151683) as applied to claim 11 and further in Xie (US 10243053)
Regarding claim 16.
Park in view of Yeo teaches elements of the claim 11 above
Park in view of Yeo does not teach the dielectric feature is above a top surface of the conductive feature
Xie teaches the dielectric feature (fig 11:113[column 7 lines 5-15]) is above a top surface of the conductive feature (fig 11:108[column 6 lines 25-35]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the dielectric feature to be above the conductive feature in order to provide space for a capping structure to protect the conductive contact from damage (Xie column 8 lines 30-40).
Claim(s) 21 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2020/0135473) in view of Yeo (US 2018/0151683)
Regarding claim 21.
Park teaches
A semiconductor device, comprising: first (fig 17:103a [para 0020]) and second (fig 17:103b [para 0020]) fins protruding from a substrate (fig 16:102 [para 0019]) and each extending lengthwise in a first direction (fig 19); a gate structure (fig 16:1 [para 0019]) across the first (fig 17:103a [para 0020]) and second (fig 17:103b [para 0020]) fins and extending lengthwise in a second direction perpendicular to the first direction (annotated fig 19); a gate spacer (fig 17:112 [para 0024]) disposed on sidewalls of the gate structure (fig 17:1 [para 0019]); a source/drain contact (fig 17:122a [para 0029]) across the first (fig 17:103a [para 0020]) and second (fig 17:103b [para 0020]) fins and extending lengthwise in the second direction; […] first and second contact isolation features (fig 17:113 [para 0026]) sandwiching the source/drain contact (fig 17:122a [para 0029]) in the second direction […].
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Park does not teach a first liner surrounding the source/drain contact.
Yeo teaches a first liner (fig 7:202 [para 0083]) disposed on the gate spacer (fig 6c:24 [para 0048]) and fully surrounding the source/drain contact (fig 7:200 [para 0083]) in a top view of the semiconductor device (fig 6c); a second liner (fig 6c,7:150 [para 0068]) disposed on the gate spacer (fig 6c:24 [para 0048]) and fully surrounding each of the first and second contact isolation features (fig 6c:160 [para 0068]) in the top view of the semiconductor device (fig 6c), wherein the first liner (fig 7:202 [para 0083]) is in physical contact with the second liner (fig 7:150 [para 0068]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a liner surrounding the contact in order to prevent metal diffusion from the contact into the surrounding dielectric material.
Regarding claim 25, Park in view of Yeo teaches the semiconductor device of claim 21.
Park teaches top surfaces of the first and second contact isolation features (fig 16:113 [para 0026]) are above a top surface of a gate electrode (fig 16:108 [para 0026]) of the gate structure (fig 16:1 [para 0031]).
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Allowable Subject Matter
Claims 3, 7, 10, 23, and 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, the prior art does not teach a semiconductor device, comprising; a fin protruding from a substrate; a first gate structure and a second gate structure over the fin; a liner layer surrounding a dielectric structure; and a conductive feature sandwiched by first and second gate structures, wherein the a first gate contact plug and a second gate contact plug over and contacting the first gate electrode and the second gate electrode, respectively, wherein top portions of the first gate contact plug and the second gate contact plug are in contact with opposing sidewalls of the liner layer, in combination with all other elements of the claim.
Regarding claim 7, the prior art does not teach a semiconductor device, comprising; a fin protruding from a substrate; a first gate structure and a second gate structure over the fin; a liner layer surrounding a dielectric structure; and a conductive feature sandwiched by first and second gate structures, wherein a residue oxide layer sandwiched between bottom portions of the first liner layer and the second liner layer, in combination with all other elements of the claim.
Regarding claim 10, the prior art does not teach a semiconductor device, comprising; a fin protruding from a substrate; a first gate structure and a second gate structure over the fin; a liner layer surrounding a dielectric structure; and a conductive feature sandwiched by first and second gate structures, wherein a top surface of the bottom dielectric layer is above the first gate electrode and the second gate electrode, in combination with all other elements of the claim.
Regarding claim 23, the prior art does not teach a semiconductor device, comprising: first and second fins protruding from a substrate; a first liner disposed on the gate spacer and fully surrounding the source/drain contact; first and second contact isolation features sandwiching the source/drain contact in the second direction; and a second liner disposed on the gate spacer and fully surrounding each of the first and second contact isolation features, wherein the first liner is in physical contact with the second liner, wherein the first liner extends under bottom surfaces of the first and second contact isolation features.
Regarding claim 24, the prior art does not teach a semiconductor device, comprising: first and second fins protruding from a substrate; a first liner disposed on the gate spacer and fully surrounding the source/drain contact; first and second contact isolation features sandwiching the source/drain contact in the second direction; and a second liner disposed on the gate spacer and fully surrounding each of the first and second contact isolation features; a first gate contact disposed on the first gate structure; and a second gate contact disposed on the second gate structure, wherein the first and second gate contacts sandwich one of the first and second contact isolation features, in combination with all other elements of the claim.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 through 16, 21, and 23 through 25 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Rejection of claims 2, 8, 9, 10, and 14 under 35 USC(b) second paragraph in the final rejection mailed 5/30.2025 has been overcome.
Claims 1-2,4-6,8-9,11-16,21 and 25 using Park (US 2020/0135473) in view of Yeo (US 2018/0151683) above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.J.G/ Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 February 2, 2026