DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Previous action: 1, 2, 4, 5, 6, 8, 9, 11, 12, 13, 14, 15, 16, 21, and 25 rejected, 3, 7, 10, 23, and 24 objected.
Present action: 1 through 16, 21, and 24 through 26 rejected
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 through 16, 21, and 24 through 26 is/are rejected under 35 U.S.C. 102(a)(2) and under 35 U.S.C. 102(a)(1) as being anticipated by Huang (US 2021/0057285).
The applied reference has a common Taiwan Semiconductor Manufacturing Company, Ltd. with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding claim 1,
Huang teaches:
A semiconductor device, comprising; a fin (fig 10c:64; [para 0060]) protruding from a substrate (fig 10c:50]0060]);
a first gate structure (fig 9:97c[para 0056]; fig 8b,18a,18b:97,98; [para 0051])and a second gate structure (fig 9:97d[para 0056]; fig 8b,18a,18b:97,98; [para 0051])over the fin (fig 10c:64; [para 0060]);
a dielectric structure (fig 18a-18c:106; [para 0071]), wherein, in a cross-sectional view (fig 18c) of the semiconductor device along a lengthwise direction (18a:D,D) of the fin (fig 10c:64; [para 0060]), the dielectric structure (fig 18a-18c:106; [para 0071]) is disposed between the first and second gate structures (fig 8b,18a,18b:97,98; [para 0051]), wherein the dielectric structure (fig 18a-18c:106; [para 0071])is spaced apart from the fin (fig 18c:64; [para 0076]), and wherein the dielectric structure (fig 18a-18c:106; [para 0071]) extends further from the substrate than a first gate electrode (fig 9:97c[para 0056]; fig 18a,18b:97,98; [para 0072]) of the first gate structure and a second gate electrode (fig 9:97d[para 0056]; fig 18a,18b:97,98 ; [para 0072]) of the second gate structure;
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a liner layer (fig 18c:109; [para 0067]) surrounding the dielectric structure (fig 18a,18c:106; [para 0071]) in a top view (fig 18a);
and a conductive feature (fig 18a-18c:111; [para 0072]) sandwiched by the first and second gate structures (fig 18a-18c:97; [para 0072]), wherein the conductive feature (fig 18b:111; [para 0072]) is divided by the dielectric structure (fig 18a-18c:106; [para 0071])into a first segment and a second segment (fig 18a:97; [para 0076]), wherein the first segment of the conductive feature (fig 18a-18c:111; [para 0072]) is above and electrically coupled to a source/drain region (fig 7:80; [para 0043]) of the fin (fig 7,10c:64; [para 0060]), and wherein the liner layer (fig 18c:90/92,109; [para 0067]) separates the dielectric structure (fig 18a-18c:106; [para 0071]) apart from the conductive feature (fig 18b:111; [para 0076]).
Regarding claim 2.
Huang teaches the semiconductor device of claim 1,
Huang teaches:
a dielectric layer (fig 18b:103; [para 0061]) over and contacting the first gate electrode (fig 9:97c[para 0056]; fig 18a,18b:97; [para 0061]) and the second gate electrode (fig 9:97d[para 0056]; fig 18a,18b:97; [para 0061]), wherein a top surface of the dielectric layer (fig 18a,18b:103; [para 0072]) is level with a top surface of the dielectric structure (fig 18a,18c:106; [para 0071]).
Regarding claim 3.
Huang teaches the semiconductor device of claim 1,
Huang teaches:
a first gate contact plug (fig 18b:121; [para 0076]) and a second gate contact plug (fig 18b:121; [para 0076]) over and contacting the first gate electrode (fig 9:97c[para 0056]; fig 18b:97; [para 0057]) and the second gate electrode (fig 9:97d[para 0056]; fig 18b:97; [para 0057]), respectively, wherein top portions of the first gate contact plug (fig 18b:121; [para 0076]) and the second gate contact plug (fig 18b:121; [para 0076]) are in contact with opposing sidewalls of the liner layer (fig 18c:90/92,109; [para 0067]), respectively.
Regarding claim 4.
Huang teaches the semiconductor device of claim 1,
Huang teaches:
the liner layer (fig 18c:90/92,109; [para 0067]) is a first liner layer (fig 18c:90/92; [para 0067]), further comprising: a second liner layer (fig 18c:109; [para 0059]) surrounding each of the first and second segments of the conductive feature (fig 18a,18b:111; [para 0072]) in the top view.
Regarding claim 5.
Huang teaches the semiconductor device of claim 4,
Huang teaches:
the first liner layer (fig 18c:90/92; [para 0067]) is thicker than the second liner layer (fig 18c:109; [para 0059]).
Regarding claim 6.
Huang teaches the semiconductor device of claim 4,
Huang teaches:
the first liner layer (fig 18c:90/92; [para 0067]) is in contact with the second liner layer (fig 18c:109; [para 0059]).
Regarding claim 7.
Huang teaches the semiconductor device of claim 4,
Huang teaches:
a residue oxide layer (fig 14c; [para 0067]) sandwiched between bottom portions of the first liner layer (fig 18c:90/92; [para 0067]) and the second liner layer (fig 18c:109; [para 0059])
Regarding claim 8.
Huang teaches the semiconductor device of claim 1,
Huang teaches:
a portion of the liner layer (fig 22b,22c:90/92,109; [para 0067,085]) is directly under the dielectric structure (fig 22b:106; [para 0071,0085]) and separates the dielectric structure (fig 22b:106; [para 0071,0085]) from contacting the substrate (fig 22b:50; [para 0085]).
Regarding claim 9.
Huang teaches the semiconductor device of claim 1,
Huang teaches:
the dielectric structure includes a bottom dielectric layer (fig 18a-18c:106; [para 0071]) and a top dielectric layer (fig 18a-18c:107; [para 0063,0071]) over the bottom dielectric layer (fig 18a-18c:105; [para 0062,0071]), and wherein compositions of the bottom dielectric layer (fig 18a-18c:105; [para 0062,0071]) and the top dielectric layer (fig 18a-18c:107; [para 0063,0071]) are different.
Regarding claim 10.
Huang teaches the semiconductor device of claim 9,
Huang teaches:
a top surface of the bottom dielectric layer (fig 18a-18c:105; [para 0071]) is above the first gate electrode (fig 9:97c[para 0056]; fig 18b:97; [para 0057]) and the second gate electrode (fig 9:97d[para 0056]; fig 18b:97; [para 0057]).
Regarding claim 11,
Huang teaches:
A semiconductor device, comprising: a metal gate (fig 18a,18b:97,98; [para 0072]) over a channel region (fig 10c:64; [para 0060]) of the semiconductor device, wherein the metal gate (fig 18a,18b:97,98; [para 0072]) extends lengthwise in a first direction;
a gate spacer (fig 18b:87; [para 0074]) on sidewalls of the metal gate (fig 18a,18b:97,98; [para 0072]);
a first liner layer (fig 18a-c:90,92; [para 0067,085]) on sidewalls of the gate spacer (fig 18b:87; [para 0074]);
a dielectric feature 106 surrounded by the first liner layer (fig 18a-18c:90/92; [para 0067,085]) in a top view, wherein a top surface of the dielectric feature (fig 18a,18c:106; [para 0071]) is above a gate electrode of the metal gate (fig 18a,18b:97,98; [para 0072]), wherein the dielectric feature (fig 18a,18c:106; [para 0071]) extends lengthwise in the first direction (fig 18a:D-D);
and a conductive feature (fig 18a-18c:111; [para 0072]) divided by the dielectric feature (fig 18a,18c:106; [para 0071]) into a first segment over and in electrical coupling with a first source/drain region (fig 7:80; [para 0043]) of the semiconductor device and a second segment over and in electrical coupling with a second source/drain region (fig 7:80; [para 0043]) of the semiconductor device, wherein along the first direction the first liner layer (fig 18a-18c:90/92; [para 0067,085]) includes a first portion disposed between the dielectric feature (fig 18a,18c:106; [para 0071]) and the first segment (fig 18a-18c:111; [para 0072]) and a second portion disposed between the dielectric feature (fig 18a,18c:106; [para 0071]) and the second segment (fig 18a-18c:111; [para 0072]).
Regarding claim 12.
Huang teaches the semiconductor device of claim 11,
Huang teaches:
wherein the channel region (fig 10c:64; [para 0060]) and the first source/drain region (fig 7:80; [para 0043]) are parts of a same transistor, and wherein the second source/drain region (fig 7:80; [para 0043]) is a part of another transistor (fig 18a-18c).
Regarding claim 13.
Huang teaches the semiconductor device of claim 11,
Huang teaches:
a second liner layer (fig 18a-c:109; [para 0067,085]) contacting the first liner layer (fig 18a-c:90/92; [para 0067,0085]), wherein the conductive feature (fig 18b:111; [para 0076]) is surrounded by the second liner layer (fig 18a-c:109; [para 0067,0085]) in the top view (fig 18a).
Regarding claim 14.
Huang teaches the semiconductor device of claim 13,
Huang teaches:
the first liner layer (fig 18a-c:90/92; [para 0067,085]),is thicker than the second liner layer (fig 18a-c:109; [para 0067,0085]).
Regarding claim 15.
Huang teaches the semiconductor device of claim 13,
Huang teaches:
the first liner layer (fig 18a-c:90/92; [para 0071,0085])and the second liner layer (fig 18a-c:109; [para 0068,0085]) include different compositions.
Regarding claim 16.
Huang teaches the semiconductor device of claim 11,
Huang teaches:
the dielectric feature (fig 18a,18c:106; [para 0071]) is above a top surface of the conductive feature (fig 18a-18c:111; [para 0072]).
Regarding claim 21.
Huang teaches:
A semiconductor device, comprising: first and second fins (fig 10c:64; [para 0060]) protruding from a substrate (fig 18a,22b,22c:50; [para 0076]) and each extending lengthwise in a first direction (fig 3,18a:D-D; [para 0028]);
a gate structure (fig 18a,22b,22c:97,98; [para 0072]) across the first and second fins (fig 10c:64; [para 0060]) and extending lengthwise in a second direction (fig 3,18a:C-C; [para 0028]) perpendicular to the first direction (fig 3,18a:D-D; [para 0028]);
a gate spacer (fig 22b,c:87; [para 0074]) disposed on sidewalls of the gate structure (fig 18a,22b,22c:97,98; [para 0072]);
a source/drain contact (fig 18a,22b,22c:111; [para 0072]) across the first and second fins (fig 10c:64; [para 0060]) and extending lengthwise in the second direction (fig 3,18a:C-C; [para 0028]);
a first liner (fig 18a,22b,22c:90/92; [para 0071,0085]) disposed on the gate spacer (fig 18a,22b,22c:87; [para 0074]) and fully surrounding the source/drain contact (fig 18a,22b,22c:111; [para 0072]) in a top view (fig 18a) of the semiconductor device;
first and second contact isolation features (fig 18a,22b,22c:106; [para 0071])sandwiching the source/drain contact (fig 18a,22b,22c:111; [para 0072]) in the second direction (fig 3,18a:C-C; [para 0028]);
and a second liner (fig 18a,22b,22c:109; [para 0071,0085]) disposed on the gate spacer (fig 18a,22b,22c:87; [para 0074]) and fully surrounding each of the first and second contact isolation features (fig 18a,22b,22c:106; [para 0071]) in the top view of the semiconductor device, wherein the first liner (fig 18a,22b,22c:90/92; [para 0071,0085]) is in physical contact with the second liner (fig 18a,22b,22c:109; [para 0071,0085]), and wherein the first liner (fig 18a,22b,22c:90/92; [para 0071,0085]) extends under bottom surfaces (fig 22b) of the first and second contact isolation features (fig 18a,22b,22c:106; [para 0071]).
Regarding claim 24.
Huang teaches the semiconductor device of claim 21,
Huang teaches:
wherein the gate structure (fig 18a,22b,22c:97,98; [para 0072])is a first gate structure (fig 9:97c[para 0056]; fig 18a,22b,22c:97,98; [para 0072]), the semiconductor device further comprising: a second gate structure (fig 9:97d[para 0056]; fig 18a,22b,22c:97,98; [para 0072]) across the first and second fins (fig 10c:64; [para 0060]) and extending lengthwise in the second direction (fig 3,18a:C-C; [para 0028]); a first gate contact (fig 18b:121; [para 0076]) disposed on the first gate structure (fig 9:97c[para 0056]; fig 18a,22b,22c:97,98; [para 0072]);
and a second gate contact (fig 18b:121; [para 0076]) disposed on the second gate structure (fig 9:97d[para 0056]; fig 18a,22b,22c:97,98; [para 0072]), wherein the first and second gate contacts (fig 18b:121; [para 0076]) one of the first and second contact isolation features (fig 18a,22b,22c:106; [para 0071]).
Regarding claim 25.
Huang teaches the semiconductor device of claim 21,
Huang teaches:
top surfaces of the first and second contact isolation features (fig 18a,22b,22c:106; [para 0071])are above a top surface of a gate electrode of the gate structure (fig 18a,22b,22c:97,98; [para 0072]).
Regarding claim 26.
Huang teaches the semiconductor device of claim 1,
Huang teaches:
in the cross-sectional view of the semiconductor device along the lengthwise direction (fig 3,18a:D-D; [para 0028]) of the fin (fig 10c:64; [para 0060]), a top surface of the dielectric structure (fig 18c:106; [para 0071]) is wider than a bottom surface of the dielectric structure (fig 18c:106; [para 0071]).
Allowable Subject Matter
The indicated allowability of claim 1 through 16, 21, and 24 through 25 is withdrawn in view of the newly discovered reference(s) to Huang (US 2021/057285).. Rejections based on the newly cited reference(s) follow.
Conclusion
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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