DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07 July 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, and 8-13 are rejected under 35 U.S.C. 103 as being unpatentable over Kahlert et al. (U.S. 2010/0078821) in view of Erb et al. (U.S. 7,157,795).
Regarding Claim 1, Kahlert et al., Figures 2a and 2f, disclose a semiconductor die, comprising:
a front-end-of-line (FEOL) structure, built on a semiconductor substrate, and comprising active devices (FEOL 203/202 over bottom portion of substrate 201);
a back-end-of-line (BEOL) structure, formed on the FEOL structure, and comprising a stack of metallization layers (metallization of substrate 201 over FEOL 203/202 [0043]);
and bonding metals, disposed on the BEOL structure, and comprising:
a conductive pad, disposed over the BEOL structure, and electrically connected to the metallization layers in the BEOL structure (conductive pad 212);
a conductive capping layer, lining along a top surface of the conductive pad (conductive capping layer 213); and
an engaging feature, landing on the conductive capping layer and separated from the conductive pad by the conductive capping layer (engaging feature 222, “In other cases, when material of the layer 213 is still formed on the surface 212S, the protection layer 233 may also be formed so as to cover the remaining material of the layer 213” [0037]); and
a passivation layer, conformally covering the BEOL structure and a stacking structure comprising the conductive pad and the conductive capping layer, wherein a bottom surface of the passivation layer is aligned with a bottom surface of the stacking structure (Kahlert et al., passivation layer 221/214/211 or 221/214 or 214).
However, they do not explicitly disclose wherein a material of the conductive capping layer comprises titanium, tantalum, tantalum nitride, or titanium nitride or wherein the semiconductor die is bonded to another semiconductor die or a package component by the engaging feature.
It is admitted prior art that it was known in the art to use a conductive engaging feature electrically connected to and formed on a device substrate to bond to another semiconductor die or package component so as to electrically connect the device substrate to a circuit and therefore render the device functional (Officially Noticed facts were not traversed, MPEP §2144.03C). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to bond the semiconductor die to another semiconductor die or a package component by the engaging feature in order to form an electrical circuit and have a functional device.
In the same field of endeavor, Erb et al. discloses a device wherein a conductive capping layer lining a top surface of a conductive pad and separating said conductive pad from an engaging feature comprises titanium, tantalum, tantalum nitride, or titanium nitride (Erb et al., conductive pad 23, conductive capping layer 24 and/or 25, engaging features 30/31, Figure 3). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the conductive capping layer to comprise titanium, tantalum, tantalum nitride, or titanium nitride in Kahlert et al. in view of Erb et al. in order to reduce via resistance and improve electromigration performance (Erb et al., Column 5, Lines 62-67).
Regarding Claim 2, Kahlert et al., Figures 2a and 2f, in view of Erb et al. further disclose the semiconductor die according to claim 1, wherein a sidewall of the conductive capping layer is coplanar with a sidewall of the conductive pad (Kahlert et al., capping layer 213, conductive pad 212).
Regarding Claim 3, Kahlert et al., Figures 2a and 2f, in view of Erb et al. further disclose the semiconductor die according to claim 1, wherein a footprint area of the conductive capping layer is identical with a footprint area of the conductive pad (Kahlert et al., capping layer 213, conductive pad 212).
Regarding Claim 4, Kahlert et al., Figures 2a and 2f, in view of Erb et al. further disclose the semiconductor die according to claim 1, wherein the engaging feature comprises:
a bonding pad, lying over the conductive capping layer, wherein a top surface of the bonding pad defines a portion of a bonding surface of the semiconductor die (Kahlert et al., bonding pad 222L);
and a conductive via, connecting the bonding pad to the conductive capping layer along a vertical direction (Kahlert et al., conductive via 222V).
Regarding Claim 8, Kahlert et al., Figures 2a and 2f, in view of Erb et al. further disclose the semiconductor die according to claim 1, wherein the engaging feature extends through the passivation layer to reach the conductive capping layer (Kahlert et al., passivation layer 221/214/211 or 221/214 or 214).
Regarding Claim 9, Kahlert et al., Figures 2a and 2f, in view of Erb et al. further disclose the semiconductor die according to claim 1, wherein the passivation layer is a multilayer structure, and comprises:
an insulating capping layer, lining along a top surface of the conductive capping layer (Kahlert et al., insulating capping layer 214);
and insulating layers, conformally covering the BEOL structure, the stacking structure comprising the conductive pad and the conductive capping layer, and the insulating capping layer (Kahlert et al., insulating layers 211/221 or 221).
Regarding Claim 10, Kahlert et al., Figures 2a and 2f, in view of Erb et al. further disclose the semiconductor die according to claim 9, wherein a sidewall of the insulating capping layer is coplanar with a sidewall of the conductive capping layer as well as a sidewall of the conductive pad (Kahlert et al., insulating capping layer 214, conductive capping layer 213, conductive pad 212).
Regarding Claim 11, Kahlert et al., Figures 2a and 2f, in view of Erb et al. further discloses semiconductor die according to claim 1, further comprising a bonding layer, laterally surrounding the bonding metals (Kahlert et al., bonding layer 221/211 or 221 or 211).
Regarding Claim 12, Kahlert et al., Figures 2a and 2f, in view of Erb et al. further disclose the semiconductor die according to claim 11, wherein a top surface of the engaging feature is substantially coplanar with a top surface of the bonding layer, and the top surfaces of the engaging feature and the bonding layer collectively define a bonding surface of the semiconductor die (Kahlert et al., bonding layer 211/221 or 221 and engaging feature 222A).
Regarding Claim 13, Kahlert et al., Figures 2a and 2f, in view of Erb et al. further disclose the semiconductor die according to claim 12, wherein the bonding layer is a multilayer structure, and comprising:
a first dielectric layer, covering the conductive pad and the conductive capping layer, and laterally surrounding a lower portion of the engaging feature (first dielectric layer (Kahlert et al., first dielectric layer 221 or 211. Please note that the term “laterally surrounding” does not require direct contact and can include from a footprint/plan view perspective);
a second dielectric layer, laterally surrounding an upper portion of the engaging feature (Kahlert et al., second dielectric layer 211 or 221);
and an etching stop layer, sandwiched between the first and second dielectric layers (Kahlert et al., etching stop layer 214).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kahlert et al. (U.S. 2010/0078821) in view of Erb et al. (U.S. 7,157,795) as applied to Claim 5 above, further in view of Hong et al. (U.S. 2021/0104482).
Regarding Claim 5, Kahlert et al., Figures 2a and 2f, in view of Erb et al. further disclose the semiconductor die according to claim 1, wherein the engaging feature comprises: a conductive pillar, standing on the conductive capping layer (Kahlert et al., pillar 222V).
However, they but they do not explicitly disclose wherein a top surface of the conductive pillar defines a portion of a bonding surface of the semiconductor die. In the same field of endeavor, Hong et al. discloses a device wherein a conductive pillar formed over a conductive pad of a substrate has a top surface that defines a portion of a bonding surface of said semiconductor die, wherein the bonding surface is directly bonded to another device (Hong et al., conductive pillar/bonding pad 130, conductive pad 110, substrate 101, Figure 10b [0075]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the top surface of the conductive pillar to define a portion of a bonding surface of the semiconductor die in Kahlert et al. in view of Erb et al., furth in view of Hong in order to have a device with excellent bonding reliability (Hong et al., [0004]). Furthermore, it has been held that a conclusion of obviousness can be drawn from “(A) combining prior art elements according to known methods to yield predictable results; (B) simple substitution of one known element for another to obtain predictable results” such as forming a dual damascene bonding pad to be a single damascene bonding pad and therefore form it as a conductive pillar, in KSR International Co. v. Teleflex Inc., 550 U.S. 398, 420, 82 USPQ2d 1385, 1397 (2007).
Claims 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (U.S. 2019/0131277) in view of Erb et al. (U.S. 7,157,795).
Regarding Claim 15, Yang et al., Figures 1d and 2, discloses a semiconductor package, comprising:
a first semiconductor die and a second semiconductor die (first die 100/115, second die 200/215), respectively comprising:
a front-end-of-line (FEOL) structure, built on a semiconductor substrate (FEOL 102/103, 202/203);
a back-end-of-line (BEOL) structure, formed on the FEOL structure, and comprising a stack of metallization layers (BEOL 104, 204);
a conductive pad, disposed over the BEOL structure (pad 124, 224);
a top portion of the conductive pad, lining along a top surface of the conductive pad (top portion of pad 124, 224);
an engaging feature, landing on the top portion of the conductive pad and separated from the conductive pad by the top portion of the conductive pad (engaging feature 120/122, 220/226);
a bonding layer, laterally surrounding the conductive pad, the top portion of the conductive pad, the conductive via and the bonding pad (bonding layer 115/110 or 115, 215/210 or 215),
wherein the bonding pad of the first semiconductor die is bonded with the bonding pad of the second semiconductor die, and the bonding layer of the first semiconductor die is bonded with the bonding layer of the second semiconductor die (bonding pad 118, 120, bonding layer 115/110 or 115, 215/210 or 215); and
a passivation layer, conformally covering the BEOL structure, the conductive pad and the conductive capping layer, wherein a bottom surface of the passivation layer is aligned with a bottom surface of the conductive pad (passivation layer 110 or 110/116a or 110/116a/118, 210 or 210/216a or 210/216a/218).
However, they do not explicitly disclose that the top portion of the conductive pad is a conductive capping layer, wherein a material of the conductive capping layer comprises titanium, tantalum, tantalum nitride, or titanium nitride or wherein the engaging feature comprises a conductive via and a bonding pad. In the same field of endeavor, Erb et al. discloses a device wherein a conductive capping layer lining a top surface of a conductive pad and separating said conductive pad from an engaging feature comprises a material of titanium, tantalum, tantalum nitride, or titanium nitride and wherein the engaging feature comprises a conductive via and a bonding pad (Erb et al., conductive pad 23, conductive capping layer 24 and/or 25, engaging features 30/31, conductive via 31b, bonding pad 31a, Figure 3). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the top portion of the conductive pad to be a conductive capping layer, wherein a material of the conductive capping layer comprises titanium, tantalum, tantalum nitride, or titanium nitride and wherein the engaging feature comprises a conductive via and a bonding pad in Yang et al. in view of Erb et al. in order to reduce via resistance and improve electromigration performance (Erb et al., Column 5, Lines 62-67). Furthermore, it has been held that a conclusion of obviousness can be drawn from “combining prior art elements according to known methods to yield predictable results,” such as “forming an engaging feature to comprise a bonding pad and a conductive via", in KSR International Co. v. Teleflex Inc., 550 U.S. 398, 420, 82 USPQ2d 1385, 1397 (2007).
Regarding Claim 16, Yang et al. in view of Erb et al. further discloses semiconductor package according to claim 15, further comprising a dielectric material formed on a peripheral portion of the first semiconductor die and laterally surrounding the second semiconductor die (Yang et al., Figure 2, dielectric layer 128 [0040]).
Regarding Claim 17, Yang et al. in view of Erb et al. further discloses semiconductor package according to claim 16, further comprising a through dielectric via penetrating through the dielectric material (Yang et al., Figure 2, via 132, dielectric 128).
Regarding Claim 18, Yang et al. in view of Erb et al. further discloses semiconductor package according to claim 16, further comprising a backside interconnection structure disposed on the second semiconductor die and the dielectric material (Yang et al., Figure 2, backside interconnection structure 140).
Regarding Claim 19, Yang et al. in view of Erb et al. further discloses semiconductor package according to claim 15, wherein the second semiconductor die further comprises a through substrate via extending into the FEOL structure from a back surface of the second semiconductor die facing away from the first semiconductor die (Yang et al., Figure 2, through substrate via 130).
Response to Arguments
Applicant's arguments filed 06 July 2026 have been fully considered but they are not persuasive.
Regarding Claims 1 and 15, the Applicant argues that the Kahlert reference fails to disclose “a bottom surface of the passivation layer is aligned with a bottom surface of the stacking structure” because “none of the dielectric material 211, layer 214 or dielectric material 221 has a bottom surface that is aligned with the bottom surface of the metal region 212”. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., a bottom surface of the passivation layer is coplanar with a bottom surface of the stacking structure) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). The term “aligned” has a more broad definition than that of coplanar, wherein coplanar requires a shared plane and “aligned” is defined as “adjusted or synchronized for coordinated functioning; in alignment”. The relative positioning of the dielectric material 211, layer 214, and 221 are all aligned for coordinated functioning, their bottom surfaces are parallel to the bottom surface of the stacking structure, and the bottom surface of the stacking structure that is coplanar with the side surfaces of the dielectric layer 211 and aligned with and intersect with the bottom surface of layer 114 at a 90º angle. Therefore, the arguments are not persuasive.
Conclusion
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Abbigale Boyle whose telephone number is 571-270-7919. The Examiner can normally be reached from 11 A.M to 7 P.M., Monday through Friday.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Zandra Smith, can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Abbigale Boyle
Examiner, Art Unit 2899
/ABBIGALE A BOYLE/Examiner, Art Unit 2899
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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