DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings were received on 17 December 2025. These drawings are unacceptable.
New corrected drawings in compliance with 37 CFR 1.84 and 37 CFR 1.121 are required in this application because:
The sheets of drawings should be numbered in consecutive Arabic numerals, starting with 1. The drawing sheet numbering must be clear and larger than the numbers used as reference characters to avoid confusion. The number of each sheet should be shown by two Arabic numerals placed on either side of an oblique line, with the first being the sheet number and the second being the total number of sheets of drawings, with no other marking. See Page(s) 1-35.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Bonding Layer Comprising Bonding Pad Over Conductive Pad Having Conductive Capping Layer
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, and 8-13 are rejected under 35 U.S.C. 103 as being unpatentable over Kahlert et al. (U.S. 2010/0078821) in view of Erb et al. (U.S. 7,157,795).
Regarding Claim 1, Kahlert et al., Figures 2a and 2f, disclose a semiconductor die, comprising:
a front-end-of-line (FEOL) structure, built on a semiconductor substrate, and comprising active devices (FEOL 203/202 over bottom portion of substrate 201);
a back-end-of-line (BEOL) structure, formed on the FEOL structure, and comprising a stack of metallization layers (metallization of substrate 201 over FEOL 203/202 [0043]);
and bonding metals, disposed on the BEOL structure, and comprising:
a conductive pad, disposed over the BEOL structure, and electrically connected to the metallization layers in the BEOL structure (conductive pad 212);
a conductive capping layer, lining along a top surface of the conductive pad (conductive capping layer 213);
and an engaging feature, landing on the conductive capping layer and separated from the conductive pad by the conductive capping layer (engaging feature 222, “In other cases, when material of the layer 213 is still formed on the surface 212S, the protection layer 233 may also be formed so as to cover the remaining material of the layer 213” [0037]).
However, they do not explicitly disclose wherein a material of the conductive capping layer comprises titanium, tantalum, tantalum nitride, or titanium nitride or wherein the semiconductor die is bonded to another semiconductor die or a package component by the engaging feature.
The Examiner takes Official Notice of the fact that it was known in the art to use a conductive engaging feature electrically connected to and formed on a device substrate to bond to another semiconductor die or package component so as to electrically connect the device substrate to a circuit and therefore render the device functional. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to bond the semiconductor die to another semiconductor die or a package component by the engaging feature in order to form an electrical circuit and have a functional device.
In the same field of endeavor, Erb et al. discloses a device wherein a conductive capping layer lining a top surface of a conductive pad and separating said conductive pad from an engaging feature comprises titanium, tantalum, tantalum nitride, or titanium nitride (Erb et al., conductive pad 23, conductive capping layer 24 and/or 25, engaging features 30/31, Figure 3). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the conductive capping layer to comprise titanium, tantalum, tantalum nitride, or titanium nitride in Kahlert et al. in view of Erb et al. in order to reduce via resistance and improve electromigration performance (Erb et al., Column 5, Lines 62-67).
Regarding Claim 2, Kahlert et al., Figures 2a and 2f, in view of Erb et al. further disclose the semiconductor die according to claim 1, wherein a sidewall of the conductive capping layer is coplanar with a sidewall of the conductive pad (Kahlert et al., capping layer 213, conductive pad 212).
Regarding Claim 3, Kahlert et al., Figures 2a and 2f, in view of Erb et al. further disclose the semiconductor die according to claim 1, wherein a footprint area of the conductive capping layer is identical with a footprint area of the conductive pad (Kahlert et al., capping layer 213, conductive pad 212).
Regarding Claim 4, Kahlert et al., Figures 2a and 2f, in view of Erb et al. further disclose the semiconductor die according to claim 1, wherein the engaging feature comprises:
a bonding pad, lying over the conductive capping layer, wherein a top surface of the bonding pad defines a portion of a bonding surface of the semiconductor die (Kahlert et al., bonding pad 222L);
and a conductive via, connecting the bonding pad to the conductive capping layer along a vertical direction (Kahlert et al., conductive via 222V).
Regarding Claim 8, Kahlert et al., Figures 2a and 2f, in view of Erb et al. further disclose the semiconductor die according to claim 1, further comprising: a passivation layer, conformally covering the BEOL structure and a stacking structure comprising the conductive pad and the conductive capping layer, wherein the engaging feature extends through the passivation layer to reach the conductive capping layer (Kahlert et al., passivation layer 221/214/21).
Regarding Claim 9, Kahlert et al., Figures 2a and 2f, in view of Erb et al. further disclose the semiconductor die according to claim 8, wherein the passivation layer is a multilayer structure, and comprises:
an insulating capping layer, lining along a top surface of the conductive capping layer (Kahlert et al., insulating capping layer 214);
and insulating layers, conformally covering the BEOL structure, the stacking structure comprising the conductive pad and the conductive capping layer, and the insulating capping layer (Kahlert et al., insulating layers 211/221).
Regarding Claim 10, Kahlert et al., Figures 2a and 2f, in view of Erb et al. further disclose the semiconductor die according to claim 9, wherein a sidewall of the insulating capping layer is coplanar with a sidewall of the conductive capping layer as well as a sidewall of the conductive pad (Kahlert et al., insulating capping layer 214, conductive capping layer 213, conductive pad 212).
Regarding Claim 11, Kahlert et al., Figures 2a and 2f, in view of Erb et al. further discloses semiconductor die according to claim 1, further comprising a bonding layer, laterally surrounding the bonding metals (Kahlert et al., bonding layer 211/214/221).
Regarding Claim 12, Kahlert et al., Figures 2a and 2f, in view of Erb et al. further disclose the semiconductor die according to claim 11, wherein a top surface of the engaging feature is substantially coplanar with a top surface of the bonding layer, and the top surfaces of the engaging feature and the bonding layer collectively define a bonding surface of the semiconductor die (Kahlert et al., bonding layer 211/214/221 and engaging feature 222A).
Regarding Claim 13, Kahlert et al., Figures 2a and 2f, in view of Erb et al. further disclose the semiconductor die according to claim 12, wherein the bonding layer is a multilayer structure, and comprising:
a first dielectric layer, covering the conductive pad and the conductive capping layer, and laterally surrounding a lower portion of the engaging feature (first dielectric layer (Kahlert et al., first dielectric layer 221 or 211. Please note that the term “laterally surrounding” does not require direct contact and can include from a footprint/plan view perspective);
a second dielectric layer, laterally surrounding an upper portion of the engaging feature (Kahlert et al., second dielectric layer 211 or 221);
and an etching stop layer, sandwiched between the first and second dielectric layers Kahlert et al., (etching stop layer 214).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kahlert et al. (U.S. 2010/0078821) Erb et al. (U.S. 7,157,795) as applied to Claim 5 above, further in view of Hong et al. (U.S. 2021/0104482).
Regarding Claim 5, Kahlert et al., Figures 2a and 2f, in view of Erb et al. further disclose the semiconductor die according to claim 1, wherein the engaging feature comprises: a conductive pillar, standing on the conductive capping layer (Kahlert et al., pillar 222V).
However, they but they do not explicitly disclose wherein a top surface of the conductive pillar defines a portion of a bonding surface of the semiconductor die. In the same field of endeavor, Hong et al. discloses a device wherein a conductive pillar formed over a conductive pad of a substrate has a top surface that defines a portion of a bonding surface of said semiconductor die, wherein the bonding surface is directly bonded to another device (Hong et al., conductive pillar/bonding pad 130, conductive pad 110, substrate 101, Figure 10b [0075]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the top surface of the conductive pillar to define a portion of a bonding surface of the semiconductor die in Kahlert et al. in view of Erb et al., furth in view of Hong in order to have a device with excellent bonding reliability (Hong et al., [0004]). Furthermore, it has been held that a conclusion of obviousness can be drawn from “(A) combining prior art elements according to known methods to yield predictable results; (B) simple substitution of one known element for another to obtain predictable results” such as forming a dual damascene bonding pad to be a single damascene bonding pad and therefore form it as a conductive pillar, in KSR International Co. v. Teleflex Inc., 550 U.S. 398, 420, 82 USPQ2d 1385, 1397 (2007).
Claims 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (U.S. 2019/0131277) in view of Kahlert et al. (U.S. 2010/0078821).
Regarding Claim 15, Yang et al., Figures 1d and 2, discloses a semiconductor package, comprising:
a first semiconductor die and a second semiconductor die (first die 100/115, second die 200/215), respectively comprising:
a front-end-of-line (FEOL) structure, built on a semiconductor substrate (FEOL 102/103, 202/203);
a back-end-of-line (BEOL) structure, formed on the FEOL structure, and comprising a stack of metallization layers (BEOL 104, 204);
a conductive pad, disposed over the BEOL structure (pad 124, 224);
a top portion of the conductive pad, lining along a top surface of the conductive pad (top portion of pad 124, 224);
an engaging feature, landing on the top portion of the conductive pad and separated from the conductive pad by the top portion of the conductive pad (engaging feature 118, 120);
and a bonding layer, laterally surrounding the conductive pad, the top portion of the conductive pad, the conductive via and the bonding pad (bonding layer 115, 215),
wherein the bonding pad of the first semiconductor die is bonded with the bonding pad of the second semiconductor die, and the bonding layer of the first semiconductor die is bonded with the bonding layer of the second semiconductor die (bonding pad 118, 120, bonding layer 115, 215).
However, they do not explicitly disclose that the top portion of the conductive pad is a conductive capping layer, wherein a material of the conductive capping layer comprises titanium, tantalum, tantalum nitride, or titanium nitride or wherein the engaging feature comprises a conductive via and a bonding pad. In the same field of endeavor, Erb et al. discloses a device wherein a conductive capping layer lining a top surface of a conductive pad and separating said conductive pad from an engaging feature comprises a material of titanium, tantalum, tantalum nitride, or titanium nitride and wherein the engaging feature comprises a conductive via and a bonding pad (Erb et al., conductive pad 23, conductive capping layer 24 and/or 25, engaging features 30/31, conductive via 31b, bonding pad 31a, Figure 3). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the top portion of the conductive pad to be a conductive capping layer, wherein a material of the conductive capping layer comprises titanium, tantalum, tantalum nitride, or titanium nitride and wherein the engaging feature comprises a conductive via and a bonding pad in Yang et al. in view of Erb et al. in order to reduce via resistance and improve electromigration performance (Erb et al., Column 5, Lines 62-67). Furthermore, it has been held that a conclusion of obviousness can be drawn from “combining prior art elements according to known methods to yield predictable results,” such as “forming an engaging feature to comprise a bonding pad and a conductive via", in KSR International Co. v. Teleflex Inc., 550 U.S. 398, 420, 82 USPQ2d 1385, 1397 (2007).
Regarding Claim 16, Yang et al. in view of Erb et al. further discloses semiconductor package according to claim 15, further comprising a dielectric material formed on a peripheral portion of the first semiconductor die and laterally surrounding the second semiconductor die (Yang et al., Figure 2, dielectric layer 128 [0040]).
Regarding Claim 17, Yang et al. in view of Erb et al. further discloses semiconductor package according to claim 16, further comprising a through dielectric via penetrating through the dielectric material (Yang et al., Figure 2, via 132, dielectric 128).
Regarding Claim 18, Yang et al. in view of Erb et al. further discloses semiconductor package according to claim 16, further comprising a backside interconnection structure disposed on the second semiconductor die and the dielectric material (Yang et al., Figure 2, backside interconnection structure 140).
Regarding Claim 19, Yang et al. in view of Erb et al. further discloses semiconductor package according to claim 15, wherein the second semiconductor die further comprises a through substrate via extending into the FEOL structure from a back surface of the second semiconductor die facing away from the first semiconductor die (Yang et al., Figure 2, through substrate via 130).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The following Officially Noticed facts were not challenged in the present response:
It was known in the art to use “a conductive engaging feature electrically connected to and formed on a device substrate to bond to another semiconductor die or package component so as to electrically connect the device substrate to a circuit and therefore render the device functional”.
Since these Officially Noticed facts were not traversed, these facts are taken to be admitted prior art (MPEP §2144.03C). Please note that, even though a fact is taken to be admitted prior art, the application of that fact in rendering obvious the claimed features may be traversed in the same manner as if the admitted prior art fact had been presented within a reference.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Abbigale Boyle whose telephone number is 571-270-7919. The Examiner can normally be reached from 11 A.M to 7 P.M., Monday through Friday.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Zandra Smith, can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Abbigale Boyle
Examiner, Art Unit 2899
/ABBIGALE A BOYLE/Examiner, Art Unit 2899
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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