Prosecution Insights
Last updated: July 17, 2026
Application No. 17/731,853

NANOWIRE/NANOSHEET DEVICE WITH SUPPORT PORTION, METHOD OF MANUFACTURING THE SAME AND ELECTRONIC APPARATUS

Final Rejection §103
Filed
Apr 28, 2022
Priority
Apr 29, 2021 — CN 202110477577.1
Examiner
PURVIS, SUE A
Art Unit
2800
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Chinese Academy of Sciences
OA Round
2 (Final)
65%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
82%
With Interview

Examiner Intelligence

Grants 65% — above average
65%
Career Allowance Rate
52 granted / 80 resolved
-3.0% vs TC avg
Strong +17% interview lift
Without
With
+16.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
16 currently pending
Career history
111
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
66.3%
+26.3% vs TC avg
§102
15.3%
-24.7% vs TC avg
§112
14.6%
-25.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 80 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-9, 17, and 18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims in U.S. Patent No. 12,176,393 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application are compared to claims of the patent below. Instant application (17/731,853) US Patent No. 12,176,393 1. A nanowire/nanosheet device, comprising: a substrate; a first source/drain layer and a second source/drain layer opposite to each other in a first direction on the substrate; a first nanowire/nanosheet spaced apart from a surface of the substrate and extending from the first source/drain layer to the second source/drain layer; a plurality of support portions penetrating the first nanowire/nanosheet in a direction perpendicular to the surface of the substrate; and a gate stack extending in a second direction to surround the first nanowire/nanosheet, wherein the second direction intersects the first direction, wherein the plurality of support portions are in direct contact with the substrate. 1. A nanowire/nanosheet device comprising: a substrate; a first source/drain layer and a second source/drain layer opposite to each other in a first direction on the substrate; a first nanowire/nanosheet and a second nanowire/nanosheet, wherein the first nanowire/nanosheet and the second nanowire/nanosheet are spaced apart from a surface of the substrate, the first nanowire/nanosheet and the second nanowire/nanosheet extend from the first source/drain layer to the second source/drain layer, respectively, and are arranged adjacent to each other in a direction parallel to the surface of the substrate; a first support portion connected between the first nanowire/nanosheet and the second nanowire/nanosheet; and a gate stack extending in a second direction to surround the first nanowire/nanosheet wherein the second direction intersects the first direction, a third nanowire/nanosheet and a fourth nanowire/nanosheet, wherein the third nanowire/nanosheet and the fourth nanowire/nanosheet are spaced apart from the surface of the substrate, the third nanowire/nanosheet and the fourth nanowire/nanosheet extend from the first source/drain layer to the second source/drain layer, respectively, and are arranged adjacent to each other in the direction parallel to the surface of the substrate; and a second support portion connected between the third nanowire/nanosheet and the fourth nanowire/nanosheet, wherein the third nanowire/nanosheet is substantially aligned with the first nanowire/nanosheet in a direction perpendicular to the surface of the substrate, the fourth nanowire/nanosheet is substantially aligned with the second nanowire/nanosheet in the direction perpendicular to the surface of the substrate, and the second support portion is substantially aligned with the first support portion in the vertical direction, and wherein the gate stack further surrounds the third nanowire/nanosheet and the fourth nanowire/nanosheet. Regarding claim 1, the claim is rendered obvious in view of the US 12,176,393 claim 1. The claims are compared above. While the claims are not identical, they are not considered to be distinct, partly because the claim of the instant application is broader than the allowed claim. Further, the claim limitation “spaced apart from a surface of the substrate and extending from the first source/drain layer to the second source/drain layer;” is taught by the claim language of the published patent’s claim 1 that “the first nanowire/nanosheet … extend from the first source/drain layer to the second source/drain layer, respectively;” Further, the claim limitation “a plurality of support portions penetrating the first nanowire/nanosheet in a direction perpendicular to the surface of the substrate;” is taught by the claim language of the published patent’s claim 1 that “a first support portion connected between the first nanowire/nanosheet and the second nanowire/nanosheet;”. 4. The nanowire/nanosheet device according to claim 1, wherein a minimum dimension of the support portion is 5nm to 30nm. 11. The nanowire/nanosheet device according to claim 1, wherein the first support portion has a width in a range of 5 nm to 15 nm. Regarding claim 4, the claim is rendered obvious in view of the published patent’s claim 11. The nearly identical portions of the claims are included above. The claims are not identical, but they are not patentably distinct because claim 4 would have been obvious over claim 11. The wording difference between “a minimum dimension of the support portion” and “the first support portion has a width” is obvious and does not make claim 4 of the instant application patentably distinct over patent claim 11. Furthermore, the range of 5 nm to 15 nm cited in US 12,176,393 claim 11 is narrower than the range of 5nm to 30nm cited in claim 4 of the instant application. Thus, the narrow range of the patent anticipates the broader range of the instant application. 5. The nanowire/nanosheet device according to claim 1, wherein a spacing between the plurality of support portions is 5nm to 20nm. 7. The nanowire/nanosheet device according to claim 5, a minimum spacing among the plurality of openings is in a range of 5 nm to 20 nm. Regarding claim 5, the claim is rendered obvious in view of the US 12,176,393 claim 7. The nearly identical portions of the claims are included above. The claims are not identical, but claim 5 is not patentably distinct because it would have been obvious over claim 7. The wording difference between “a spacing between the plurality of support portions” and “a minimum spacing among the plurality of openings is in a range” is obvious and does not make claim 5 of the instant application patentably distinct over patent claim 7. 17. An electronic apparatus comprising the nanowire/nanosheet device according to claim 1. 12. An electronic apparatus comprising the nanowire/nanosheet device according to claim 1. 18. The electronic apparatus according to claim 17, wherein the electronic apparatus comprises a smart phone, a personal computer, a tablet computer, an artificial intelligence device, a wearable device or a power supply. 13. The electronic apparatus according to claim 12, wherein the electronic apparatus comprises a smart phone, a personal computer, a tablet computer, an artificial intelligence apparatus, a wearable device, or a portable power supply. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al (US PGPub 2021/0083127 A1). Regarding claim 1, Xie teaches a nanowire/nanosheet device (see figs. 16b and 18E), comprising: a substrate (140) (para. [0045]); a first source/drain layer and a second source/drain layer (185, on each side of Fig. 16B) opposite to each other in a first direction on the substrate (140); a first nanowire/nanosheet (110) spaced apart from a surface of the substrate and extending from the first source/drain layer to the second source/drain layer (see Fig. 16B); a plurality of support portions penetrating the first nanowire/nanosheet in a direction perpendicular to the surface of the substrate (vertical support structure / pillar 1801 embodiment; See [0085]-[0087], [0090]-[0093], Fig. 18A, 18B, and 18C); a gate stack (191) extending in a second direction to surround the first nanowire/nanosheet, wherein the second direction intersects the first direction. Xie does not explicitly show that the plurality of support portions are in direct contact with the substrate. It would have been obvious to one having ordinary skill in the art before the effective filing date to have the plurality of support potions in direct contact with the substrate Xie, because it would provide a more rigid and stable anchoring of the support structures, thereby better resisting nanosheet deformation, bending, or stiction during fabrication and post-release handling, as expressly recognized by Xie. Such a modification would merely constitute a predictable use of known structural anchoring techniques to improve the mechanical support function already taught by Xie. Regarding claim 2, Xie discloses the nanowire/nanosheet device according to claim 1, further comprising: a second nanowire/nanosheet spaced apart from the surface of the substrate and extending from the first source/drain layer to the second source/drain layer (See Fig. 16B and 18E; disclosure is to a stack of nano-sheets rather than only a single sheet), wherein the first nanowire/nanosheet and the second nanowire/nanosheet are at different heights relative to the substrate (See Fig. 16B and 18E), wherein the plurality of support portions further penetrate the second nanowire/nanosheet in the vertical direction, and is physically connected to the first nanowire/nanosheet and the second nanowire/nanosheet (See Fig. 16B and 18E), and wherein the gate stack surrounds the second nanowire/nanosheet ([0025]). Regarding claim 3, Xie discloses the nanowire/nanosheet device according to claim 2, wherein the first nanowire/nanosheet and the second nanowire/nanosheet are substantially aligned in the vertical direction ([0037], [0086]). Regarding claim 4, Xie discloses the nanowire/nanosheet device according to claim 1, wherein a minimum dimension of the plurality of support portions is 5nm to 30nm (support pillar widths such as 8–15 nm for vertical opening/pillar formation. See [0055], [0088]). 6. The nanowire/nanosheet device according to claim 1, wherein the plurality of support portions comprise a dielectric material. Claims 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Xie as applied to claim 1 above, and further in view of Glass et al. (US PGPub 2020/0357930 A1). Regarding claim 17, Xie teaches the limitations of claim 1 as provided above. Xie does not teach an electronic apparatus comprising the nanowire/nanosheet device according to claim 1. However, in a similar field of endeavor, Glass teaches (para. [0110], "the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the arts"). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Glass into the nanowire/nanosheet device of Xie to form a device with a nanowire/nanosheet device useful in various devices. One would have been motivated to do so as incorporating the instant device into a larger apparatus allows it to actually be put to use, rather than just being a component of a device. Regarding claim 18, Xie in view of Glass teach the limitations of claim 17 as provided above. Glass further teaches the electronic apparatus comprises a smart phone, a personal computer, a tablet computer, an artificial intelligence device, a wearable device or a power supply (para. [0110], "For example, in computer systems (e.g., desktop, laptop, server), cellular phones, personal electronics, etc."). Response to Arguments Applicant’s arguments with respect to claim(s) May 28, 2025 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUE A PURVIS whose telephone number is (571)272-1236. The examiner can normally be reached M-F 0830 to 1630. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Apr 28, 2022
Application Filed
Mar 14, 2025
Non-Final Rejection mailed — §103
May 28, 2025
Response Filed
Jun 16, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
65%
Grant Probability
82%
With Interview (+16.9%)
3y 4m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 80 resolved cases by this examiner. Grant probability derived from career allowance rate.

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