Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed April 29th, 2026, have been fully considered but they are not persuasive.
Applicant argues (pgs. 6-7, “Remarks”) that Yuan’s method is not capable of any drying steps and that Usenko discloses drying the wafer in a separate process, in a separate piece of equipment. Further, the office distinguishes Yuan-Usenko as requiring “removal of the wafer from one process environment, transferring to a separate environment, and then drying.” Thus, it would not have been obvious to a person of ordinary skill in the art to combine Matsumura with Yuan-Usenko since both Yuan and Usenko teaches away from Matsumura and the claimed invention.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). In this instance, applicant is attacking Yuan and Usenko for not teaching a single process environment where it is Matsumura that teaches a single process environment for the reasons of increasing productivity, helping prevent dropped substrates, and making the apparatus compact as detailed in the rejection below.
Therefore, applicant’s arguments are not persuasive.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 11 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
In this instance, Claim 11 states “the dry-in and dry-out porosification process is performed in a single process environment” in lines 4-5. While applicant’s filed specification ([0103], [0105]) teaches that the materials are processed in a suitable dry-in/dry-out porous silicon tool, there is no detailing of the tool and its properties. It is not expressly stated that such a tool contains only a single process environment or what a potential process environment may include. Therefore, applicant does not have support for the limitation recited above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate that the corresponding limitations are addressed with a secondary reference/embodiment in an obviousness analysis.
Claims 11-12, 15-16, 18-20, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Yuan (2001/0023111 A1; hereinafter Yuan) in view of Usenko (2018/0047614 A1; hereinafter Usenko) and Matsumura et al. (2003/0121773 A1; hereinafter Matsumura).
Regarding Claim 11, Yuan (figs. 5a and 7b) teaches a method comprising:
forming a porous layer ([0044], 112) over a wafer ([0044], 110), the porous layer (112) having a higher resistivity than the wafer ([0046], porous silicon has a resistivity on the order of 10 kΩ*cm while the substrate has a resistivity on the order of .01 Ω*cm), wherein
forming the porous layer (112) comprises a dry-in and dry-out porosification process ([0041]-[0043]), wherein the dry-in and dry-out porosification process is performed in a single process environment, the dry-in and dry-out porosification process comprises:
exposing the wafer (110) to an acid solution ([0041], electrolyte containing HF);
passing an electrolyzing current ([0041], “provides a current source”) through the wafer (110) and the acid solution to form the porous layer (112); and
drying the porous layer;
growing an epitaxial layer ([0044], 114) directly over the porous layer (112); and
forming a semiconductor device ([0049], CMOS chip) in the epitaxial layer (114), wherein
a porosity of the porous layer (112) reduces radio frequency (RF) bleeding ([0047], “exhibits high resistivity to signals propagating through the passive components thus limiting coupling losses in the substrate 110”) from the semiconductor device (152, 154, 156) into the wafer (110).
Yuan doesn’t explicitly teach drying the porous layer.
However, Usenko (fig. 3) teaches drying ([0040]) the porous layer ([0024], 44). Usenko also teaches that drying the porous layer oxidizes the pores with native oxide ([0040]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Yuan to include the drying of Usenko to form native oxide in the pores.
Yuan doesn’t explicitly teach the dry-in and dry-out porosification process is performed in a single process environment.
However, Matsumura teaches the dry-in and dry-out porosification process ([0103], anodizing, washing, drying) is performed in a single process environment ([0103], all performed in apparatus 100). Matsumura also teaches that the substrate isn’t conveyed between units for individually performing the process steps and increases productivity, helps prevent dropped substrates, and can make the apparatus compact ([0103]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Yuan to include the single process environment of Matsumura to increase productivity and compactify the apparatus.
Regarding Claim 12, Yuan (figs. 5a and 7b) teaches the method of claim 11, wherein forming the porous layer (112) comprises forming the porous layer (112) over an entirety (see figs. 5a and 7b) of the wafer (110).
Regarding Claim 15, Yuan (figs. 5a and 7b) teaches the method of claim 11, wherein the semiconductor device comprises a transistor ([0049], CMOS chip, see fig. 7b) of a radio frequency (RF) switch. Yuan doesn’t explicitly teach that the transistor is of a radio frequency (RF) switch.
However, Usenko (fig. 3) teaches the semiconductor device comprises a radio frequency (RF) switch ([0011]). Usenko also teaches wanting to use high resistivity wafers for RF related devices in order to reduce loss ([0011]) wherein the high resistivity wafers include porosified silicon ([0024]). One of ordinary skill in the art would have found it obvious to try and form an RF switch over a high resistivity wafer including a porous layer and yielded the predictable results of reduced losses in the system.
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention form an RF switch over a high resistivity wafer including a porous layer since this limitation is one of a finite number of identified, predictable potential solutions. This is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Regarding Claim 16, Yuan doesn’t explicitly teach the method of claim 11, further comprising annealing the porous layer prior to growing the epitaxial layer.
However, Usenko (fig. 3) teaches annealing ([0042]) the porous layer ([0024], 44) prior to growing the epitaxial layer ([0025], 48). Usenko also teaches that annealing the porous layer thermally oxidizes the pores ([0042]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Yuan to include the annealing of Usenko to thermally oxidize the porous layer.
Regarding Claim 18, Yuan doesn’t explicitly teach the method of claim 11, wherein the porosity of the porous layer is between about 35% and about 65%.
However, Usenko (fig. 3) teaches the porosity of the porous layer ([0024], 44) is between about 35% and about 65% ([0039]).
Porosity, however, will not support the patentability of the subject matter encompassed by the prior art unless there is evidence indicating such porosity is critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality of the claimed porosity, and similar porosity is used for porous layers in the art, it would have been obvious to one of ordinary skill in the art to select the appropriate porosity of the porous layer.
Regarding Claim 19, Yuan (figs. 5a and 7b) teaches the method of claim 11, wherein forming the porous layer (112) comprises porosifying an upper portion of the wafer (112, see figs. 5a and 7b).
Regarding Claim 20, Yuan (figs. 5a and 7b) teaches the method of claim 11, wherein the wafer (110) comprises a silicon wafer ([0041], “silicon wafer”).
Regarding Claim 22, Yuan (figs. 5a and 7b) teaches the method of claim 11, wherein the porous layer (112) is a fully depleted porous layer that is free of carriers ([0050], porous silicon can be devoid of free carriers).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Yuan and Usenko as applied to Claim 11 above, and further in view of Mieno (2012/0168879 A1; hereinafter Mieno).
Regarding Claim 17, Yuan doesn’t explicitly teach the method of claim 11, wherein growing the epitaxial layer comprises growing the epitaxial layer with a crystal orientation that matches a crystal orientation of the wafer.
However, Mieno (fig. 11) teaches growing the epitaxial layer ([0082], 109) comprises growing the epitaxial layer (109) with a crystal orientation that matches a crystal orientation ([0082]) of the wafer ([0082], 100). Mieno also teaches that using an epitaxial layer with the same crystal orientation as part of a channel region can reduce leakage current.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Yuan to include the crystal orientation matching of Mieno to reduce leakage current.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.H./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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