Detailed Action
This office action is in response to the request for continued examination filed on November 3rd, 2025. Claims 1-12 and 15-21 are pending. Claims 1-10 have been withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on October 2nd, 2025, has been entered.
Response to Arguments
Applicant's arguments filed October 2nd, 2025, have been fully considered but they are not persuasive.
Applicant argues (pg. 6-8, “Remarks”) that “dry-in and dry-out porosification process” is clear on its face and that it would be reasonably understood as requiring the wafer to be dry when received and to be dry when removed in a single process environment. Yuan discloses a tool which does not have drying capability. Usenko discloses drying the wafer in a separate process, in a different piece of equipment.
The phrase “dry-in and dry-out porosification process” refers to a method and does not require a single process environment. It does not preclude the removal of the wafer from one process environment, transferring to a separate environment, and then drying as taught by the combination of Yuan and Usenko. When the above process concludes, the porous layer ends dry and thus satisfies the requirement of a “dry-in and dry-out porosification process”.
Therefore, applicant’s arguments are not persuasive.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-12, 15-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yuan (2001/0023111 A1; hereinafter Yuan) in view of Usenko (2018/0047614 A1; hereinafter Usenko).
Regarding Claim 11, Yuan (figs. 5a and 7b) teaches a method comprising:
forming a porous layer ([0044], 112) over a wafer ([0044], 110), the porous layer (112) having a higher resistivity than the wafer ([0046], porous silicon has a resistivity on the order of 10 kΩ*cm while the substrate has a resistivity on the order of .01 Ω*cm), wherein
forming the porous layer (112) comprises a dry-in and dry-out porosification process ([0041]-[0043]), the dry-in and dry-out porosification process comprises:
exposing the wafer (110) to an acid solution ([0041], electrolyte containing HF);
passing an electrolyzing current ([0041], “provides a current source”) through the wafer (110) and the acid solution to form the porous layer (112);
growing an epitaxial layer ([0044], 114) directly over the porous layer (112); and
forming a semiconductor device ([0049], CMOS chip) in the epitaxial layer (114), wherein
a porosity of the porous layer (112) reduces radio frequency (RF) bleeding ([0047], “exhibits high resistivity to signals propagating through the passive components thus limiting coupling losses in the substrate 110”) from the semiconductor device (152, 154, 156) into the wafer (110).
Yuan doesn’t explicitly teach drying the porous layer.
However, Usenko (fig. 3) teaches drying ([0040]) the porous layer ([0024], 44). Usenko also teaches that drying the porous layer oxidizes the pores with native oxide ([0040]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Yuan to include the drying of Usenko to form native oxide in the pores.
Regarding Claim 12, Yuan (figs. 5a and 7b) teaches forming the porous layer (112) comprises forming the porous layer (112) over an entirety (see figs. 5a and 7b) of the wafer (110).
Regarding Claim 15, Yuan (figs. 5a and 7b) teaches the semiconductor device comprises a transistor ([0049], CMOS chip, see fig. 7b). Yuan doesn’t explicitly teach that the transistor is of a radio frequency (RF) switch.
However, Usenko (fig. 3) teaches the semiconductor device comprises a radio frequency (RF) switch ([0011]). Usenko also teaches wanting to use high resistivity wafers for RF related devices in order to reduce loss ([0011]) wherein the high resistivity wafers include porosified silicon ([0024]). One of ordinary skill in the art would have found it obvious to try and form an RF switch over a high resistivity wafer including a porous layer and yielded the predictable results of reduced losses in the system.
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention form an RF switch over a high resistivity wafer including a porous layer since this limitation is one of a finite number of identified, predictable potential solutions. This is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Regarding Claim 16, Yuan doesn’t explicitly teach annealing the porous layer prior to growing the epitaxial layer.
However, Usenko (fig. 3) teaches annealing ([0042]) the porous layer ([0024], 44) prior to growing the epitaxial layer ([0025], 48). Usenko also teaches that annealing the porous layer thermally oxidizes the pores ([0042]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Yuan to include the annealing of Usenko to thermally oxidize the porous layer.
Regarding Claim 18, Yuan doesn’t explicitly teach that the porosity of the porous layer is between about 35% and about 65%.
However, Usenko (fig. 3) teaches the porosity of the porous layer ([0024], 44) is between about 35% and about 65% ([0039]).
Porosity, however, will not support the patentability of the subject matter encompassed by the prior art unless there is evidence indicating such porosity is critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality of the claimed porosity, and similar porosity is used for porous layers in the art, it would have been obvious to one of ordinary skill in the art to select the appropriate porosity of the porous layer.
Regarding Claim 19, Yuan (figs. 5a and 7b) teaches forming the porous layer (112) comprises porosifying an upper portion of the wafer (112, see figs. 5a and 7b).
Regarding Claim 20, Yuan (figs. 5a and 7b) teaches the wafer (110) comprises a silicon wafer ([0041], “silicon wafer”).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Yuan and Usenko as applied to Claim 11 above, and further in view of Mieno (2012/0168879 A1; hereinafter Mieno).
Regarding Claim 17, Yuan doesn’t explicitly teach growing the epitaxial layer comprises growing the epitaxial layer with a crystal orientation that matches a crystal orientation of the wafer.
However, Mieno (fig. 11) teaches growing the epitaxial layer ([0082], 109) comprises growing the epitaxial layer (109) with a crystal orientation that matches a crystal orientation ([0082]) of the wafer ([0082], 100). Mieno also teaches that using an epitaxial layer with the same crystal orientation as part of a channel region can reduce leakage current.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Yuan to include the crystal orientation matching of Mieno to reduce leakage current.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Yuan and Usenko as applied to Claim 11 above, and further in view of Matsumura et al. (2003/0121773 A1; hereinafter Matsumura).
Regarding Claim 17, Yuan doesn’t explicitly teach the dry-in and dry-out porosification process is performed in a single process environment.
However, Matsumura teaches the dry-in and dry-out porosification process ([0103], anodizing, washing, drying) is performed in a single process environment ([0103], all performed in apparatus 100). Matsumura also teaches that the substrate isn’t conveyed between units for individually performing the process steps and increases productivity, helps prevent dropped substrates, and can make the apparatus compact ([0103]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Yuan to include the single process environment of Matsumura to increase productivity and compactify the apparatus.
Conclusion
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/A.H./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 January 27, 2026