DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on December 31st, 2025 has been entered.
Response to Amendment
Applicant's amendment to the claims, filed on December 31st, 2025, is acknowledged. Entry of amendment is accepted and made of record.
Response to Arguments/Remarks
Applicant's response filed on December 31st, 2025 is acknowledged and isanswered as follows.
Applicant's arguments, see pgs. 8-10, with respect to the rejections of claims under 35 U.S.C 112(a), 35 U.S.C 112(b), 35 U.S.C 102(b) and/or 35 U.S.C 103(a) have been considered but are moot in view of the new ground(s) of rejection.
Election/Restrictions
Amended claims 31-33, 35 and 38-40 directed to an invention that is independent or distinct from the invention originally claimed for the following reasons: claim 31 recites “coupling a second die and a third die to the second interposer; applying a molding compound around the second die and the third die to fill gaps” in lines 11-13 being described as second die 104b and third die 104c in nonelected Species N, O and P of Figs. 10, 11 and 12.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 31-33, 35 and 38-40 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
Claim Objections
Claims 22-23 are objected to because of the following informalities:
Claim 22 recites “each semiconductor device dies” in line 3 refers back to each of “a plurality of semiconductor device dies” in line 3 of claim 17 and should be amended to “each of the plurality of semiconductor device dies” for avoiding confusion. Appropriate correction is required.
Claim 23 recites “each semiconductor device dies” in line 2 refers back to each of “a plurality of semiconductor device dies” in line 3 of claim 17 and should be amended to “each of the plurality of semiconductor device dies” for avoiding confusion. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claim 26 and 28-30 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 26 recites the limitations “debonding the interposer from the carrier substrate to form an assembly comprising the interposer and the plurality of dies attached to the interposer” in lines 4-5, “dicing the assembly to form a first chiplet comprising a first interposer and a second chiplet comprising a second interposer” in lines 4-5, and “wherein the first chiplet comprises a serializer/de-serializer to the first interposer” in lines 11-12. According to Applicant’s disclosure, individual first chiplets 506 are formed by dicing the assembly of the interposer 108a, wherein the first chiplet 506 comprising semiconductor die 104a as a serializer/de-serializer die (see Figs. 2-5 and [0049]. Furthermore, Individual second chiplets 906 are formed by dicing the assembly of the interposer 108b that is different from the assembly of the interposer 108a (see Figs. 6-9 and [0061]). There is no evidence suggesting the first chiplet 506 and the second chiplet 906 are formed from dicing the same interposer of the assembly as claimed. Therefore, the above limitations of claim 26 are not supported in the original disclosure and claim 26 recites new matter.
Claims 28-30 are rejected for depending on claim 26 and having the above issues incorporated into the claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 17, 25 and 37 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by KAMGAING et al. (Pub. No.: US 2022/0406721 A1), hereinafter as KAMGAING.
Regarding claim 17, KAMGAING discloses a method of fabricating a semiconductor device in Fig. 4, comprising: forming a plurality of interposers (first substrate 420 and second substrate 422) (see [0039] and [0041]); attaching a plurality of semiconductor device dies (dies 402, 404, 412 and SerDes dies not shown) to respective ones of the plurality of interposers (see [0039] and [0046]); forming a first chiplet (combination of die 412, SerDes dies and second substrate 422) comprising a first interposer (second substrate 422) (see [0039-0041] and [0046]); forming a second chiplet (combination of die 402, die 404 and first substrate 420) comprising a second interposer (first substrate 420) and attaching the first chiplet and the second chiplet (attached by BGAs 432 and 434) separate from each other to a package substrate (interposer 430) such that the first chiplet is proximate to a sidewall of the package substrate (the sidewall of second substrate 422 is proximate to a sidewall of interposer 430), wherein the first chiplet comprises a serializer/de-serializer die (die 412 includes SerDes die not shown in Fig. 4, but similar to die 304 having SerDes 303 in Fig. 3C and same as SerDes 729 in Fig. 7) attached to the first interposer (see [0036], [0046] and [0057]).
Regarding claim 25, KAMGAING discloses the method of claim 17, further comprising forming a plurality of bump structures (BGAs 432 and 434) located between the plurality of interposers and the package substrate (see Fig. 4 and [0042]).
Regarding claim 37, KAMGAING discloses the method of claim 17, further where the first interposer is formed separately from forming the second interposer (second substrate 422 is separately from first substrate 420) (see Fig. 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over KAMGAING et al. (Pub. No.: US 2022/0406721 A1), hereinafter as KAMGAING as applied to claim 17 above, and further in view of Negoro (Pub. No.: US 2013/0043581 A1), hereinafter as Negoro.
Regarding claim 21, KAMGAING discloses the method of claim 17, but fails to disclose wherein attaching the first chiplet and the second chiplet separate to each other to the package substrate further comprises placing the second chiplet at least 2 mm from the first chiplet.
Negoro discloses a method comprising attaching a first chiplet (chip 21) and a second chiplet (chip 22) separately from each other to a package substrate further comprises placing the second chiplet at least 2 mm from the first chiplet (see Fig. 1 and [0030]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify first chiplet and the second chiplet of KAMGAING being apart at least 2 mm as same as the method of Negoro because the modified method would provide adequate spacing for the package to dissipate heat and preventing electrical shortage.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over KAMGAING et al. (Pub. No.: US 2022/0406721 A1), hereinafter as KAMGAING, as applied to claim 17 above.
Regarding claim 22, KAMGAING discloses the method of claim 17, but fails to disclose wherein attaching a plurality of semiconductor device dies to the interposer further comprises placing each semiconductor device die at least 500 microns from an edge of the interposer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have method of KAMGAING comprising attaching a plurality of semiconductor device dies to the interposer further comprises placing each semiconductor device die at least 500 microns from an edge of the interposer because having such spacing would provide enough space for forming the package substrate and improving heat management that basing on manufacturing parameter. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. In re Aller, 105 USPQ 233
Claims 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over KAMGAING et al. (Pub. No.: US 2022/0406721 A1), hereinafter as KAMGAING as applied to claim 17 above, in view of Huang et al. (Pub. No.: US 2018/0350755 A1), hereinafter as Huang.
Regarding claim 23, KAMGAING discloses the method of claim 17, but fails to disclose further comprising forming a plurality of underfill material portions surrounding a portion of each semiconductor device dies.
Huang discloses a method of fabricating a semiconductor device in Figs. 1-2 comprising forming a plurality of underfill material portions (underfills 46) surrounding a portion of each semiconductor device dies (bottom surfaces of dies 44) (see Fig. 1 and [0019-0020]), and forming epoxy molding compound (EMC) (encapsulating material 48) surrounding the plurality of semiconductor dies (see Fig. 2 and [0021-0022]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporating the underfill material and the epoxy molding compound of Huang into the method of KAMGAING for surrounding each of the plurality of semiconductor device dies because the modified structure would provide improve mechanical reliability of the semiconductor dies mounting on the package substrate and further reduce thermal stress between the semiconductor dies and the package substrate.
Regarding claim 24, KAMGAING discloses the method of claim 17, but fails to disclose further comprising forming an epoxy molding compound (EMC) surrounding the plurality of semiconductor device dies.
Huang discloses a method of fabricating a semiconductor device in Figs. 1-2 comprising forming a plurality of underfill material portions (underfills 46) surrounding a portion of each semiconductor device dies (bottom surfaces of dies 44) (see Fig. 1 and [0019-0020]), and forming epoxy molding compound (EMC) (encapsulating material 48) surrounding the plurality of semiconductor dies (see Fig. 2 and [0021-0022]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporating the underfill material and the epoxy molding compound of Huang into the method of KAMGAING for surrounding each of the plurality of semiconductor device dies because the modified structure would provide improve mechanical reliability of the semiconductor dies mounting on the package substrate and further reduce thermal stress between the semiconductor dies and the package substrate.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818