DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
The election of claims 1-4 and 6-10, drawn to group 1 and species a, is acknowledged.
Claims 5 and 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected method and species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 03/04/2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 and 6-10 are rejected under 35 U.S.C. 102(a)(1) as being taught by Choi et al (US-8361863-B2, pub date 01/29/2013, hereinafter “Choi”).
Regarding claim 1, figs. 3H and 3I of Choi teach a transistor structure (fig. 3I), comprising: a substrate (25); a first gate (labeled "1" in annotated fig. 3I below, see also para. [0029], "Polysilicon layer 50 is selectively etched with a photoresist mask to form gate electrodes") and a second gate (gates labeled "2" in annotated fig. 3I below, see also para. [0029], "Polysilicon layer 50 is selectively etched with a photoresist mask to form gate electrodes") located on the substrate (25); a first gate dielectric layer (39) located between the first gate ("1") and the substrate (25) and having a single thickness (39 is a single thickness); and a second gate dielectric layer (the combined feature 33 and 35) located between the second gate ("2") and the substrate (25) and having a plurality of thicknesses (33 has one thickness, and 35 has another thickness), wherein a maximum thickness of the first gate dielectric layer (39) is the same as a maximum thickness of the second gate dielectric layer (33 and 35, the thickness of region 33 is the same as the thickness 39).
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Regarding claim 2, figs. 3H and 3I of Choi teach the second gate dielectric layer (combination of 33 and 35) comprises at least one protruding portion (33 protrudes relative to 35).
Regarding claim 3, figs. 3H and 3I of Choi teach the protruding portion (33 protrudes relative to 35) has a top surface (the top of 33) and a sidewall (the sides of 33 that extend on either side of the top), and the sidewall is connected to the top surface (the top and sides of 33 are connected).
Regarding claim 4, figs. 3H and 3I of Choi teach the sidewall is not perpendicular to the top surface (the sidewalls of 33 are at an angle relative to a 90-degree vertical, therefore the top and sides of 33 are not perpendicular to one another).
Regarding claim 6, figs. 3H and 3I of Choi teach a third gate (gate labeled "3" in the annotated fig. 3I above, see also para. [0029], "Polysilicon layer 50 is selectively etched with a photoresist mask to form gate electrodes") located on the substrate (25); and a third gate dielectric layer (37) located between the third gate ("3") and the substrate (25) and having the single thickness (the thickness of 37 is uniform across the whole layer).
Regarding claim 7, figs. 3H and 3I of Choi teach a maximum thickness (thickness of 33) of the second gate dielectric layer (combination of 33 and 35) is greater than a maximum thickness of the third gate dielectric layer (37) (37 has a smaller thickness than the thickness of 33).
Regarding claim 8, figs. 3H and 3I of Choi teach a minimum thickness (thickness of 35) of the second gate dielectric layer (combination of 33 and 35) is equal to a maximum thickness of the third gate dielectric layer (37) (37 is the same thickness as the thickness of 35).
Regarding claim 9, figs. 3H and 3I of Choi teach the first gate ("1") and the second gate ("2") are separated from each other ("1" and "2" are separated from each other by the valley/recess).
Regarding claim 10, figs. 3H and 3I of Choi teach the first gate dielectric layer (39) and the second gate dielectric layer (combination of 33 and 35) are separated from each other (39 and 33/35 are separated from one another by 37 and multiple valleys/recesses).
Conclusion
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/TESSA ELIZABETH MCNAMEE/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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