Prosecution Insights
Last updated: July 17, 2026
Application No. 17/736,076

SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME

Final Rejection §102§103
Filed
May 03, 2022
Priority
Jul 16, 2021 — provisional 63/222,654
Examiner
GUPTA, RAJ R
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
2 (Final)
68%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
82%
With Interview

Examiner Intelligence

Grants 68% — above average
68%
Career Allowance Rate
422 granted / 619 resolved
At TC average
Moderate +14% lift
Without
With
+13.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 12m
Avg Prosecution
12 currently pending
Career history
635
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
86.5%
+46.5% vs TC avg
§102
6.8%
-33.2% vs TC avg
§112
3.3%
-36.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 619 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-5, 7-10, and 14 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Lin et al. (US 2021/0098376). With regard to claim 1, Lin teaches, in Figs 4-11C, a method, comprising: forming a first conductive feature (282B) over a substrate (210), the first conductive feature comprising a conductive fill material (286); forming an etch stop layer (294) on the conductive fill material; forming an intermetallization dielectric (292) on the etch stop layer; forming an opening (300B at Fig 6) in the etch stop layer and the intermetallization dielectric to expose a portion of the conductive fill material; forming a recess in the exposed portion of the conductive fill material, wherein the opening and the recess together form a rivet-shaped space (300B at Figs 7A-7C); forming a second conductive feature (330) in the rivet-shaped space, wherein the second conductive feature is rivet-shaped (Fig 8C); forming a metal nitride layer (335) over the intermetallization dielectric and the second conductive feature, comprising: depositing the metal nitride layer; and treating the metal nitride layer with a plasma treatment process ([0043]-[0044]); and performing a planarization process to remove the metal nitride layer ([0046]-[0047]). With regard to claim 2, Lin teaches, in Figs 4-11C, forming a metal layer on the intermetallization dielectric and the second conductive feature, wherein the metal nitride layer is formed on the metal layer ([0044]). With regard to claim 3, Lin teaches, in Figs 4-11C, that the metal layer comprises titanium and the metal nitride layer comprises titanium nitride ([0044]). With regard to claim 4, Lin teaches, in Figs 4-11C, that the depositing the metal nitride layer is performed by a plasma enhanced chemical vapor deposition process ([0044]). With regard to claim 5, Lin teaches, in Figs 4-11C, that the plasma enhanced chemical vapor deposition process comprises introducing a titanium-containing precursor and a nitrogen- containing precursor into the processing chamber and forming a first plasma in a processing chamber ([0044]). With regard to claim 7, Lin teaches, in Figs 4-11C, that the planarization process is a chemical mechanical planarization process ([0046]). With regard to claim 8, Lin teaches, in Figs 4-11C, that a portion of the intermetallization dielectric is removed by the planarization process ([0046]-[0047]). With regard to claim 9, Lin teaches, in Figs 4-11C, a method, comprising: forming a first conductive feature (282B) in an active region over a substrate (210), the first conductive feature comprising a conductive fill material (286); forming a resistor layer (282A) in a resistor region over a substrate; forming an etch stop layer (294) on the conductive fill material and the resistor layer; forming an intermetallization dielectric (292) on the etch stop layer; forming a first opening (300B) in the etch stop layer and the intermetallization dielectric to expose a portion of the conductive fill material; forming a second opening (300A) in the etch stop layer and the intermetallization dielectric to expose a portion of the resistor layer; forming a second conductive feature (330) in the first opening, wherein the second conductive feature extends over a top surface of the intermetallization dielectric (see Fig 8A); forming a metal nitride layer (335) over the intermetallization dielectric and the second conductive feature and in the second opening (see Fig 9A), comprising: depositing the metal nitride layer; and treating the metal nitride layer with a plasma treatment process to increase a nitrogen concentration in a top portion of the metal nitride layer ([0043]-[0044]); and performing a planarization process to remove portions of the metal nitride layer disposed over the intermetallization dielectric and a portion of the second conductive feature ([0046]-[0047]). With regard to claim 10, Lin teaches, in Figs 4-11C, forming a mask layer (284) in the second opening before forming the second conductive feature in the first opening. With regard to claim 14, Lin teaches, in Figs 4-11C, forming a metal layer on the intermetallization dielectric and the second conductive feature and in the second opening, wherein the metal nitride layer is formed on the metal layer ([0043]-[0044]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 6 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2021/0098376) in view of Kuratomi et al. (US 2020/0211852). With regard to claim 6, Lin teaches most of the limitations of this claim, as set forth above with regard to claim 5. Lin does not explicitly teach that the plasma treatment process comprises introducing a nitrogen gas and a hydrogen gas into the processing chamber and forming a second plasma in the processing chamber. Kuratomi teaches that the plasma treatment process comprises introducing a nitrogen gas and a hydrogen gas into the processing chamber and forming a second plasma in the processing chamber ([0007]), “to reduce contact resistance and maximize volume of feature fill material,” ([0003]). Therefore, it would have been obvious to the ordinary artisan at the time of filing to combine the method of Lin with the plasma treatment process of Kuratomi to allow for selective deposition and thus reduce contact resistance and maximize volume of feature fill material. With regard to claim 15, Lin teaches most of the limitations of this claim, as set forth above with regard to claim 9. Lin does not explicitly teach that the plasma treatment process comprises introducing a nitrogen-containing gas and a hydrogen-containing gas into a processing chamber and forming a plasma in the processing chamber. Kuratomi teaches that the plasma treatment process comprises introducing a nitrogen-containing gas and a hydrogen-containing gas into a processing chamber and forming a plasma in the processing chamber ([0007]), “to reduce contact resistance and maximize volume of feature fill material,” ([0003]). Therefore, it would have been obvious to the ordinary artisan at the time of filing to combine the method of Lin with the plasma treatment process of Kuratomi to allow for selective deposition and thus reduce contact resistance and maximize volume of feature fill material. Claim(s) 21 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2021/0098376) in view of Chen et al. (US 2020/0051858). With regard to claim 21, Lin teaches, in Figs 4-11C, a method, comprising: depositing a dielectric layer (292) in an active region and a resistor region; forming a first opening (300B) in the dielectric layer to expose a conductive fill material (282B) in the active region; forming a second opening (300A) in the dielectric layer to expose a resistor layer (282A) in the resistor region; forming a conductive feature (330) in the first opening in the active region, wherein the conductive feature extends over a top surface of the dielectric layer; depositing a metal layer (335) over the dielectric layer and the conductive feature in the active region and in the second opening in the resistor region; and performing a planarization process to remove of the metal layer disposed in the active region and to remove a portion of the metal layer disposed in the resistor region ([0046]-[0047]). Lin does not explicitly teach that the resistor layer and the conductive fill material comprise different materials. Chen teaches, in Fig 6, that the resistor layer (76) and the conductive fill material (56) comprise different materials ([0020], [0030]) so that, “better interface management and electrical properties may be obtained,” ([0056]). Therefore, it would have been obvious to the ordinary artisan at the effective time of filing to combine the method of Lin with the conductive features of Chen so that better interface management and electrical properties may be obtained. With regard to claim 22, Lin teaches, in Figs 4-11C, depositing an etch stop layer (294) in the active region and the resistor region, wherein the dielectric layer is deposited on the etch stop layer. Allowable Subject Matter Claims 11-13 and 23-25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: the prior art of record fails to anticipate or render obvious claimed limitations of wherein forming the second conductive feature comprises: forming a first portion in a recess in the conductive fill material; forming a second portion on the first portion, wherein first gaps are formed between the second portion and the etch stop layer; forming a sealing portion around a top portion of the second portion; and forming a third portion on the second portion, wherein second gaps are formed between the third portion and the intermetallization dielectric, as set forth in claim 11, or of wherein forming the conductive feature comprises: depositing a first portion of the conductive feature in the first opening, wherein a first gap is formed between the first portion of the conductive feature and the etch stop layer; forming a sealing portion on the first portion of the conductive feature; and depositing a second portion of the conductive feature to fill the first opening, wherein a second gap is formed between the second portion of the conductive feature and the dielectric layer, as set forth in claim 23, each when taken in concert with all the other limitations of the respective claims, base claims, and any intervening claims. All other objected claims depend from either of these claims. Response to Arguments Applicant's arguments filed 11/12/2025 have been fully considered but they are not persuasive. The Applicants argue: the Examiner has not demonstrated how Lin discloses a method comprising treating the metal nitride layer with a plasma treatment process, as recited in claims 1 and 9, and in claims dependent thereon The Examiner responds: The process of applying a Nitrogen plasma treatment to the titanium layer to form a titanium nitride layer will necessarily meet the claimed limitation of “treating the metal nitride layer with a plasma treatment process” set forth in claim 1 as during the treatment of the titanium layer, it becomes at least somewhat nitrogenated, allowing it to meet the broadest reasonable interpretation of “the metal nitride layer”. The plasma treatment then continues until desired nitrogenation is achieved. This continuing treatment meets the claimed limitation. All other arguments have been fully addressed in prior Office Actions or in the rejections set forth above. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAJ R GUPTA whose telephone number is (571)270-5707. The examiner can normally be reached 9:30AM-4PM, 8PM-10PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 5712721236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RAJ R GUPTA/Primary Examiner, Art Unit 2893
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Prosecution Timeline

May 03, 2022
Application Filed
Aug 12, 2025
Non-Final Rejection mailed — §102, §103
Oct 20, 2025
Interview Requested
Nov 12, 2025
Response Filed
Jul 01, 2026
Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
68%
Grant Probability
82%
With Interview (+13.6%)
2y 12m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 619 resolved cases by this examiner. Grant probability derived from career allowance rate.

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