DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the
first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C.
102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the
statutory basis for the rejection will not be considered a new ground of rejection if the prior art
relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of Claims
Claims 1-18 are pending
Claims 12 and 14-15 have been withdrawn
Claims 1 and 11 have been amended
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-11, 13, 16-18 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding Claim 1:
Claim 1 recites the limitation “a command to a wafer moving device to move a wafer directly between the first load lock chamber and the second load lock chamber when predetermined wafer transfer conditions are satisfied.” There insufficient support in the written specification for this limitation. It is noted that on the remarks filed 08/19/2024, the applicant elected species B1, directed to the embodiment of Fig. 11; Fig. 11 displays two load lock chambers connected by an inter-load lock chamber [IA - 0088]. As such, it is unclear how a wafer can be directly transferred between the two load lock chambers when there is an intermediary chamber between them. Furthermore, utilizing the WHC 40 to transfer substrates between the load lock chambers would result in the wafers not being directly transferred between the load lock chambers, but rather be transferred to the WHC 40 first.
Regarding Claims 2-11, 13, and 16-18:
Claims 2-13 and 16-18 are rejected at least based on their dependency on claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-5, 9-11, 13, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nozawa (US 10290523) in view of Pool (US 20030113188), Fuse et al. (US 5217501), and Lin et al. (US 20170018443).
Regarding Claim 1:
Nozawa teaches a substrate treatment apparatus comprising :a plurality of load ports (load ports 12); a front-end module (EFEM 10) adjacent to the plurality of load ports; a first load lock chamber (load lock 30) adjacent to the front-end module, the first load lock chamber having a plurality of wafer housing slots (LLC 30 comprises first and second load lock stages 32 and 34, respectively); a second load lock chamber (LLC 30 comprises first and second load lock stages 32 and 34, respectively; the load lock apparatus 31 has the same configuration as that of the load lock apparatus 30) adjacent to the front-end module, the second load lock chamber having a plurality of wafer housing slots (the load lock chambers 106A and 106B comprise of multiple wafer stations 536A-536G); a wafer handling chamber (WHC 40) adjacent to the first load lock chamber and the second load lock chamber; a first wafer transfer device (first robot 14) in the front-end module; a second wafer transfer device (second robots 42 and 44) in the wafer handling chamber; and a controller (controller 70) including a processor and a memory configured to cause the processor to execute a program stored in the memory, or including a dedicated circuitry to move the wafer from the first load lock chamber or the second load lock chamber to a reaction chamber using the second wafer transfer device (the second robots 42 and 44 simultaneously convey two wafers between the first LLS and the second LLS, and the first processing stage and the second processing stage) [Fig. 1, 5, 7 & Col. 3 lines, 34-46, Col. 5 lines 22-37,Col. 8 lines 41-53, Col. 9 lines 53-57].
Nozawa does not specifically disclose an inter-load lock chamber between the first load lock chamber and the second load lock chamber; an inter-load lock wafer transfer device provided in the inter-load lock chamber, in the first load lock chamber or in the second load lock chamber.
Pool teaches an inter-load lock chamber (main load lock chamber 202) configured to communicate with the first load lock chamber (first load lock antechamber 204) and the second load lock (second load lock antechamber 206) chamber via a gate valve (slit valves 208 and 209); an inter-load lock wafer transfer device (robot 260) provided in the inter-load lock chamber, in the first load lock chamber or in the second load lock chamber [Fig. 2 & 0021, 0025].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the apparatus of Nozawa to include a inter load lock chamber, as in Pool, to improve throughput [Pool - 0028].
Modified Nozawa does not specifically disclose wherein the first load lock chamber and the second load lock chamber are independent chambers.
Fuse teaches wherein the first load lock chamber and the second load lock chamber are independent chambers (load lock chamber 44 is divided into two independent chambers 44a and 44b) [Fig. 5 & Col. 7 lines 45-50].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the load locks of Modified Nozawa to be independent chambers with gate valves, as in Fuse, to reduce conveying time and to reduce cross-wafer contamination [Fuse - Col. 7 lines 45-50, lines 65-68, Col. 8 lines 1-3], and wherein the substrate treatment apparatus is configured, so that gas movement between the first load lock chamber and the second load lock chamber is prevented when the first load lock chamber and the second load lock chamber are isolated from each other (load lock chambers 44a and 44b are independent so they are capable of preventing gas flow to each other) [Fig. 5 & Col. 7 lines 45-50].
Modified Nozawa (Nozawa modified by Pool and Fuse) does not specifically disclose a command to a wafer moving device to selectively move a wafer directly between the first load lock chamber, the wafer handling chamber, and the second load lock chamber or directly between the first load lock chamber and the second load lock chamber when predetermined wafer transfer conditions are satisfied
Lin teaches a command to a wafer moving device (first transfer robot 110) to selectively move a wafer directly between the first load lock (transfer load lock 104) chamber, the wafer handling chamber (first transfer chamber 110), and the second load lock chamber (storage chamber 106) when predetermined wafer transfer conditions are satisfied (the outer load lock portal 103 is closed and the transfer load lock 104 is pumped to be closed to an internal environment of the processing tool. Then, the first lot 120a of wafers is transferred from the transfer load lock 104 to the designated storage chamber 106 by a first transfer robot 111 of the first transfer chamber 110) [Fig. 3 & 0054].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the apparatus of Modified Nozawa to include instructions for transferring substrates between load lock chambers, as in Lin, to reduce queue time and for more flexible ordering of wafers [Lin - 0012, 0073].
Furthermore, although taught by the cited prior art, the limitations “wherein the substrate treatment apparatus is configured, so that gas movement between the first load lock chamber and the second load lock chamber is prevented when the first load lock chamber and the second load lock chamber are isolated from each other,” are merely intended use and are given weight to the extent that the prior art is capable of performing the intended use. A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987).
Regarding Claim 2:
Nozawa teaches wherein the wafer transfer conditions include that there is a wafer of which treatment is not completed in the first load lock chamber and the second load lock chamber, and there is a wafer to be transferred to the first load lock chamber or the second load lock chamber in any one load port of the plurality of load ports (in step 4, the first robot 14 conveys the wafer located at the aligner 16 to the first LLS 32 or the second LLS 34; placement of the wafers on LLS 32 or LLS 34 occurs prior to wafer treatment, so there would be a wafer where treatment is not completed present in LLC 30); and the controller is further configured to carry out the command such that the wafer moving device operates so as to attain a state in which there is no wafer in any one of the first load lock chamber and the second load lock chamber (after a wafer is transferred away from LLC 30 to be treated, there would be no wafer present in either LLC until treatment is finished and the treated wafers are transferred to LLC 31) [Fig. 1, 5, 7 & Col. 8 lines 4-14].
Regarding Claim 4:
Nozawa teaches wherein when the program is executed by the processor, or when the processing of the dedicated circuitry is executed, the controller issues the command to the first wafer transfer device to move the wafer from one of the plurality of load ports to a load lock chamber containing no wafer, the load lock chamber containing no wafer being one of the first load lock chamber and the second load lock chamber (first robot 14 moves wafers from load ports 12 to aligners 16 or 18, after which, the wafers are taken to LLC 30; no wafer must be present in a respective load lock stage if a wafer is being transferred in to that load lock stage) [Fig. 1 & Col. 8 lines 4-32].
Regarding Claim 5:
Nozawa teaches wherein the controller is further configured to carry out the command such that the wafer moving device operates so as to move wafers housed in the first load lock chamber or wafers housed in the second load lock chamber, the moved wafers having a smaller number than the other wafers (in process step 5, prior to wafer treatment, the wafers are picked up from LLC 30; second robot 42 is capable of moving a singular wafer out of LLC 30 as opposed to two) [Fig. 1 & Col. 5 lines 31-37].
Regarding Claim 9:
Nozawa teaches wherein the wafer transfer conditions include that a process job which designates a transfer path of the wafer permits use of the first load lock chamber and the second load lock chamber (both LLC 30 and LLC 31 are used in the overall processing of wafers in the wafer processing apparatus) [Fig. 1, 5, 7 & Col. 3 lines, 34-46, Col. 5 lines 22-37,Col. 8 lines 41-53, Col. 9 lines 53-57].
Regarding Claim 10:
Nozawa teaches wherein the wafer moving device is the second wafer transfer device (second robots 42 and 44 transfer wafers from LLC 30 to the chambers modules 52, which are then transferred to LLC 31 after processing) [Fig. 1, 5, 7 & Col. 9 lines 52-58].
Regarding Claim 11:
Nozawa does not specifically disclose wherein the inter-load lock wafer transfer device is provided in the first load lock chamber or in the second load lock chamber.
Pool teaches wherein the inter-load lock wafer transfer device (robot 260) provided in the first load lock chamber or in the second load lock chamber. [Fig. 2 & 0021, 0025].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the apparatus of Nozawa to include a inter load lock chamber, as in Pool, to improve throughput [Pool - 0028].
Regarding Claim 13:
Nozawa teaches a plurality of reactor chambers in contact with the wafer handling chamber (there are a plurality of chambers modules 52) [Fig. 1 & Col. 4 lines 29-32].
Regarding Claim 18:
Nozawa does not specifically disclose a first gate valve provided between the first load lock chamber and the front-end module; a second gate valve provided between the second load lock chamber and the front-end module; a third gate valve provided between the first load lock chamber and the wafer handling chamber; and a fourth gate valve provided between the second load lock chamber and the wafer handling chamber.
Fuse teaches a first gate valve (gate valve 55) provided between the first load lock chamber and the front-end module; a second gate valve (gate valve 56) provided between the second load lock chamber and the front-end module; a third gate valve (gate valve 53) provided between the first load lock chamber and the wafer handling chamber; and a fourth gate valve (gate valve 54) provided between the second load lock chamber and the wafer handling chamber (load lock chambers 44a and 44b have individual gate valves for each interface with other chambers) [Fig. 5 & Col. 5 lines 19-36, Col. 6 lines 54-60].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the load locks of Modified Nozawa to be independent chambers with gate valves, as in Fuse, to reduce conveying time and to reduce cross-wafer contamination[Fuse - Col. 7 lines 45-50, lines 65-68, Col. 8 lines 1-3].
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nozawa (US 10290523) in view of Pool (US 20030113188), Fuse et al. (US 5217501), and Lin et al. (US 20170018443), as applied to claims 1-2, 4-5, 9-11, 13, and 18 above, and further in view of Mitchell et al. (US 20040234359).
The limitations of claims 1-2, 4-5, 9-11, 13, and 18 have been set forth above.
Regarding Claim 3:
Modified Nozawa does not specifically disclose wherein the plurality of load ports include a first load port, a second load port and a third load port; the wafer transfer conditions include that there is a wafer which has been transferred from the first load port and of which treatment is not completed, in the first load lock chamber, there is a wafer which has been transferred from the second load port and of which the treatment is not completed, in the second load lock chamber, and there is a wafer to be transferred to the first load lock chamber or the second load lock chamber, in the third load port; and the command causes the wafer moving device to operate so as to attain a state in which there is no wafer in any one of the first load lock chamber and the second load lock chamber.
Mitchell teaches wherein the plurality of load ports include a first load port, a second load port and a third load port (there are three load lock chambers L1, L2, and L3 in treatment station 134) [Fig. 5 & 0037]; the wafer transfer conditions include that there is a wafer which has been transferred from the first load port and of which treatment is not completed, in the first load lock chamber, there is a wafer which has been transferred from the second load port and of which the treatment is not completed, in the second load lock chamber, and there is a wafer to be transferred to the first load lock chamber or the second load lock chamber, in the third load port (as evidenced by Fig. 6, prior to wafer treatment, wafers are placed inside load locks L1, L2, and L3; during evacuation or venting of load lock L3, a wafer may be placed in load lock 2) [Fig. 5, 6 & 0030-0032]; and the controller is further configured to carry out the command such that the wafer moving device operates so as to attain a state in which there is no wafer in any one of the first load lock chamber and the second load lock chamber (after wafers are moved from the load locks into chamber 136 for treatment, there would be no wafer left in the load locks until new ones are transferred in) [Fig. 5, 6 & 0030-0032].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the apparatus of Modified Nozawa to include more load lock chambers, as in Mitchell, to improve throughput [Mitchell - 0037].
Claim(s) 6-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nozawa (US 10290523) in view of Pool (US 20030113188), Fuse et al. (US 5217501), and Lin et al. (US 20170018443), as applied to claims 1-2, 4-5, 9-11, 13, and 18 above, and further in view of Nogami (US 4759681).
The limitations of claims 1-2, 4-5, 9-11, 13, and 18 have been set forth above.
Regarding Claim 6:
Modified Nozawa teaches and the controller is further configured to carry out the command such that the wafer moving device operates so as to attain a state in which only the first wafer exists in any one of the first load lock chamber and the second load lock chamber (two wafers need not be carried into LLC 30; a singular wafer can be carried into LLC 30, therefore the apparatus is capable having only one type of wafer in either LLC) [Nozawa - Fig. 1, 5, 7 & Col. 8 lines 4-14].
Modified Nozawa does not specifically disclose wherein the wafer transfer conditions include that a first wafer of which treatment has been completed and a second wafer of which the treatment is not completed are mixed in the first load lock chamber or the second load lock chamber.
Nogami teaches wherein the wafer transfer conditions include that a first wafer of which treatment has been completed and a second wafer of which the treatment is not completed are mixed in the first load lock chamber or the second load lock chamber (both processed and unprocessed wafers are present in the transport chamber 42; the operator removes the cassette 22A having the processed wafers 2 contained therein, and another cassette 22A containing unprocessed wafers 2 is set in position, whereupon the wafers 2 are automatically transferred to the stocker 26A as stated above and made available for delivery. Concurrently with this, wafers 2 are supplied from the stocker 26B, followed by ion implantation and collection of wafer 2 in the cassette 22B) [Fig. 4 & Col. 4 lines 14-23].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the apparatus of Modified Nozawa to include mix unprocessed and processed wafers in the same chamber, as in Nogami, to improve efficiency [Nogami - Col. 7 lines 19-17].
Regarding Claim 7:
Modified Nozawa teaches the controller is further configured to carry out the command such that the wafer moving device operates so as to attain a state in which only the first wafers exist in any one of the first load lock chamber and the second load lock chamber (two wafers need not be carried into LLC 30; a singular wafer can be carried into LLC 30, therefore the apparatus is capable having only one type of wafer in either LLC) [Nozawa - Fig. 1, 5, 7 & Col. 8 lines 4-14].
Nozawa does not specifically disclose the wafer transfer conditions include that first wafers which have been transferred from the first load port and of which treatment has been completed, and second wafers which have been transferred from the second load port and of which the treatment is not completed are mixed in the first load lock chamber or the second load lock chamber.
Nogami teaches the wafer transfer conditions include that first wafers which have been transferred from the first load port and of which treatment has been completed, and second wafers which have been transferred from the second load port and of which the treatment is not completed are mixed in the first load lock chamber or the second load lock chamber (both processed and unprocessed wafers are present in the transport chamber 42; the operator removes the cassette 22A having the processed wafers 2 contained therein, and another cassette 22A containing unprocessed wafers 2 is set in position, whereupon the wafers 2 are automatically transferred to the stocker 26A as stated above and made available for delivery. Concurrently with this, wafers 2 are supplied from the stocker 26B, followed by ion implantation and collection of wafer 2 in the cassette 22B) [Fig. 4 & Col. 4 lines 14-23].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the apparatus of Modified Nozawa to include mix unprocessed and processed wafers in the same chamber, as in Nogami, to improve efficiency [Nogami - Col. 7 lines 19-17].
Regarding Claim 8:
Modified Nozawa teaches wherein the controller is further configured to carry out the command such that the wafer moving device operates so as to move the first wafers or the second wafers, the moved wafers having a smaller number than the other wafers (in process step 5, prior to wafer treatment, the wafers are picked up from LLC 30; second robot 42 is capable of moving a singular wafer out of LLC 30 as opposed to two) [Nozawa - Fig. 1 & Col. 5 lines 31-37].
Claim(s) 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nozawa (US 10290523) in view of Pool (US 20030113188), Fuse et al. (US 5217501), and Lin et al. (US 20170018443), as applied to claims 1-2, 4-5, 9-11, 13, and 18 above, and further in view of Maydan et al. (US 5855681).
The limitations of claims 1-2, 4-5, 9-11, 13, and 18 have been set forth above.
Regarding Claim 16:
Modified Nozawa does not specifically disclose wherein the first load lock chamber comprises: a shaft; and a plurality of vertically-oriented wafer housing slots supported by the shaft.
Maydan teaches wherein the first load lock chamber comprises: a shaft (shaft 224) and a plurality of vertically-oriented wafer housing slots supported by the shaft (the load lock chamber 112 comprises a load lock cassette 218 comprising vertically stacked wafer seats) [Fig. 9 & Col. 5 lines 58-67, Col. 6 lines 1-4].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the apparatus of Modified Nozawa to include moveable interlock chambers with a plurality of wafer housing slots, as in Maydan, to improve throughput [Maydan - Abstract, Fig. 9 & Col. 5 lines 58-67, Col. 6 lines 1-4, lines 14-19].
Regarding Claim 17:
Modified Nozawa does not specifically disclose a driving motor configured to move the shaft up and down.
Maydan teaches a driving motor configured to move the shaft up and down (a motor, such as a stepper motor or other elevator system, is disposed below the bottom 204 of the load lock chamber 112 and moves the shaft 224 upwardly and downwardly within the load lock chamber 112 to locate a pair of wafers in alignment with a wafer handler for loading or unloading wafers from the load lock chamber 112) [Fig. 10 & Col. 6 lines 14-19].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the apparatus of Modified Nozawa to include moveable interlock chambers with a plurality of wafer housing slots, as in Maydan, to improve throughput [Maydan - Abstract, Fig. 9 & Col. 5 lines 58-67, Col. 6 lines 1-4, lines 14-19].
Response to Arguments
Applicant' s arguments, see Remarks, filed 02/03/2026, with respect to the objection of claim 12 has been fully considered and are persuasive. The objection of claim 12 has been fully withdrawn.
Applicant' s arguments, see Remarks, filed 02/03/2026, with respect to the rejection of claims 1-11 and 16-18 under 35 USC 103 have been fully considered but are not persuasive.
Applicant argues that the combination of references does not specifically disclose “a controller including a processor and a memory configured to cause the processor to execute a program stored in the memory, or including a dedicated circuitry, to issue a command to a wafer moving device to selectively move a wafer directly between the first load lock chamber, the wafer handling chamber, and the second load lock chamber or directly between the first load lock chamber and the second load lock chamber when predetermined wafer transfer conditions are satisfied,” because Lin et al. (US 20170018443) cannot be used to modify Nozawa (US 10290523) as modified by Pool (US 20030113188) because the teachings of Lin would necessarily change Modified Nozawa’s basic, intended principle of operation and structure.
In response to applicant's argument that Lin cannot be used to modify Nozawa as modified by Pool because the teachings of Lin would necessarily change Modified Nozawa’s basic, intended principle of operation and structure, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
It is noted that Pool is only being used to modify Nozawa to include an inter-load lock chamber (main chamber 202) with two other load-lock chambers, as the arrangement of the inter-load lock chamber along with the two load-lock chambers helps improve throughput by providing a buffer/storage while other wafers are processed [Pool - 0028]. Lin is being used to modify Modified Nozawa to include instructions for transferring substrates between load lock chambers (by utilizing a wafer handling chamber) to reduce queue time and for more flexible ordering of wafers [Lin - 0012, 0073]. The examiner fails to see how including instructions for transferring wafers between load lock chambers would necessarily and fundamentally change the operations and structure of Modified Nozawa, as transfer between load lock chambers either using a inter-load lock chamber or by utilizing a wafer handling chamber would be capable of coexistence/being performed simultaneously. Furthermore, the examiner considers one of ordinary skill in the art as one of high skill and creativity, and as such, would be capable of combining the teachings of all the listed references without destroying the functionality and structure of the modified apparatus.
Furthermore, the applicant’s amendments has necessitated a new rejection under 35 USC 112a. Specifically, claim 1 recites “a controller including a processor and a memory configured to cause the processor to execute a program stored in the memory, or including a dedicated circuitry, to issue a command to a wafer moving device to selectively move a wafer directly between the first load lock chamber, the wafer handling chamber, and the second load lock chamber or directly between the first load lock chamber and the second load lock chamber when predetermined wafer transfer conditions are satisfied.” There is insufficient support in the written specification for this limitation. It is noted that in the remarks filed 08/19/2024, the applicant has elected Species B1, directed to the embodiment of Fig. 11; Fig. 11 displays two load lock chambers connected by an inter-load lock chamber [IA - 0088]. As such, it is unclear how a wafer can be directly transferred between two load lock chambers when there is an intermediary chamber between them. Furthermore, utilizing the WHC 40 to transfer substrates between the load lock chambers would result in the wafers not being directly transferred between the load lock chambers, but rather be transferred to the WHC 40 first.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSHUA NATHANIEL PINEDA REYES whose telephone number is (571)272-4693. The examiner can normally be reached Monday - Friday 8 AM to 4:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Gordon Baldwin can be reached at (571) 272-5166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.R./Examiner, Art Unit 1718 /GORDON BALDWIN/Supervisory Patent Examiner, Art Unit 1718
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