DETAILED ACTION
This action is responsive to the following communication: the response filed 9/23/2025. The changes and remarks disclosed therein have been considered.
Claim(s) status: 1-20 pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 7-8, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung (US 2015/0117129) in view of Khakifirooz et al. (US 2019/0103159 ‒hereinafter Khakifirooz).
Regarding claim 1, Jung discloses a semiconductor apparatus comprising:
one or more substrates (“a semiconductor substrate on which the memory cell array 110 disposed” para 0072); and
logic (140; fig. 2) coupled to the one or more substrates (i.e. via the memory device 100; fig. 2), wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware (fig. 5), the logic to:
while programming a memory page (“program operation is performed on each page” para 0035) with a sequence of programming passes (“sequentially generates a plurality of program voltages … in an incremental step pulse programming (ISPP) method” para 0041, i.e. each step pulse(s) is considered a programming pass in the ISPP sequence), detect (S34; fig. 3) a program interruption (Yes, “interrupt instruction is determined to be inputted”; fig. 3 para 0055) to the sequence of programming passes (i.e. of the ISPP sequence);
after the program interruption (i.e. after Yes at S34; fig. 3), perform (S36; fig. 3) a threshold voltage state verify sense (“performs a verify operation by sensing the potential of the corresponding bit line” para 0036, i.e. to determine a threshold voltage of a program operation; para 0049) on the memory page (para 0035) based on a sense level (i.e. sense level of the sensing potential of the corresponding bit line coupled to the memory page);
determine (i.e. during an update of status data; fig. 3, para 0048-0049) a memory page status (“status data indicating information on a processing status of an operation” para 0024) of the memory page (para 0035) based on the threshold voltage state verify sense (“The status data may include all of the related data of the program operation ... For example, the status data may include a potential level of the program voltage, and a threshold voltage corresponding to the ongoing program operation [i.e. as performed by the threshold voltage state verify sense]” para 0049), wherein the memory page status indicates is one of erased, programed with first pass data (“an extent of progress of the program operation” para 0057, i.e. less than, equal, or greater than 80%), and programed with second pass data (“an extent of progress of the program operation” para 0057, i.e. an other of less than, equal, or greater than 80%) based on the threshold voltage state verify sense (“The status data may include all of the related data of the program operation” para 0049, further a register stores “a threshold voltage of the memory cells by the program operation, and a detailed operation step of the erase operation as the status data in addition to the resultant count number counted by the pulse counter” claim 3); and
perform a program continuation (S39; fig. 3) to continue the sequence of programming passes after the program interruption (S38; fig. 3) based on the memory page status (i.e. based on the status data as outputted to a controller; para 0055-0057; fig. 3).
Jung does not expressly disclose indicates a number of programming passes that have been completed on the memory page among the sequence of programming passes at a time of the program interruption.
Khakifirooz discloses indicates a number (a pulse number; fig. 4 para 0035) of programming passes (i.e. of programming loops; fig. 4) that have been completed (“where the pulse number indicates at which pulse the programming was interrupted” para 0044, in which pulse(s) prior to the interrupt are considered completed) on the memory page (para 0028) among the sequence of programming passes (fig. 4) at a time of the program interruption (a time in which the pulse number is applied).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Jung is modifiable as taught by Khakifirooz for the purpose of preventing disturbances and error by reducing unnecessary programming after data access is interrupted (para 0035 of Khakifirooz), which may decrease latencies and avoid points of failure that could otherwise hinder a complex system.
Regarding claim 7, Jung discloses the semiconductor apparatus, wherein the program interruption is one of a loss of power, a shut down, and a restart (i.e. restarting the program operation S39 after the program interruption S38; fig. 3).
Regarding claim 8, Jung discloses a computing system comprising: a memory array (110; fig. 2) including a plurality of cell blocks (BLK1-BLKz; fig. 2); and
a memory controller (140; fig. 2) coupled to the memory array (110), the memory controller configured to:
while programming a memory page (“program operation is performed on each page” para 0035) with a sequence of programming passes (“sequentially generates a plurality of program voltages … in an incremental step pulse programming (ISPP) method” para 0041, i.e. each step pulse(s) is considered a programming pass in the ISPP sequence), detect (S34; fig. 3) a program interruption (Yes, “interrupt instruction is determined to be inputted”; fig. 3 para 0055) to the sequence of programming passes (i.e. of the ISPP sequence);
after the program interruption (i.e. after Yes at S34; fig. 3), perform a threshold voltage state verify sense (“performs a verify operation by sensing the potential of the corresponding bit line” para 0036, i.e. to determine a threshold voltage of a program operation; para 0049) on the memory page (para 0035) based on a sense level (i.e. sense level of the sensing potential of the corresponding bit line coupled to the memory page);
determine (i.e. during an update of status data; fig. 3, para 0048-0049) a memory page status (“status data indicating information on a processing status of an operation” para 0024) of the memory page (para 0035) based on the threshold voltage state verify sense (“The status data may include all of the related data of the program operation ... For example, the status data may include a potential level of the program voltage, and a threshold voltage corresponding to the ongoing program operation [i.e. as performed by the threshold voltage state verify sense]” para 0049), wherein the memory page status indicates is one of erased, programed with first pass data (“an extent of progress of the program operation” para 0057, i.e. less than, equal, or greater than 80%), and programed with second pass data (“an extent of progress of the program operation” para 0057, i.e. an other of less than, equal, or greater than 80%) based on the threshold voltage state verify sense (“The status data may include all of the related data of the program operation” para 0049, further a register stores “a threshold voltage of the memory cells by the program operation, and a detailed operation step of the erase operation as the status data in addition to the resultant count number counted by the pulse counter” claim 3); and
perform a program continuation (S39; fig. 3) to continue the sequence of programming passes after the program interruption (S38; fig. 3) based on the memory page status (i.e. based on the status data as outputted to a controller; para 0055-0057; fig. 3).
Jung does not expressly disclose indicates a number of programming passes that have been completed on the memory page among the sequence of programming passes at a time of the program interruption.
Khakifirooz discloses indicates a number (a pulse number; fig. 4 para 0035) of programming passes (i.e. of programming loops; fig. 4) that have been completed (“where the pulse number indicates at which pulse the programming was interrupted” para 0044, in which pulse(s) prior to the interrupt are considered completed) on the memory page (para 0028) among the sequence of programming passes (fig. 4) at a time of the program interruption (a time in which the pulse number is applied).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Jung is modifiable as taught by Khakifirooz for the purpose of preventing disturbances and error by reducing unnecessary programming after data access is interrupted (para 0035 of Khakifirooz), which may decrease latencies and avoid points of failure that could otherwise hinder a complex system.
Regarding claim 14, Jung discloses a method comprising:
while programming a memory page (“program operation is performed on each page” para 0035) with a sequence of programming passes (“sequentially generates a plurality of program voltages … in an incremental step pulse programming (ISPP) method” para 0041, i.e. each step pulse(s) is considered a programming pass in the ISPP sequence), detecting (S34; fig. 3) a program interruption (Yes, “interrupt instruction is determined to be inputted”; fig. 3 para 0055) to the sequence of programming passes (i.e. of the ISPP sequence);
after the program interruption (i.e. after Yes at S34; fig. 3), performing a threshold voltage state verify sense (“performs a verify operation by sensing the potential of the corresponding bit line” para 0036, i.e. to determine a threshold voltage of a program operation; para 0049) on the memory page (para 0035) based on a sense level (i.e. sense level of the sensing potential of the corresponding bit line coupled to the memory page);
determining (i.e. during an update of status data; fig. 3, para 0048-0049) a memory page status (“status data indicating information on a processing status of an operation” para 0024) of the memory page (para 0035) based on the threshold voltage state verify sense (“The status data may include all of the related data of the program operation ... For example, the status data may include a potential level of the program voltage, and a threshold voltage corresponding to the ongoing program operation [i.e. as performed by the threshold voltage state verify sense]” para 0049), wherein the memory page status indicates is one of erased, programed with first pass data (“an extent of progress of the program operation” para 0057, i.e. less than, equal, or greater than 80%), and programed with second pass data (“an extent of progress of the program operation” para 0057, i.e. an other of less than, equal, or greater than 80%) based on the threshold voltage state verify sense (“The status data may include all of the related data of the program operation” para 0049, further a register stores “a threshold voltage of the memory cells by the program operation, and a detailed operation step of the erase operation as the status data in addition to the resultant count number counted by the pulse counter” claim 3); and
performing a program continuation (S39; fig. 3) to continue the sequence of programming passes after the program interruption (S38; fig. 3) based on the memory page status (i.e. based on the status data as outputted to a controller; para 0055-0057; fig. 3).
Jung does not expressly disclose indicates a number of programming passes that have been completed on the memory page among the sequence of programming passes at a time of the program interruption.
Khakifirooz discloses indicates a number (a pulse number; fig. 4 para 0035) of programming passes (i.e. of programming loops; fig. 4) that have been completed (“where the pulse number indicates at which pulse the programming was interrupted” para 0044, in which pulse(s) prior to the interrupt are considered completed) on the memory page (para 0028) among the sequence of programming passes (fig. 4) at a time of the program interruption (a time in which the pulse number is applied).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Jung is modifiable as taught by Khakifirooz for the purpose of preventing disturbances and error by reducing unnecessary programming after data access is interrupted (para 0035 of Khakifirooz), which may decrease latencies and avoid points of failure that could otherwise hinder a complex system.
Claim(s) 2-3, 9-10, 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung (US 2015/0117129) in view of Khakifirooz et al. (US 2019/0103159 ‒hereinafter Khakifirooz), and further in view of Gan et al. (US 2009/0083021 ‒hereinafter Gan).
Regarding claim 2, Jung discloses the semiconductor apparatus, wherein the memory page status is determined as one of erased, programed with first pass data, and programed with second pass data based on the threshold voltage state verify sense using a command (para 0038).
Jung, as modified, does not expressly disclose using a single NAND command.
Gan discloses using a single NAND command (para 0031).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Jung is further modifiable as taught by Gan for the purpose of improving data accessing schemes by facilitating communication of a NAND device (Abstract, para 0003 of Gan), which is common and well known in the art for reducing signal propagation delays.
Regarding claim 3, Jung, as modified, does not expressly disclose the semiconductor apparatus, wherein the single NAND command is performed with a preexisting read operation.
Gan discloses single NAND command is performed with a preexisting read operation (para 0018).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Jung is further modifiable as taught by Gan for the purpose of improving data accessing schemes by facilitating communication of a NAND device (Abstract, para 0003 of Gan), which is common and well known in the art for reducing signal propagation delays.
Regarding claim 9, Jung discloses the computing system, wherein the memory page status is determined as one of erased, programed with first pass data, and programed with second pass data based on the threshold voltage state verify sense using a command (para 0038).
Jung, as modified, does not expressly disclose using a single NAND command.
Gan discloses using a single NAND command (para 0031).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Jung is further modifiable as taught by Gan for the purpose of improving data accessing schemes by facilitating communication of a NAND device (Abstract, para 0003 of Gan), which is common and well known in the art for reducing signal propagation delays.
Regarding claim 10, Jung, as modified, does not expressly disclose the computing system, wherein the single NAND command is performed with a preexisting read operation.
Gan discloses single NAND command is performed with a preexisting read operation (para 0018).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Jung is further modifiable as taught by Gan for the purpose of improving data accessing schemes by facilitating communication of a NAND device (Abstract, para 0003 of Gan), which is common and well known in the art for reducing signal propagation delays.
Regarding claim 15, Jung discloses the method, wherein the memory page status is determined as one of erased, programed with first pass data, and programed with second pass data based on the threshold voltage state verify sense using a command (para 0038).
Jung, as modified, does not expressly disclose using a single NAND command.
Gan discloses using a single NAND command (para 0031).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Jung is further modifiable as taught by Gan for the purpose of improving data accessing schemes by facilitating communication of a NAND device (Abstract, para 0003 of Gan), which is common and well known in the art for reducing signal propagation delays.
Regarding claim 16, Jung, as modified, does not expressly disclose the method, wherein the single NAND command is performed with a preexisting read operation.
Gan discloses single NAND command is performed with a preexisting read operation (para 0018).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Jung is further modifiable as taught by Gan for the purpose of improving data accessing schemes by facilitating communication of a NAND device (Abstract, para 0003 of Gan), which is common and well known in the art for reducing signal propagation delays.
Claim(s) 4, 6, 11, 13, 17, 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung (US 2015/0117129) in view of Khakifirooz et al. (US 2019/0103159 ‒hereinafter Khakifirooz), and further in view of Lee (US 2019/0287635).
Regarding claim 4, Jung discloses the semiconductor apparatus, wherein the memory page status is determined as one of erased, programed with first pass data, and programed with second pass data based on the threshold voltage state verify sense and based on a threshold (para 0049).
Jung, as modified, does not expressly disclose a trimmable threshold.
Lee discloses a trimmable threshold (adjustable threshold, such as increasing threshold voltages; fig. 6, para 0049-0050).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Jung is further modifiable as taught by Lee for the purpose of acquiring memory status to determine subsequent steps in performing programming operations (para 0140-0144, 0189 of Lee), which is common and well known in the art for facilitating data accessing schemes and securing integrity of data storage.
Regarding claim 6, Jung, as modified, does not expressly disclose the semiconductor apparatus, wherein the threshold voltage state verify sense is performed at a second from last programming level.
Lee discloses the threshold voltage state verify sense (Vvfy2; fig. 6) is performed at a second from last programming level (i.e. at PV2; fig. 6).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Jung is further modifiable as taught by Lee for the purpose of acquiring memory status to determine subsequent steps in performing programming operations (para 0140-0144, 0189 of Lee), which is common and well known in the art for facilitating data accessing schemes and securing integrity of data storage.
Regarding claim 11, Jung discloses the computing system, wherein the memory page status is determined as one of erased, programed with first pass data, and programed with second pass data based on the threshold voltage state verify sense and based on a threshold (para 0049).
Jung, as modified, does not expressly disclose a trimmable threshold.
Lee discloses a trimmable threshold (adjustable threshold, such as increasing threshold voltages; fig. 6, para 0049-0050).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Jung is further modifiable as taught by Lee for the purpose of acquiring memory status to determine subsequent steps in performing programming operations (para 0140-0144, 0189 of Lee), which is common and well known in the art for facilitating data accessing schemes and securing integrity of data storage.
Regarding claim 13, Jung, as modified, does not expressly disclose the computing system, wherein the threshold voltage state verify sense is performed at a second from last programming level.
Lee discloses the threshold voltage state verify sense (Vvfy2; fig. 6) is performed at a second from last programming level (i.e. at PV2; fig. 6).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Jung is further modifiable as taught by Lee for the purpose of acquiring memory status to determine subsequent steps in performing programming operations (para 0140-0144, 0189 of Lee), which is common and well known in the art for facilitating data accessing schemes and securing integrity of data storage.
Regarding claim 17, Jung discloses the method, wherein the memory page status is determined as one of erased, programed with first pass data, and programed with second pass data based on the threshold voltage state verify sense and based on a threshold (para 0049).
Jung, as modified, does not expressly disclose a trimmable threshold.
Lee discloses a trimmable threshold (adjustable threshold, such as increasing threshold voltages; fig. 6, para 0049-0050).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Jung is further modifiable as taught by Lee for the purpose of acquiring memory status to determine subsequent steps in performing programming operations (para 0140-0144, 0189 of Lee), which is common and well known in the art for facilitating data accessing schemes and securing integrity of data storage.
Regarding claim 19, Jung, as modified, does not expressly disclose the method, wherein the threshold voltage state verify sense is performed at a second from last programming level.
Lee discloses the threshold voltage state verify sense (Vvfy2; fig. 6) is performed at a second from last programming level (i.e. at PV2; fig. 6).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Jung is further modifiable as taught by Lee for the purpose of acquiring memory status to determine subsequent steps in performing programming operations (para 0140-0144, 0189 of Lee), which is common and well known in the art for facilitating data accessing schemes and securing integrity of data storage.
Regarding claim 20, Jung, as modified, does not expressly disclose the method, wherein the threshold voltage state verify sense is performed at one of a last programming level, a second from last programming level, and a third from last programming level.
Lee discloses the threshold voltage state verify sense (Vvfy3/Vvfy2/VVfy1; fig. 6) is performed (i.e. respectively) at a one of a last programming level (i.e. at PV3; fig. 6), a second from last programming level (i.e. PV2; fig. 6), and a third from last programming level (i.e. PV1; fig. 6).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Jung is further modifiable as taught by Lee for the purpose of acquiring memory status to determine subsequent steps in performing programming operations (para 0140-0144, 0189 of Lee), which is common and well known in the art for facilitating data accessing schemes and securing integrity of data storage.
Claim(s) 5, 12, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung (US 2015/0117129) in view of Khakifirooz et al. (US 2019/0103159 ‒hereinafter Khakifirooz), and further in view of Caywood et al. (US 5,621,738 ‒hereinafter Caywood).
Regarding claim 5, Jung, as modified, does not expressly disclose the semiconductor apparatus, wherein the determination of the memory page status bypasses use of program flag bytes.
Caywood discloses bypasses use of program flag bytes (use of program flay bytes S15’ is considered bypassed for No at S14’; fig. 4).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Jung is further modifiable as taught by Caywood for the purpose of facilitating data accessing schemes by improving the overall speed of programming operations (column/line(s): 4/24-31 of Caywood), which is common and well known in the art to reducing signal propagation delays.
Regarding claim 12, Jung, as modified, does not expressly disclose the computing system, wherein the determination of the memory page status bypasses use of program flag bytes.
Caywood discloses bypasses use of program flag bytes (use of program flay bytes S15’ is considered bypassed for No at S14’; fig. 4).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Jung is further modifiable as taught by Caywood for the purpose of facilitating data accessing schemes by improving the overall speed of programming operations (column/line(s): 4/24-31 of Caywood), which is common and well known in the art to reducing signal propagation delays.
Regarding claim 18, Jung, as modified, does not expressly disclose the method, wherein the determination of the memory page status bypasses use of program flag bytes.
Caywood discloses bypasses use of program flag bytes (use of program flay bytes S15’ is considered bypassed for No at S14’; fig. 4).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Jung is further modifiable as taught by Caywood for the purpose of facilitating data accessing schemes by improving the overall speed of programming operations (column/line(s): 4/24-31 of Caywood), which is common and well known in the art to reducing signal propagation delays.
Response to Arguments
Applicant’s arguments with respect to the pending claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/UYEN SMET/
Primary Examiner, Art Unit 2824______