DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
2. The Amendments filed September 19th, 2025 are noted.
Applicant’s amendment(s) to the claims have overcome the 35 U.S.C. § 112 rejection(s)
previously set forth in the Non-Final Office Action mailed 06/26/2025, so the 35 U.S.C. § 112
rejection(s) have been withdrawn.
Applicant’s amendments to the claims are noted.
3. Claims 7, 13, and 15-20 are now canceled; Claims 1-6, 8-12, 14, and 21-28 remain pending in the application.
4. Claims 1-6, 8-12, 14, and 21-28 have been fully considered in examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-6 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Sunamura (U.S. PG Pub No US2014/0061810A1) (of record) in view of Endo (U.S. PG Pub No US2008/0067508A1) (of record).
Regarding claim 1, Sunamura teaches a transistor structure (100) fig. 1A [0092, 0004], comprising:
a gate electrode (222) fig. 1A [0092];
an active layer (220) fig. 1A [0092];
a gate dielectric layer (221) fig. 1A [0092] separating the active layer (220) from the gate electrode (222);
a source electrode (comprising left 285) fig. 1A [0092, 0102] and a drain electrode (comprising right 285) fig. 1A [0092, 0102] both formed uniformly of a material layer (Ti/TiN multilayer [0116] 284 uniformly covers/ has uniform thickness over s/d electrodes 285); and
wherein the material layer (TiN layer of 284 barrier representing Ti/TiN multilayer [0116]) fig. 1A [0092] comprises Ti [0116]; and
a glue layer (Ti layer of 284 barrier representing Ti/TiN multilayer [0116]) fig. 1A [0092] disposed between both the source electrode (left 285) and drain electrode (right 285) and the active layer (220) (although 284 is not explicitly cited in Sunamura’s written disclosure, it is understood from [0116] that it corresponds to the Ti/TiN barrier film over which the source and drain electrodes 285 [0092] are formed).
However, Sunamura does not explicitly disclose a source electrode (left 285) and a drain electrode (right 285) both formed of a hydrogen-rich material.
Endo teaches a transistor structure [see title, fig. 5E, 0098-0104] a source electrode (11) fig. 5E [0102] and a drain electrode (12) fig. 5E [0102] both formed uniformly of a hydrogen-rich material (both comprising metal implanted with hydrogen [0102]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the source/drain electrodes in the transistor structure of Sunamura to be implanted with hydrogen [0102] in order to enable the diffusion of hydrogen into surrounding components [0103] so as to reduce parasitic resistance [0012-0015], thereby providing a FET with improved hysteresis, uniformity, and operation characteristics [0104], as taught by Endo.
Regarding claim 2, Sunamura teaches the transistor structure (100) fig. 1A [0092, 0004] of claim 1. Sunamura also teaches wherein the active layer (220) fig. 1A [0092] comprises one of InGaZnO [0109], InZnO [0109], ZnO [0109].
Regarding claim 3, Sunamura teaches the transistor structure (100) fig. 1A [0092, 0004] of claim 1. Sunamura also teaches wherein the active layer (220) fig. 1A [0092] comprises a composition given by Inx GayZnz MO, wherein 0 < x < 1; 0 y 1; 0 z < 1; and M is one of Ti (understood that IGZO and TiO2 may be combined in a plurality of layers such that the overall composition of 220 is represented by any desired stoichiometric formula).
Regarding claim 4, Sunamura teaches the transistor structure (100) fig. 1A [0092, 0004] of claim 1. Sunamura also teaches wherein the gate dielectric layer (221) fig. 1A [0092] comprises a high-k dielectric material comprising one or more of hafnium oxide [0113], zirconium oxide [0113], titanium oxide [0113], aluminum oxide [0113].
Regarding claim 5, Sunamura teaches the transistor structure (100) fig. 1A [0092, 0004] of claim 1. Sunamura also teaches wherein the gate dielectric layer (221) fig. 1A [0092] comprises an alternating multi-layer structure comprising silicon oxide and silicon nitride (a combination / a permutation of SiO2 and SiNx may be used [0113]).
Regarding claim 6, Sunamura teaches the transistor structure (100) fig. 1A [0092, 0004] of claim 1. Sunamura also teaches wherein the gate dielectric layer (221) fig. 1A [0092] comprises a ferroelectric material (hafnium-oxide [0113]).
Although Sunamura does not explicitly disclose the magnetic qualities of gate dielectric layer 221, Sunamura [0113] discloses that gate dielectric 221 may comprise an oxide of Hf – i.e, Hafnium-Oxide/ HfO2 – which is substantially the same material as disclosed by [0077 instant application] for ferroelectric dielectric materials. Therefore, the gate dielectric 221 of Sunamura is considered to possess the essential qualities of a ferroelectric material – in view of [0077] of the instant application’s disclosure. (See MPEP 2112.01, II).
Regarding claim 21, Sunamura teaches the transistor structure (100) fig. 1A [0092, 0004] of claim 1. Sunamura also teaches further comprising:
an inter-layer dielectric layer (152) fig 1A [0092] (“interlayer insulating layer”); and
a capping layer (171) fig. 1A [0099] (“cap insulating layer”) disposed between the active layer (220) and the inter-layer dielectric layer (152).
Claims 8-12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Sunamura (U.S. PG Pub No US2014/0061810A1) (of record) in view of Lee (U.S. PG Pub No US2019/0131360A1) (of record) and Jang (U.S. PG Pub No US2019/0244820A1) (of record).
Regarding claim 8, Sunamura teaches a transistor structure (100) fig. 1A [0092, 0004], comprising:
a gate electrode (222) fig. 1A [0092];
an active layer (220) fig. 1A [0092];
an inter-layer dielectric layer (152) fig 1A [0092] (“interlayer insulating layer”);
a capping layer (171 with 172) fig. 1A [0099] (“cap insulating layer”) disposed between the active layer (220) and the inter-layer dielectric layer (152) and in direct contact with a top surface of the active layer (220);
a gate dielectric layer (221) fig. 1A [0092] separating the active layer (220) from the gate electrode (222); and
a source electrode (left 286 comprising 285) fig. 1A [0092, 0102] and a drain electrode (right 286 comprising 285) fig. 1A [0092, 0102], wherein each of the source electrode (left 286) and drain electrode (right 286) comprise a fill material (284) fig. 1A [0092].
However, Sunamura does not explicitly disclose a capping layer (171) disposed between the active layer and inter-layer dielectric (152);
wherein the capping layer is disposed between the source electrode (left 286 comprising 285) and drain electrode (right 286 comprising 285),
wherein the fill material (284) is a hydrogen-rich material layer (of Ti/TiN [0116]).
Lee teaches a transistor structure [see fig. 4, 0076] comprising a capping layer (INT1) fig. 4 [0081] disposed between the active layer (A) fig. 4 [0080] and inter-layer dielectric (INT2) fig. 4 [0083];
wherein the capping layer (INT1) is disposed between the source electrode (SE) fig. 4 [0084] and drain electrode (DE) fig. 4 [0084].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified to have provided an additional insulating layer disposed between the interlayer dielectric and the active layer [0080-0084] as well as between the source and drain electrodes [0080-0084] enhance the dielectric protection offered by the interlayer dielectric(s) [0080-0084] as well as vary the material composition of the insulating layers [0080-0084], as taught by Lee.
However, Sunamura in view of Lee does not explicitly disclose wherein the fill material (284) is a hydrogen-rich material layer (of Ti/TiN [0116]).
Jang teaches a transistor structure [see fig. 10F, 0062, 0003] wherein the (TiN) [0179] fill material (19L’) fig. 10F [0179] is a hydrogen-rich material layer (TiN doped with hydrogen [00177-0179]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the TiN-barrier layer in the transistor structure of Sunamura in view of Lee to be enriched with hydrogen [0177-0179] in order to lower its resistance [0176], thereby improving its conductivity [0176-0179], as taught by Jang.
Regarding claim 9, Sunamura teaches the transistor structure (100) fig. 1A [0092, 0004] of claim 1. Sunamura also teaches wherein the active layer (220) fig. 1A [0092] comprises one of InGaZnO [0109], InZnO [0109], ZnO [0109].
Regarding claim 10, Sunamura teaches the transistor structure (100) fig. 1A [0092, 0004] of claim 1. Sunamura also teaches wherein the active layer (220) fig. 1A [0092] comprises a composition given by Inx GayZnz MO, wherein 0 < x < 1; 0 y 1; 0 z < 1; and M is one of Ti (understood that IGZO and TiO2 may be combined in a plurality of layers such that the overall composition of 220 is represented by any desired stoichiometric formula).
Regarding claim 11, Sunamura teaches the transistor structure (100) fig. 1A [0092, 0004] of claim 8. Sunamura also teaches wherein the gate dielectric layer (221) fig. 1A [0092] comprises a high-k dielectric material comprising one or more of hafnium oxide [0113], zirconium oxide [0113], titanium oxide [0113], aluminum oxide [0113].
Regarding claim 12, Sunamura teaches the transistor structure (100) fig. 1A [0092, 0004] of claim 8. Sunamura also teaches further comprising a glue layer (290) fig. 1A [0092, 0116] (comprising metallic-liner/barrier such as TiN) [0116] separating (diagonally-separating) the source electrode (left 286 comprising 285) fig. 1A [0092, 0102] from the active layer (220) fig. 1A [0092] and separating the drain electrode (right 286 comprising 285) fig. 1A [0092, 0102] from the active layer (220).
Regarding claim 14, Sunamura teaches the transistor structure (100) fig. 1A [0092, 0004] of claim 8. Sunamura in view of Jang also teaches wherein the hydrogen-rich material layer (284) fig. 1A [0092] (H-doped by Jang) comprises TiN and alloys of Ti (Ti/TiN) [0116] and mixtures thereof, with or without N and/or 0, deposited by chemical vapor deposition or by atomic layer deposition.
For the purposes of Examination, the limitation(s) in the structure-claims concerning the particular deposition process, i.e, CVD of ALD, of the hydrogen-rich material layer have been considered as product-by-process limitations since they do not impart a unique structure in the finished product (See MPEP 2113, I).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Sunamura (U.S. PG Pub No US2014/0061810A1) (of record) modified by Endo (U.S. PG Pub No US2008/0067508A1) (of record), as applied in claim 21 above, and further in view of Lee (U.S. PG Pub No US2019/0131360A1) (of record).
Regarding claim 22, Sunamura teaches the transistor structure (100) fig. 1A [0092, 0004] of claim 21. However, Sunamura does not explicitly disclose wherein the capping layer (171) fig. 1A [0099] (“cap insulating layer”) is disposed between the source electrode (left 286 comprising 285) and drain electrode (right 286 comprising 285).
Lee teaches a transistor structure [see fig. 4, 0076] wherein the capping layer (INT1) fig. 4 [0081] is disposed between the source electrode (SE) fig. 4 [0084] and drain electrode (DE) fig. 4 [0084].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified to have expanded the capping layer of Sunamura to additional dielectric material disposed between the source and drain electrodes [0080-0084] in order to enhance the dielectric protection offered by the dielectric(s) [0080-0084] as well as vary the material composition of the insulating layers [0080-0084], as taught by Lee.
Claims 23-28 are rejected under 35 U.S.C. 103 as being unpatentable over Sunamura (U.S. PG Pub No US2014/0061810A1) (of record) in view of Jang (U.S. PG Pub No US2019/0244820A1) (of record).
Regarding claim 23, Sunamura teaches a transistor structure (100) fig. 1A [0092, 0004], comprising (for the purposes of Examination, fig. 1A of Sunamura has been considered from a flipped perspective):
a gate electrode (222) fig. 1A [0092];
an active layer (220) fig. 1A [0092];
a gate dielectric layer (221) fig. 1A [0092] that is in contact with the gate electrode (222) and the active layer (220) and separates the gate electrode (222) from the active layer (220); and
an inter-layer dielectric layer (171 with 172) fig 1A [0099] over the active layer (220) such that an entirety of a top surface of the active layer (220) (in flipped perspective; see modified fig. 1A of Sunamura below) is in direct contact with the inter-layer dielectric layer (comprising 171); and
a source electrode (left 286 comprising 285) fig. 1A [0092, 0102] and a drain electrode (right 286 comprising 285) fig. 1A [0092, 0102] surrounded (laterally) by the inter-layer dielectric layer (171 with 172), wherein a material layer (left/right barrier film TiN implied as 284) fig. 1A [0116] separates the source electrode (left 286 comprising 285) and the drain electrode (right left 286 comprising 285) from the active layer (220).
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Fig. 1A of Sunamura from flipped perspective
However, Sunamura does not explicitly disclose wherein the material layer (TiN barrier layer) is a hydrogen-rich material layer.
Jang teaches a transistor structure [see fig. 10F, 0062, 0003] wherein the material layer (which separates the electrodes (represented by 21) fig. 10F [0181-0183] from the active layer (11 comprising 14) fig. 10F [0182, 0184]) is a hydrogen-rich material layer (TiN) [0179] fill material (19L’) fig. 10F [0179].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the TiN-barrier layer in the transistor structure of Sunamura to be enriched with hydrogen [0177-0179] in order to lower its resistance [0176], thereby improving its conductivity [0176-0179], as taught by Jang.
Regarding claim 24, Sunamura teaches the transistor structure (100) fig. 1A [0092, 0004] of claim 23. Sunamura also teaches wherein the gate dielectric layer (221) fig. 1A [0092] comprises a high-k dielectric material comprising one or more of hafnium oxide [0113], zirconium oxide [0113], titanium oxide [0113], aluminum oxide [0113].
Regarding claim 25, Sunamura teaches the transistor structure (100) fig. 1A [0092, 0004] of claim 23. Sunamura also teaches wherein the gate dielectric layer (221) fig. 1A [0092] further comprises:
comprises an alternating multi-layer structure comprising silicon oxide and silicon nitride (a combination / a permutation of SiO2 and SiNx may be used [0113]) over the gate electrode (222) see modified fig. 1A perspective above [0092]; or
a ferroelectric material (221 = hafnium-oxide [0113]) over the gate electrode (222).
Although Sunamura does not explicitly disclose the magnetic qualities of gate dielectric layer 221, Sunamura [0113] discloses that gate dielectric 221 may comprise an oxide of Hf – i.e, Hafnium-Oxide/ HfO2 – which is substantially the same material as disclosed by [0077 instant application] for ferroelectric dielectric materials. Therefore, the gate dielectric 221 of Sunamura is considered to possess the essential qualities of a ferroelectric material – in view of [0077] of the instant application’s disclosure. (See MPEP 2112.01, II).
Regarding claim 26, Sunamura teaches the transistor structure (100) fig. 1A [0092, 0004] of claim 23. Sunamura also teaches wherein the active layer (220) fig. 1A [0092] comprises one of InGaZnO [0109], InZnO [0109], ZnO [0109] over the gate dielectric layer (221) modified fig. 1A above [0092].
Regarding claim 27, Sunamura teaches the transistor structure (100) fig. 1A [0092, 0004] of claim 23. Sunamura in view of Jang also teaches further comprising a conductive material (289) fig. 1A [0116, 0092] (at least partially) over the hydrogen-rich material layer (left/right barrier film TiN implied as 284) fig. 1A [0116] (modified by Jang to be hydrogen-enriched) further separating the source electrode (left 286 comprising 285) fig. 1A [0092, 0102] and the drain electrode (right 286 comprising 285) fig. 1A [0092, 0102].
Regarding claim 28, Sunamura teaches the transistor structure (100) fig. 1A [0092, 0004] of claim 23. Sunamura also teaches further comprising a plurality of metal interconnect structures (162, 164, 187, 188) fig. 1A [0092] in an existing semiconductor structure (100), wherein the transistor (comprising 220) fig. 1A [0092] is located (at least partially) over one of the plurality of metal interconnect level structures (188) fig. 1A [0092] (in flipped perspective of fig. 1A.
Response to Arguments
Applicant's arguments filed 09/19/2025 have been fully considered but they are not persuasive.
Applicant’s argument(s) and amendment(s) with respect to claim 1 have been considered but are rendered largely moot because of an interpretation of the term “uniformly” as relating to geometry – more specifically, the thickness of the (hydrogen-rich) material. "Uniformly", as recited in claim, appears broad/ambiguous because it's not really clear what is uniformly "formed". For example, if both source and drain comprise a hydrogen-rich material, and they both have the same thickness, then it could be interpreted that the source and drain are formed uniformly (thick) of a hydrogen rich material.
Therefore, the rejection of record is maintained on the basis that (in Sunamura) “… a source electrode (comprising left 285) fig. 1A [0092, 0102] and a drain electrode (comprising right 285) fig. 1A [0092, 0102] both formed uniformly of a material layer (Ti/TiN multilayer [0116] 284 uniformly covers/ has uniform thickness over s/d electrodes 285)” --- that the materials composing the source/drain electrodes in Sunamura already have uniform-thickness, and that (in Endo) “a source electrode (11) fig. 5E [0102] and a drain electrode (12) fig. 5E [0102] both formed uniformly of a hydrogen-rich material (both comprising metal implanted with hydrogen [0102])” --- that the hydrogen-rich materials composing the source/drain electrodes in Endo also have uniform-thickness, and that the modification of Sunamura by Endo results in uniformly-formed (thick) hydrogen-rich source/drain electrodes in Sunamura’s device.
Applicant’s arguments with respect to independent claim(s) 8 and 23 have been fully considered but are rendered largely moot by a reinterpretation of both the capping layer of claim 8 and the inter-layer dielectric layer of claim 23 to further comprise insulating material layer (172) fig. 1A [0099] of Sunamura – which reads on the amended limitation(s) in claims 8 and 23 (see respective rejections above). It is noted that because element 172 of Sunamura is not cited elsewhere in the rejections of record, this reinterpretation raises no contradiction(s) with the rejection(s) of record.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Other remaining references on the PTO-892 form (of record) disclose source/drain electrodes composed of hydrogen-rich materials.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 12/01/2025
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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