DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/09/2026 has been entered.
Claim Objections
Claim 23 is objected to because of the following informalities:
Claim 23, line 3: “the first inter-dielectric” should read --- the first inter-dielectric layer ---
Claim 24, lines 2-3: “wherein the high-k dielectric material comprising one or more of” should read --- wherein the high-k dielectric material comprises one or more of ---
Appropriate correction is required.
Claim Interpretation
For the purposes of Examination, for consistency with the level of support provided by the instant application’s disclosure, Examiner notes that, with respect to the term “an entirety” in claim 23, Examiner interprets “an entirety of a top surface” to be a portion of a top surface entirely satisfying the claimed limitation(s), rather than the ‘entire’ top surface overall.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-6 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Koezuka (U.S. PG Pub No US US2014/0374908A1) in view of Endo (U.S. PG Pub No US2008/0067508A1) (of record).
Regarding claim 1, Koezuka teaches a transistor structure (200) fig. 1B [0049], comprising:
a gate electrode (104) fig. 1B [0050] disposed in a first inter-dielectric layer (106) fig. 1B [0050] (layer 106 interposed-between layers 104, 108 may be formed of dielectric such as silicon nitride [0075, 0077]);
a gate dielectric layer (108) fig. 1B [0051] disposed on (supported by) the gate electrode (104) and the first inter-dielectric layer (106);
an active layer (110) fig. 1B [0050-0051] (110 active layer hosting transistor channel [0090-0093]) having a top surface and sidewalls, wherein the active layer (11) is disposed (directly) on the gate dielectric layer (108);
a source electrode (114a of 116a) fig. 1B [0052] and a drain electrode (114b of 116b) fig. 1B [0052], both formed uniformly of a material, wherein the material comprises at least one of TiN and Ti (114 a/b may be formed of Ti/TiN [0055]), and
wherein the source electrode (114a) and the drain electrode (114b) abut (conforms to borders of and is supported by) the gate dielectric layer (108), the top surface and the sidewalls of the active layer (110); and
a glue layer (112a/b) fig. 1B [0054] (may be formed of titanium nitride [0054]) ([0073] of Koezuka evidences that the material of 112 a/b, such as TiN [0054], promotes adhesion/gluing, thus, 112a/b acts as glue/gluing layer between 110 and 114a/b) disposed between both the source electrode (comprising 114a) and drain electrode (comprising 114b) and the active layer (110).
However, Koezuka does not explicitly disclose the source electrode (114a) and a drain electrode (114b) both formed uniformly of a hydrogen-rich material (Ti/TiN mentioned [0055], however, hydrogen not disclosed).
Endo teaches a transistor structure [see title, fig. 5E, 0098-0104] comprising a source electrode (11) fig. 5E [0102] and a drain electrode (12) fig. 5E [0102] both formed uniformly of a hydrogen-rich material (both comprising metal implanted with hydrogen [0102]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the source/drain electrodes in the transistor structure of Koezuka to be implanted with hydrogen [0102] in order to enable the diffusion of hydrogen into surrounding components [0103] so as to reduce parasitic resistance [0012-0015], thereby providing a FET with improved hysteresis, uniformity, and operation characteristics [0104], as taught by Endo.
Regarding claim 2, Koezuka in view of Endo teaches the transistor structure of claim 1. Koezuka also teaches wherein the active layer (110) fig. 1B [0050-0051] comprises InZnO [0083].
Regarding claim 3, Koezuka in view of Endo teaches the transistor structure of claim 1. Koezuka also teaches wherein the active layer (110) fig. 1B [0050-0051] comprises a composition given by InxGayZnz MO (oxide-containing In-Ga-Zn-O [0083]), wherein 0 < x < 1; 0 ≤y ≤1; 0 ≤z ≤ 1; and M is one of Ti, Al, Ag, Ce, Ga and Sn (may comprise InZnMO, wherein M is Ti; InZnTiO is InxGayZnz MO wherein y = 0 and z = 1 and x = 1 [0083-0084]).
Regarding claim 4, Koezuka in view of Endo teaches the transistor structure of claim 1. Koezuka also teaches wherein the gate dielectric layer (108) fig. 1B [0051, 0080] comprises a high-k dielectric material [0080] comprising hafnium oxide [0080].
Regarding claim 5, Koezuka in view of Endo teaches the transistor structure of claim 1. Koezuka also teaches wherein the gate dielectric layer (108) fig. 1B [0051, 0075] comprises an alternating multi-layer structure [0075] comprising silicon oxide and silicon nitride (may be three or more layers of silicon oxide – silicon nitride – silicon oxide [0075]).
Regarding claim 6, Koezuka in view of Endo teaches the transistor structure of claim 1. Koezuka also teaches further comprising a second inter-dielectric layer (122) fig. 1B [0065, 0104] (layer 122 interposed-between layers 106, 124 may be formed of dielectric such as silicon nitride [0065, 0077, 0104]), wherein the active layer (110) fig. 1B [0050-0051], the source electrode (114a of 116a) fig. 1B [0052], and the drain electrode (114b of 116b) fig. 1B [0052] are disposed in the second inter-dielectric layer (122).
Regarding claim 21, Koezuka in view of Endo teaches the transistor structure of claim 1. Koezuka also teaches further comprising an inter-layer dielectric layer (122) fig. 1B [0065, 0104] (layer 122 interposed-between layers 106, 124 may be formed of dielectric such as silicon nitride [0065, 0077, 0104]); and
a capping layer (124) fig. 1B [0065, 0101, 0105] (acting to cap / cover underlying layers 110, 122, etc.) located (diagonally) between (portions of) the active layer (114b of 116b) fig. 1B [0052] and the inter-layer dielectric layer (122).
Regarding claim 22, Koezuka in view of Endo teaches the transistor structure of claim 21. Koezuka also teaches wherein the capping layer is disposed (horizontally) between (portions of) the source electrode (114a of 116a) fig. 1B [0052] and the drain electrode (114b of 116b) fig. 1B [0052].
Claims 8-12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Koezuka (U.S. PG Pub No US2014/0374908A1) in view of Lee (U.S. PG Pub No US2015/0200208A1) and Jang (U.S. PG Pub No US2019/0244820A1) (of record).
Regarding claim 8, Koezuka teaches a transistor structure (200) fig. 1B [0049], comprising:
a gate electrode (104) fig. 1B [0050] disposed in a first inter-dielectric layer (106) fig. 1B [0050] (layer 106 interposed-between layers 104, 108 may be formed of dielectric such as silicon nitride [0075, 0077]);
a gate dielectric layer (108) fig. 1B [0051] disposed on (supported by) the gate electrode (104) and the first inter-dielectric layer (106);
an active layer (110) fig. 1B [0050-0051] (110 active layer hosting transistor channel [0090-0093]) disposed (directly) on the gate dielectric layer (108), wherein the active layer (110) includes a top surface and sidewalls;
a second inter-layer dielectric layer (122) fig. 1B [0065, 0104] (layer 122 interposed-between layers 106, 124 may be formed of dielectric such as silicon nitride [0065, 0077, 0104]) over (above) the active layer (110);
a source electrode (114a of 116a) fig. 1B [0052] and a drain electrode (114b of 116b) fig. 1B [0052], wherein each of the source electrode (114a) and the drain electrode (114b) comprise a film material (114 a/b may be formed of Ti/TiN [0055]), and wherein the source electrode (114a) and the drain electrode (114b) are in (thermal) contact with the gate dielectric layer (108) and the sidewalls of the active layer (110) (114a/b of 116a/b thermally connected to 108, 110 through 112a/b of 116a/b [0054]).
However, Koezuka does not explicitly disclose a capping layer disposed between the active layer (110) and the second inter-layer dielectric (122) and in direct contact with the top surface of the active layer (110);
wherein the capping layer is disposed between the source electrode (114a) and drain electrode (114b),
wherein the fill material (of 114a/b) is a hydrogen-rich material layer (of Ti/TiN [0055]).
Lee teaches a transistor structure [see fig. 2, 0039-0040] comprising a capping layer (180) fig. 2 [0057-0058, 0081] (acting to cap / cover underlying layers 140, 151, etc.) disposed between the active layer (151) fig. 2 [0003, 0045] and inter-layer dielectric (181) fig. 2 [0059-0060, 0081] (dielectric disposed between layers 173, 175) and in direct contact with the top surface of the active layer (151);
wherein the capping layer (180) is disposed (horizontally) between the source electrode (173r) fig. 2 [0051-0053] and drain electrode (175r) fig. 2 [0051-0053].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified to have provided an additional insulating layer disposed between the interlayer dielectric and the active layer [0003, 0045, 0057-0060] as well as between the source and drain electrodes [0051-0053] in order to enhance the dielectric protection offered by the interlayer dielectric(s) [0057-0060] as well as the amount of insulation material [0057] between the source/drain electrodes [0051-0053], as taught by Lee.
However, Koezuka in view of Lee does not explicitly disclose wherein the fill material (114a/b) is a hydrogen-rich material layer (of Ti/TiN [0054-0055]).
Jang teaches a transistor structure [see fig. 10F, 0062, 0003] wherein the (TiN) [0179] fill material (19L’) fig. 10F [0179] is a hydrogen-rich material layer (TiN doped with hydrogen [0177-0179]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the TiN-barrier layer in the transistor structure of Koezuka in view of Lee to be enriched with hydrogen [0177-0179] in order to lower its resistance [0176], thereby improving its conductivity [0176-0179], as taught by Jang.
Regarding claim 9, Koezuka in view of Lee and Jang teaches the transistor structure of claim 8. Koezuka also teaches wherein the active layer (110) fig. 1B [0050-0051] comprises InZnO [0083].
Regarding claim 10, Koezuka in view of Lee and Jang teaches the transistor structure of claim 8. Koezuka also teaches wherein the active layer (110) fig. 1B [0050-0051] comprises a composition given by InxGayZnz MO (oxide-containing In-Ga-Zn-O [0083]), wherein 0 < x < 1; 0 ≤y ≤1; 0 ≤z ≤ 1; and M is one of Ti, Al, Ag, Ce, Ga and Sn (may comprise InZnMO, wherein M is Ti; InZnTiO is InxGayZnz MO wherein y = 0 and z = 1 and x = 1 [0083-0084]).
Regarding claim 11, Koezuka in view of Lee and Jang teaches the transistor structure of claim 8. Koezuka also teaches wherein the gate dielectric layer (108) fig. 1B [0051, 0080] comprises a high-k dielectric material [0080] comprising hafnium oxide [0080].
Regarding claim 12, Koezuka in view of Lee and Jang teaches the transistor structure of claim 8. Koezuka also teaches further comprising a glue layer (112a/b) fig. 1B [0054] (may be formed of titanium nitride [0054]) ([0073] of Koezuka evidences that the material of 112 a/b, such as TiN [0054], promotes adhesion/gluing, thus, 112a/b acts as glue/gluing layer between 110 and 114a/b) separating the source electrode (114a of 116a) fig. 1B [0052] from the active layer (110) fig. 1B [0050-0051] and separating the drain electrode (114b of 116b) fig. 1B [0052] from the active layer (110).
Regarding claim 14, Koezuka in view of Lee and Jang teaches the transistor structure of claim 8. Koezuka in view of Jang also teaches wherein the hydrogen-rich fill material (114 a/b) fig. 2 [0055] (may be formed of Ti/TiN [0055]) (H-doped by Jang [0177-0179 Jang]) comprises TiN (Ti/TiN) [0055], deposited by chemical vapor deposition or by atomic layer deposition.
For the purposes of Examination, the limitation(s) in the structure-claims concerning the particular deposition process, i.e, CVD of ALD, of the hydrogen-rich material layer have been considered as product-by-process limitations since they do not impart a unique structure in the finished product (See MPEP 2113, I).
Claims 23-28 are rejected under 35 U.S.C. 103 as being unpatentable over Koezuka (U.S. PG Pub No US US2014/0374908A1) in view of Jang (U.S. PG Pub No US2019/0244820A1) (of record).
Regarding claim 23, Koezuka teaches a transistor structure (200) fig. 1B [0049], comprising:
a gate electrode (104) fig. 1B [0050] disposed in a first inter-dielectric layer (106) fig. 1B [0050] (layer 106 interposed-between layers 104, 108 may be formed of dielectric such as silicon nitride [0075, 0077]);
a gate dielectric layer (108) fig. 1B [0051] disposed on (supported by) the gate electrode (104) and the first inter-dielectric layer (106);
an active layer (110) fig. 1B [0050-0051] (110 active layer hosting transistor channel [0090-0093]) having a top surface and sidewalls, wherein the active layer (11) is disposed (directly) on the gate dielectric layer (108);
a second inter-layer dielectric layer (122) fig. 1B [0065, 0104] (layer 122 interposed-between layers 106, 124 may be formed of dielectric such as silicon nitride [0065, 0077, 0104]) over (above) the active layer (110) such that an entirety (an entire, respective portion in direct contact with 122) of a top surface of the active layer (110) is in direct contact with the second inter-layer dielectric layer (122); and
a source electrode (114a of 116a) fig. 1B [0052] and a drain electrode (114b of 116b) fig. 1B [0052] surrounded (laterally) by the second inter-layer dielectric layer (122), wherein a material layer (112a/b) fig. 1B [0054] (may be formed of titanium nitride [0054]) separates the source electrode (114a) and the drain electrode (114b) from the active layer (110), and wherein the material layer (112a-b) is in (direct) contact with the top surface (of 110), the sidewalls (of 110), and the gate dielectric layer (108).
However, Koezuka does not explicitly disclose wherein the material layer (112a/b) is a hydrogen-rich material layer (hydrogen not disclosed for TiN layer [0054]).
Jang teaches a transistor structure [see fig. 10F, 0062, 0003] wherein the material layer (which separates the electrodes (represented by 21) fig. 10F [0181-0183] from the active layer (11 comprising 14) fig. 10F [0182, 0184]) is a hydrogen-rich material layer (TiN) [0179] fill material (19L’) fig. 10F [0179].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the TiN-barrier layer in the transistor structure of Koezuka to be enriched with hydrogen [0177-0179] in order to lower its resistance [0176], thereby improving its conductivity [0176-0179], as taught by Jang.
Regarding claim 24, Koezuka in view of Jang teaches the transistor structure of claim 23. Koezuka also teaches wherein the gate dielectric layer (108) fig. 1B [0051, 0080] comprises a high-k dielectric material [0080] over the gate electrode (104) fig.1B [0051], wherein the high-k dielectric material comprises hafnium oxide [0080].
Regarding claim 25, Koezuka in view of Jang teaches the transistor structure of claim 23. Koezuka also teaches wherein the gate dielectric layer (108) fig. 1B [0051, 0075] further comprises:
an alternating multi-layer structure [0075] comprising silicon oxide and silicon nitride (may be three or more layers of silicon oxide – silicon nitride – silicon oxide [0075]) over the gate electrode (104) fig. 1B [0051].
Regarding claim 26, Koezuka in view of Jang teaches the transistor structure of claim 23. Koezuka also teaches wherein the active layer (110) fig. 1B [0050-0051] further comprises InZnO [0083].
Regarding claim 27, Koezuka in view of Jang teaches the transistor structure of claim 23. Koezuka in view of Jang also teaches further comprising a conductive material (118a/118b) fig. 1B [0050] (118a/b formed of conductive oxide such as ITO [0061]) over the hydrogen-rich material layer (112a/112b) fig. 1B [0054] (TiN barrier modified by Jang to be hydrogen-enriched) further (horizontally) separating the source electrode (114a of 116a) fig. 1B [0052] and the drain electrode (114b of 116b) fig. 1B [0052].
Regarding claim 28, Koezuka in view of Jang teaches the transistor structure of claim 23. Koezuka in view of Jang also teaches wherein the first inter-dielectric layer (106) fig. 1B [0050] and the second inter-dielectric layer (122) fig. 1B [0065, 0104] are (vertically) separated by the gate dielectric layer (108) fig. 1B [0051].
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 8, and 23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Other remaining references newly-added to the PTO-892 form are considered relevant to the present disclosure because they all feature examples of bottom gate thin film transistors with interlayer dielectrics and/or barrier layers.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 08/14/2026
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