Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
Claims 15-19, 21, 24-25, 29, 30, and 32-34 are rejected under 35 U.S.C. 103 as being unpatentable over Reznicek (PGPub No. 20210193829) in further view of Wu (PGPub No. 20200287021) and Kwon (PGPub No. 20180301564).
Regarding claim 15, Reznicek teaches forming a gate structure (Fig. 2, 210) on a first channel region (Fig. 2, 120 & 130); forming a first recess in a substrate adjacent the gate structure (Fig. 3B); and depositing a first spacer layer in the first recess (Fig. 4B, 410). Specifically, Reznicek teaches a semiconductor structure comprising a semiconductor material stack (first channel region) made up of alternating layers of semiconductor material layer 120 and semiconductor channel material layer 130, sacrificial gate structures 210 located on top of said stack (Fig 2; [0045] & [0053]), a recess within the semiconductor material stack adjacent to the gate structures 210 (Fig. 3B), and a dielectric gate spacer material layer 410 (first spacer layer) formed within said recess (Fig. 4B; [0066]).
Reznicek fails to teach depositing a second spacer layer on the first spacer layer in the first recess; etching the first spacer layer and the second spacer layer using a first etching process to form a first inner spacer portion and a second inner spacer portion, respectively, in the first recess; and forming a source/drain region in the first recess and overlapping an uppermost surface of the first inner spacer portion in a cross-sectional view, wherein a bottom air gap in the first recess, wherein the bottom air gap is enclosed by a bottommost surface of the source/drain region and the uppermost surface of the first inner spacer portion in the first recess in the cross-sectional view.
Wu teaches depositing a second spacer layer on the first spacer layer in the first recess (Fig. 6, 162-1 & 162-2); and etching the first spacer layer and the second spacer layer using a first etching process to form a first inner spacer portion and a second inner spacer portion, respectively, in the first recess (Fig. 8, 170). Specifically, Wu teaches a method for fabricating a semiconductor device comprising a hardened inner spacer layer 162-1 (first spacer layer) formed from inner spacer layer 160-1 (Fig. 5; [0044]), a second hardened inner spacer 162-2 (second spacer layer) formed from inner spacer layer 160-2 (Fig. 7; [0046]), and inner spacers 170 formed after an inner spacer etch (Fig. 8; [0047]). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to modify the overall structure as taught in Reznicek according to the teachings of Wu, where two spacer layers are now deposited and etched to form inner spacer portions in order to improve the inner spacer quality and prevent source/drain epitaxial material etch out.
Reznicek et al. still fails to teach forming a source/drain region in the first recess and overlapping an uppermost surface of the first inner spacer portion in a cross-sectional view, wherein a bottom air gap in the first recess, wherein the bottom air gap is enclosed by a bottommost surface of the source/drain region and the uppermost surface of the first inner spacer portion in the first recess in the cross-sectional view.
Kwon teaches forming a source/drain region in the first recess (Fig. 15A; SD) and overlapping an uppermost surface of the first inner spacer portion in a cross-sectional view (Id.; 148a), wherein a bottom air gap in the first recess, wherein the bottom air gap is enclosed by a bottommost surface of the source/drain region and the uppermost surface of the first inner spacer portion in the first recess in the cross- sectional view (Id.; AG). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Reznicek et al. and Kwon, such that an air gap is formed between a source/drain region and the first inner spacer portion in order to provide an adequate degree of separation between said region and portion which by extension would prevent an undue interference between each of the components.
Regarding claim 16, Wu teaches wherein the first etching process etches the second spacer layer at a rate at least five times greater than a rate at which the first etching process etches the first spacer layer ([0042-46]). Specifically, Wu teaches hardened inner spacers 162-1 and 162-2 formed from inner spacer layers 160-1 and 160-2 respectively via UV condensation (Figs. 4-7; [0042-46]). Inner spacer layers 160-1 and 160-2 can include any suitable dielectric material, such as a low-k dielectric material ([0042] & [0045]). Examples of suitable low-k dielectric materials can be formed from include, but are not limited to, nitrides (e.g., SiN), carbonitrides (e.g., SiCN, SiBCN, and SiOCN), organosilicate glass (OSG), oxides (e.g., fluorine doped silicon dioxide, carbon doped silicon dioxide, porous silicon dioxide, and porous carbon doped silicon dioxide), spin-on materials (e.g., spin-on organic polymeric dielectrics and spin-on silicon based polymeric dielectrics (e.g., hydrogen silsesquioxane (HSQ) and methylsilsesquioxane (MSQ))), etc. ([0043]). Regarding the etch rates of each spacer layer, it is interpreted that one of ordinary skill in the art would consider these rates to obviously be based on the material composition of the spacer layer. Since the claimed invention discloses that the spacer layers “may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like” (see [0035]), it is further interpreted that a reference teaching spacer layers of similar/same composition would obviously teach the same relative etch rates as claimed.
Regarding claim 17, Wu teaches wherein the first spacer layer comprises a first material, and wherein the second spacer layer comprises a second material different from the first material ([0043]). Specifically, Wu teaches hardened inner spacers 162-1 and 162-2 formed from inner spacer layers 160-1 and 160-2 respectively via UV condensation (Figs. 4-7; [0042-46]). Inner spacer layers 160-1 and 160-2 can include any suitable dielectric material, such as a low-k dielectric material ([0042] & [0045]). Examples of suitable low-k dielectric materials can be formed from include, but are not limited to, nitrides (e.g., SiN), carbonitrides (e.g., SiCN, SiBCN, and SiOCN), organosilicate glass (OSG), oxides (e.g., fluorine doped silicon dioxide, carbon doped silicon dioxide, porous silicon dioxide, and porous carbon doped silicon dioxide), spin-on materials (e.g., spin-on organic polymeric dielectrics and spin-on silicon based polymeric dielectrics (e.g., hydrogen silsesquioxane (HSQ) and methylsilsesquioxane (MSQ))), etc. ([0043]).
Regarding claim 18, Reznicek teaches forming a multi-layer stack on the substrate, the multi-layer stack comprising alternating layers of a first semiconductor material and a second semiconductor material different from the first semiconductor material (Fig. 1, 120 & 130), wherein the gate structure is formed on the multi-layer stack (Fig. 2, 210), and wherein the first recess is formed through the multi-layer stack and forms a plurality of nanostructures from the multi-layer stack (Fig. 3B). Specifically, Reznicek teaches a semiconductor structure comprising a semiconductor material stack (multi-layer stack) made up of alternating layers of semiconductor material layer 120 and semiconductor channel material layer 130, sacrificial gate structures 210 located on top of said stack (Fig 2; [0045] & [0053]), and a recess within the semiconductor material stack adjacent to the gate structures 210 (Fig. 3B) resulting in the formation of nanosheet stacks (plurality of nanostructures).
Reznicek fails to teach etching a sidewall of the first semiconductor material to form a sidewall recess, wherein the first spacer layer and the second spacer layer are deposited in the sidewall recess and fill the sidewall recess, wherein etching the first spacer layer and the second spacer layer using the first etching process forms a third inner spacer portion and a fourth inner spacer portion, respectively, in the sidewall recess.
Wu teaches etching a sidewall of the first semiconductor material to form a sidewall recess (Fig. 3, 150), wherein the first spacer layer and the second spacer layer are deposited in the sidewall recess and fill the sidewall recess (Fig. 7, 162-1 & 162-2), wherein etching the first spacer layer and the second spacer layer using the first etching process forms a third inner spacer portion and a fourth inner spacer portion, respectively, in the sidewall recess (Fig. 8, 170). Specifically, Wu teaches a method for fabricating a semiconductor device comprising indentations 150 (sidewall recess) formed within the stack 110 (Fig. 3; [0041]), hardened inner spacers 162-1 (first spacer layer) and 162-2 (second spacer layer) that fill said indentations (Fig. 7), and inner spacers 170 formed after an inner spacer etch (Fig. 8; [0047]). The term “inner spacers” is interpreted to mean the same as “third inner spacer portion” and “fourth inner spacer portion” as used in the claimed invention due to 1) said third and fourth portions retaining the same composition as the first and second spacer layers respectively, and 2) the structural similarities between Figures 7 and 8, where the inner spacers 170 of Figure 8 are clearly shown as comprising two portions that were previously labeled in Figure 7 as the hardened inner spacer layers 162-1 and 162-2 respectively. Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to modify the overall structure as taught in Reznicek according to the teachings of Wu, where two spacer layers are now deposited and etched to form inner spacer portions in order to improve the inner spacer quality and prevent source/drain epitaxial material etch out.
Regarding claim 19, Wu teaches wherein the first inner spacer portion and the third inner spacer portion are continuous (Fig. 7, 162-1). Specifically, Wu teaches a method for fabricating a semiconductor device comprising indentations 150 formed within the stack 110 (Fig. 3; [0041]) and a first hardened inner spacer 162-1 that fills said indentations and the underlying recess as one continuous layer (Fig. 7). Due to the similarities in placement, the “hardened inner spacer” is interpreted to comprise at least two portions, one towards the bottom of the recess and another located along the sidewall of the recess, that together make up a single continuous layer comprised of the same material throughout. Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to further modify the overall structure of Reznicek according to Wu, where the spacer portions are continuous so as to prevent source/drain epitaxial material etch out along additional areas throughout the overall structure.
Regarding claim 21, Wu teaches wherein the source/drain region contacts the substrate (Fig. 9, 180-1 & 180-2). Specifically, Wu teaches a method for fabricating a semiconductor device comprising source/drain regions 180-1 and 180-2 formed on the substrate 102 (Fig. 9; [0048]). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Reznicek and Wu, such that the source/drain region contacts the substrate in order to produce better heat dissipation and/or simplify the fabrication process.
Regarding claim 24, Reznicek teaches wherein the first recess extends into the substrate (Fig. 3B and [0061] point to the formation of recesses within the semiconductor material stack that extend into the substrate 100.).
Regarding claim 25, Kwon teaches wherein the second air gap extends below an upper surface of the substrate (Fig. 15A points to the air gaps AG (second air gap) extending below the upper surface(s) of the first region R1 of the substrate 100.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Reznicek et al. with those of Kwon, such that the air gap extends below an upper surface of the substrate in order further separate the overlying source/drain region from the underlying components.
Regarding claim 29, Kwon teaches wherein the second air gap contacts the substrate (Fig. 12A and [0039] point to an air gap AG located in a recess that extends below growth prevention regions 148, The growth prevention regions 148 may be portions of the substrate 100 ([0039]). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Reznicek et al. and Kwon, such that the second air gap contacts the substrate in order to improve physical stability and short-channel control.
Regarding claim 30, Reznicek teaches a method comprising: forming a nanostructure on a substrate, the nanostructure comprising a strip of alternating layers of a first semiconductor material and a second semiconductor material different from the first semiconductor material (Fig. 1, 120/130); forming a first gate structure on the nanostructure (Fig. 2, 210); recessing the nanostructure adjacent the first gate structure to form a first recess and a second recess in the nanostructures on opposing sides of the first gate structure (Figs. 3A-3B and [0061]); and forming a first bottom spacer along a bottommost surface of the first recess in a cross-sectional view (Fig. 4B, 410).
Reznicek fails to teach forming a second bottom spacer over the first bottommost spacer on the bottom of the first recess in the cross-sectional view; and forming a first source/drain region in the first recess and a second source/drain region in the second recess, wherein a first air gap is vertically between the source/drain region and the second bottom spacer along a line perpendicular to the bottommost surface of the first recess in the cross-sectional view, wherein the cross-sectional view extends through the first gate structure, the first source/drain region, and the second source/drain region.
Wu teaches forming a second bottom spacer over the first bottommost spacer on the bottom of the first recess in the cross-sectional view (Fig. 7, 162-1 & 162-2). Specifically, Wu teaches a method for fabricating a semiconductor device comprising a hardened inner spacer layer 162-1 (first bottom spacer) formed from inner spacer layer 160-1 (Fig. 5; [0044]), a second hardened inner spacer 162-2 (second bottom spacer) formed from inner spacer layer 160-2 (Fig. 7; [0046]), with both layers being shown as formed over the areas (first recess) previously created by a fin channel etch (Fig. 2; [0040]). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to modify the overall structure as taught in Reznicek according to the teachings of Wu, where a second bottom spacer is formed towards the bottom of the first recess so as to improve the inner spacer quality and further prevent source/drain epitaxial material etch out.
Reznicek et al. still fails to teach forming a first source/drain region in the first recess and a second source/drain region in the second recess, wherein a first air gap is vertically between the source/drain region and the second bottom spacer along a line perpendicular to the bottommost surface of the first recess in the cross-sectional view, wherein the cross-sectional view extends through the first gate structure, the first source/drain region, and the second source/drain region.
Kwon teaches forming a first source/drain region in the first recess and a second source/drain region in the second recess (Fig. 15A; SD), wherein a first air gap is vertically between the source/drain region and the second bottom spacer along a line perpendicular to the bottommost surface of the first recess in the cross-sectional view, wherein the cross-sectional view extends through the first gate structure, the first source/drain region, and the second source/drain region (Id.; AG (first air gap), SD (source/drain region), 148a (second bottom spacer)). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Reznicek et al. and Kwon, such that a first air gap and a second air gap are formed in order to provide an adequate degree of separation between the overlying source/drain region(s) and the underlying components which by extension would prevent any undue interference between each of the components.
Regarding claim 32, Wu teaches wherein the first inner spacer and the first bottom spacer are a first same material (Figs. 7-8, 162-1 & 170), wherein the second inner spacer and the second bottom spacer are a second same material (Figs. 7-8, 162-2 & 170). Specifically, Wu teaches a method for fabricating a semiconductor device comprising a hardened inner spacer layer 162-1 (first spacer layer) formed from inner spacer layer 160-1 (Fig. 5; [0044]), a second hardened inner spacer 162-2 (second spacer layer) formed from inner spacer layer 160-2 (Fig. 7; [0046]), and inner spacers 170 formed after an inner spacer etch (Fig. 8; [0047]). The term “inner spacers” is interpreted to mean the same as “first inner spacer” and “second inner spacer” as used in the claimed invention due to the similarities in location and structure, i.e., a dual-layer structure positioned on the sidewall of a stack of alternating layers. By extension, the term “inner spacers” is also interpreted to mean the same as “first bottom spacer” and “second bottom spacer” respectively, due to the structural similarities between Figures 7 and 8, where the inner spacers 170 of Figure 8 are clearly shown as comprising two portions that were previously labeled in Figure 7 as the hardened inner spacer layers 162-1 and 162-2 respectively. Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to modify the overall structure as taught in Reznicek according to the teachings of Wu, such that the spacers located towards the sidewall and the corresponding spacers located towards the bottom of the recess are comprised on the same respective materials in order to simplify the fabrication process and limit production costs.
Regarding claim 33, Wu teaches wherein the first inner spacer and the first bottom spacer are portions of a single layer (Fig. 7, 162-1). Specifically, Wu teaches a method for fabricating a semiconductor device comprising indentations 150 formed within the stack 110 (Fig. 3; [0041]) and a first hardened inner spacer 162-1 that fills said indentations and the underlying recess as one single layer (Fig. 7). The term “hardened inner spacer” is interpreted to mean the same as both “first inner spacer” and “first bottom spacer” as used in the claimed invention due to 1) the first bottom spacer having the same material composition as the first inner spacer as previously disclosed in claim 32 of the claimed invention, and 2) the obvious conclusion that if the “third inner spacer portion” remains a single layer with, and is of the same composition as, the “first inner spacer portion”, then one of ordinary skill in the art will conclude that they are the same layer. Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to further modify the overall structure of Reznicek et al. according to Wu, where the spacer portions are continuous so as to prevent source/drain epitaxial material etch out along additional areas throughout the overall structure.
Regarding claim 34, Kwon teaches wherein the first air gap extends lower than an upper surface of the substrate (Fig. 12A and [0039] point to an air gap AG located in a recess that extends below growth prevention regions 148, The growth prevention regions 148 may be portions of the substrate 100 ([0039]). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Reznicek et al. with those of Kwon, such that the air gap is positioned further down below the surface of the substrate in order provide adequate room for further steps during the fabrication process.
Claim(s) 20, 22-23, 26-28, and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Reznicek et al. in further view of Frougier (US Patent No. 10903317).
Regarding claim 20, Frougier teaches wherein forming the source/drain region forms a side air gap in the sidewall recess enclosed by the source/drain region and the third inner spacer portion (Fig. 3, 115 & 180). Specifically, Frougier teaches a gate-all-around field effect transistor (GAAFET) 100 comprising a source/drain region 115 located adjacent to the gate 164, and air-gaps 180 shown within the second spacer layer (third inner spacer portion) 142a (Fig. 3). It should, however, be understood that the figures disclosed in Frougier are not intended to be limiting and that other GAAFET embodiments are anticipated, given possible variations in the dimensions of the inner spacer cavities and/or possible variations in the thickness of the conformally deposited dielectric spacer material; for example, the GAAFET 100 could similarly include air-gaps in the second and third spacer layers 142a-142b; the second and third spacer layers 142a-142b could completely encapsulate the air-gaps 180 (as illustrated); the air-gaps 180 could physically separate the second and third spacer layers 142a-142b from the source/drain regions; etc. (Col. 11, line 62 – Col. 12, line 6). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to modify the overall structure as taught in Reznicek et al. according to the teachings of Frougier, such that a source/drain region is formed in the first recess to provide functionality to the overall structure, and an air gap is formed between the source/drain region and third inner spacer portion along the sidewall recess and/or towards the bottom of the first recess in order to reduce parasitic capacitance and improve the performance of the overall structure.
Regarding claim 22, Frougier teaches wherein the source/drain region contacts the first inner spacer portion (Fig. 3). Specifically, Frougier teaches a gate-all-around field effect transistor (GAAFET) 100 comprising a source/drain region 115 located adjacent to the gate 164, and air-gaps 180 shown within the second spacer layer (first inner spacer portion) 142a (Fig. 3). It should, however, be understood that the figures disclosed in Frougier are not intended to be limiting and that other GAAFET embodiments are anticipated, given possible variations in the dimensions of the inner spacer cavities and/or possible variations in the thickness of the conformally deposited dielectric spacer material; for example, the GAAFET 100 could similarly include air-gaps in the second and third spacer layers 142a-142b; the second and third spacer layers 142a-142b could completely encapsulate the air-gaps 180 (as illustrated); the air-gaps 180 could physically separate the second and third spacer layers 142a-142b from the source/drain regions; etc. (Col. 11, line 62 – Col. 12, line 6). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to modify the overall structure as taught in Reznicek et al. according to the teachings of Frougier, such that a source/drain region is formed in the first recess to provide functionality to the overall structure and is in direct contact with the first inner spacer portion so as to improve physical stability and short-channel control within the overall structure.
Regarding claim 23, Reznicek teaches forming a multi-layer stack on a substrate, the multi-layer stack comprising a strip of alternating layers of a first material and a second material different from the first material (Fig. 1, 120 & 130); forming a first gate structure on the multi-layer stack (Fig. 2, 210); recessing the multi-layer stack adjacent the first gate structure to form a first recess (Fig. 3B); recessing a sidewall of a first layer of the multi-layer stack in the first recess to form a second recess (Fig. 4B); and after recessing the sidewall of the first inner layer, forming a first inner spacer layer in the first recess (Fig. 4B, 410). Specifically, Reznicek teaches a semiconductor structure comprising a substrate 100, a semiconductor material stack (multi-layer stack) made up of alternating layers of semiconductor material layer 120 and semiconductor channel material layer 130, sacrificial gate structures 210 located on top of said stack (Fig 2; [0045] & [0053]), and a recess (first recess) within the semiconductor material stack adjacent to the gate structures 210 (Fig. 3B). Reznicek also teaches the recessing of sacrificial semiconductor material layer 120 (second recess) and formation of dielectric gate spacer material layer 410 (Fig. 4B; [0066]).
Reznicek fails to teach after forming the first inner spacer layer, forming a second inner spacer layer over the first inner spacer layer in the first recess; after forming the second inner spacer layer, etching the first inner spacer layer and the second inner spacer layer to form an inner spacer structure in the second recess, the inner spacer structure including a first inner spacer and a second inner spacer, the first inner spacer being between the second inner spacer and the first layer, remaining portions of the first inner spacer layer and the second inner spacer layer remaining along a bottommost surface of the first recess in a cross-sectional view; and after etching the first inner spacer layer and the second inner spacer layer, forming a source/drain region in the first recess and directly over the remaining portions of the first inner spacer layer and the second inner spacer layer, wherein a first air gap is laterally enclosed by the source/drain region and the inner spacer structure, and wherein a second air gap is vertically enclosed by the source/drain region and the remaining portions of the first inner spacer layer and the second inner spacer layer along the bottommost surface of the first recess in the cross-sectional view, wherein the cross-sectional view extends through the source/drain region in a direction perpendicular to a longitudinal axis of the first gate structure.
Wu teaches after forming the first inner spacer layer, forming a second inner spacer layer over the first inner spacer layer in the first recess (Fig. 6, 162-1 & 162-2); and after forming the second inner spacer layer, etching the first inner spacer layer and the second inner spacer layer to form an inner spacer structure in the second recess, the inner spacer structure including a first inner spacer and a second inner spacer, the first inner spacer being between the second inner spacer and the first layer (Fig. 8, 170). Specifically, Wu teaches a method for fabricating a semiconductor device comprising a hardened inner spacer layer 162-1 (first spacer layer) formed from inner spacer layer 160-1 (Fig. 5; [0044]), a second hardened inner spacer 162-2 (second spacer layer) formed from inner spacer layer 160-2 (Fig. 7; [0046]), and inner spacers 170 formed after an inner spacer etch (Fig. 8; [0047]). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to modify the overall structure as taught in Reznicek according to the teachings of Wu, where two spacer layers are now deposited and etched to form inner spacer portions in order to improve the inner spacer quality and prevent source/drain epitaxial material etch out.
Reznicek et al. still fails to teach remaining portions of the first inner spacer layer and the second inner spacer layer remaining along a bottommost surface of the first recess in a cross-sectional view; and after etching the first inner spacer layer and the second inner spacer layer, forming a source/drain region in the first recess and directly over the remaining portions of the first inner spacer layer and the second inner spacer layer, wherein a first air gap is laterally enclosed by the source/drain region and the inner spacer structure, and wherein a second air gap is vertically enclosed by the source/drain region and the remaining portions of the first inner spacer layer and the second inner spacer layer along the bottommost surface of the first recess in the cross-sectional view, wherein the cross-sectional view extends through the source/drain region in a direction perpendicular to a longitudinal axis of the first gate structure.
Kwon teaches remaining portions of the first inner spacer layer and the second inner spacer layer remaining along a bottommost surface of the first recess in a cross-sectional view (Fig. 15A and [0075]; 148a); and after etching the first inner spacer layer and the second inner spacer layer, forming a source/drain region in the first recess and directly over the remaining portions of the first inner spacer layer and the second inner spacer layer (Id.; SD), and wherein a second air gap is vertically enclosed by the source/drain region and the remaining portions of the first inner spacer layer and the second inner spacer layer along the bottommost surface of the first recess in the cross-sectional view, wherein the cross-sectional view extends through the source/drain region in a direction perpendicular to a longitudinal axis of the first gate structure (Id.; AG (second air gap)). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Reznicek et al. and Kwon, such that a first air gap is formed in order to provide an adequate degree of separation between the overlying source/drain region(s) and the underlying components which by extension would prevent any undue interference between each of the components.
Reznicek et al. still fails to teach wherein a first air gap is laterally enclosed by the source/drain region and the inner spacer structure.
Frougier teaches wherein a first air gap is laterally enclosed by the source/drain region and the inner spacer structure (Fig. 3 points to the source/drain regions 115, spacer layers 142 (inner spacer structure), and air-gaps 180 (first air gap). Col. 11, line 62 – Col. 12, line 6 further points to possible variations in the dimensions where, for example, the air-gaps 180 physically separate the spacer layers 142 from the source/drain regions 115.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to modify the overall structure as taught in Reznicek et al. according to the teachings of Frougier, such that a source/drain region is formed in the first recess to provide functionality to the overall structure, and air gaps are formed along the side and bottom of the source/drain region in order to reduce parasitic capacitance and improve the performance of the overall structure.
Regarding claim 26, Frougier teaches wherein the source/drain region contacts the remaining portions of the first inner spacer layer (Fig. 3). Specifically, Frougier teaches a gate-all-around field effect transistor (GAAFET) 100 comprising a source/drain region 115 located adjacent to the gate 164, and air-gaps 180 shown within the first and second inner spacers 121 and 122, specifically within second spacer layer 142a (first inner spacer layer) (Id.). It should, however, be understood that the figures disclosed in Frougier are not intended to be limiting and that other GAAFET embodiments are anticipated, given possible variations in the dimensions of the inner spacer cavities and/or possible variations in the thickness of the conformally deposited dielectric spacer material; for example, the GAAFET 100 could similarly include air-gaps in the second and third spacer layers 142a-142b (Col. 11, lines 62-67). The second and third spacer layers 142a-142b could completely encapsulate the air-gaps 180 (as illustrated); the air-gaps 180 could physically separate the second and third spacer layers 142a-142b from the source/drain regions; etc. (Col. 11, line 67 – Col. 12, line 6). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to modify the overall structure as taught in Reznicek et al. according to the teachings of Frougier, such that the source/drain region is in direct contact with the first inner spacer layer towards the bottom of the recess so as to improve physical stability and short-channel control within the overall structure.
Regarding claim 27, Frougier teaches wherein the source/drain region contacts the remaining portions of the second inner spacer layer (Fig. 3). Specifically, Frougier teaches a gate-all-around field effect transistor (GAAFET) 100 comprising a source/drain region 115 located adjacent to the gate 164, and air-gaps 180 shown within the first and second inner spacers 121 and 122, specifically within third spacer layer 142b (second inner spacer layer) (Id.). It should, however, be understood that the figures disclosed in Frougier are not intended to be limiting and that other GAAFET embodiments are anticipated, given possible variations in the dimensions of the inner spacer cavities and/or possible variations in the thickness of the conformally deposited dielectric spacer material; for example, the GAAFET 100 could similarly include air-gaps in the second and third spacer layers 142a-142b (Col. 11, lines 62-67). The second and third spacer layers 142a-142b could completely encapsulate the air-gaps 180 (as illustrated); the air-gaps 180 could physically separate the second and third spacer layers 142a-142b from the source/drain regions; etc. (Col. 11, line 67 – Col. 12, line 6). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to modify the overall structure as taught in Reznicek et al. according to the teachings of Frougier, such that the source/drain region is in direct contact with the second inner spacer layer towards the bottom of the recess so as to improve physical stability and short-channel control within the overall structure.
Regarding claim 28, Frougier teaches wherein the source/drain region is free from direct contact with the second inner spacer (Fig. 3). Specifically, Frougier teaches a gate-all-around field effect transistor (GAAFET) 100 comprising a source/drain region 115 located adjacent to the gate 164, and air-gaps 180 shown within the first and second inner spacers 121 and 122, specifically within third spacer layer 142b (second inner spacer) (Id.). It should, however, be understood that the figures disclosed in Frougier are not intended to be limiting and that other GAAFET embodiments are anticipated, given possible variations in the dimensions of the inner spacer cavities and/or possible variations in the thickness of the conformally deposited dielectric spacer material; for example, the GAAFET 100 could similarly include air-gaps in the second and third spacer layers 142a-142b (Col. 11, lines 62-67). The second and third spacer layers 142a-142b could completely encapsulate the air-gaps 180 (as illustrated); the air-gaps 180 could physically separate the second and third spacer layers 142a-142b from the source/drain regions; etc. (Col. 11, line 67 – Col. 12, line 6). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to modify the overall structure as taught in Reznicek et al. according to the teachings of Frougier, such that the source/drain region is in direct contact with the second inner spacer along the sidewall of the recess so as to improve physical stability and short-channel control within the overall structure.
Regarding claim 31, Reznicek teaches recessing sidewalls of a first layer of the alternating layers (Fig. 4B); and forming a first inner spacer on the sidewall of the first layer (Id.). Specifically, Reznicek teaches a semiconductor structure comprising the formation of a semiconductor material stack made up of alternating layers of semiconductor material layer 120 and semiconductor channel material layer 130, the recessing of sacrificial semiconductor material layer 120 (sidewall(s)) and the formation of dielectric gate spacer material layer 410 (first inner spacer) (Fig. 4B; [0066]). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to further modify the overall structure of Reznicek et al. according to the teachings of Reznicek, such that a sidewall is recessed and a first inner spacer is formed on said sidewall so as to prevent source/drain epitaxial material etch out.
Reznicek fails to teach forming a second inner spacer on the first inner spacer, wherein a second air gap is between the first source/drain region and the second inner spacer.
Wu teaches forming a second inner spacer on the first inner spacer (Fig. 7, 162-2). Specifically, Wu teaches a method for fabricating a semiconductor device comprising indentations 150 formed within the stack 110 (Fig. 3; [0041]),and hardened inner spacers 162-1 (first inner spacer) and 162-2 (second inner spacer) that fill said indentations (Fig. 7). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to modify the overall structure as taught in Reznicek according to the teachings of Wu, where a second inner spacer is now also deposited in order to improve the inner spacer quality and prevent source/drain epitaxial material etch out.
Reznicek et al. still fails to teach wherein a second air gap is between the first source/drain region and the second inner spacer.
Frougier teaches wherein a second air gap is between the first source/drain region and the second inner spacer (Fig. 3). Specifically, Frougier teaches a gate-all-around field effect transistor (GAAFET) 100 comprising a source/drain region 115 located adjacent to the gate 164, and air-gaps 180 shown within the first and second inner spacers 121 and 122, specifically within second spacer layer 142b (second inner spacer) (Id.). It should, however, be understood that the figures disclosed in Frougier are not intended to be limiting and that other GAAFET embodiments are anticipated, given possible variations in the dimensions of the inner spacer cavities and/or possible variations in the thickness of the conformally deposited dielectric spacer material; for example, the GAAFET 100 could similarly include air-gaps in the second and third spacer layers 142a-142b; the second and third spacer layers 142a-142b could completely encapsulate the air-gaps 180 (as illustrated); the air-gaps 180 could physically separate the second and third spacer layers 142a-142b from the source/drain regions; etc. (Col. 11, line 62 – Col. 12, line 6). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to modify the overall structure as taught in Reznicek et al. according to the teachings of Frougier, such that a second air gap is formed between the source/drain region and the second inner spacer in order to reduce parasitic capacitance and improve the performance of the overall structure.
Response to Arguments
Applicant’s arguments, see Remarks, filed 01/12/2026, with respect to the rejection(s) of amended claim(s) 15, 23, 25, 30, and 31 (and by extension any and all dependent claims) under 35 U.S.C. §103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Reznicek (PGPub No. 20210193829) in further view of Wu (PGPub No. 20200287021) and Kwon (PGPub No. 20180301564).
Conclusion
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/PATRICK CULLEN/Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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