DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on September 12, 2025 has been entered.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “the bottom width of the bottom part is equal to the top width of the upper part” (claims 1 and 18; note: “at least equal to” means greater than or equal to) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to because the shading of “FN” as shown in Fig. 2A is inconsistent with the shading of “FN” as shown in Figs. 2B and 2C. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 and 11-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the protruding channel" in last line. There is insufficient antecedent basis for this limitation in the claim. Also, it is unclear as to whether said limitation is the same as or different from “a s protruding channel structure”, as recited in claim 1, line 7.
The term "slightly" in claim 5 is a relative term which renders the claim indefinite. The term "slightly" is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
Claim 6 recites the limitation "the top and bottom widths of the bottom part" in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. Also, it is unclear as to whether said limitation is the same as or different from “a top width” and/or “a bottom width”, as recited in claim 1.
Claim 11 recites the limitation "the second protruding channel" in line 12. There is insufficient antecedent basis for this limitation in the claim. Also, it is unclear as to whether said limitation is the same as or different from “a second protruding channel structure”, as recited in claim 11, lines 9-10 and 19-20.
Claim 11 recites the limitation "the upper parts" in line 19. There is insufficient antecedent basis for this limitation in the claim. Also, it is unclear as to whether said limitation is the same as or different from “an upper part”, as recited in claim 11, line 13.
The claimed limitation of "the upper parts of the first protruding channel structure and the second protruding channel", as recited in claim 11, is unclear as to the upper part(s) of which element applicant refers.
The claimed limitation of "the at least one barrier layer", as recited in claim 14, is unclear as to the at least one barrier layer of which element applicant refers.
The claimed limitation of "… thickness between the top surface of the gate conductor and the at least one barrier layer", as recited in claim 17, is unclear as to … thickness between the top surface of the gate conductor and at which level of the at least one barrier layer applicant referrers.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-9 and 11-13 and 18-20, as best understood, is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (2014/0327087) in view of Huang et al. (2019/0252549).
As for claims 1-7, 11, 18-20, Kim et al. show in Figs. 2A (B-B’ for 11a structure), 2B (D-D’ for 11b and 11c structures), 7, 9B, 9C and related text a memory device, comprising:
an array of memory cells CAR, each comprising an access transistor CTR and a storage capacitor coupled to the access transistor ([0090]), wherein the access transistor comprises a trench gate structure 9a/11a buried in a semiconductor substrate 1; and
a peripheral circuit TR1/TR2, disposed around the array of memory cells, and comprising:
a (three-dimensional) first transistor TR1, formed on the semiconductor substrate, and comprising a first protruding channel structure AR2 having a first conductive type N and a first gate structure 11b covering the first protruding channel structure (Figs. 7; 2B: D-D’; 9B); and
a second transistor TR2, formed on the semiconductor substrate, and comprising a second protruding channel structure AR2 having a second conductive type P and a second gate structure 11c covering the second protruding channel structure (Figs. 7; 2B: D-D’; 9C),
wherein each of the first protruding channel structure and the second protruding channel has a bottom part and an upper part;
wherein each of the first gate structure and the second gate structure comprises a gate conductor 32 and a gate dielectric layer 9b/9c lining along a bottom side of the gate conductor, wherein the second gate structure further comprises a work function layer 36 extending in between the gate conductor and the gate dielectric layer (Figs. 7, 9B and 9C);
wherein only the upper parts of the first protruding channel structure and the second protruding channel are surrounded by the gate conductor and the gate dielectric layer (Figs. 2B: D-D’, 9B and 9C);
wherein only the upper part of the second protruding channel is surrounded by the work function layer (Figs. 2B: D-D’ and 9C); and
wherein (the) a bottom width of the bottom part is at least equal to the top width of the upper part (Figs. 2B: D-D’).
Kim et al. do not disclose the upper part has a top width and a bottom width smaller than the top width; the bottom part of the protruding channel structure has a top width and a bottom width which is equal to the top width of the bottom part; the upper part of the protruding channel structure has a top wall and two sidewalls downwardly extended from two ends of the top wall respectively, the two sidewalls of the upper part of the protruding channel are curved walls (claim 1); a lateral recess is defined at a bottom of the upper part of the protruding channel structure (claim 2); the gate structure further extends into the lateral recess (claim 3); the lateral recess is defined by one of the two sidewalls of the upper part and a top surface of an edge region of the bottom part (claim 4); top and bottom widths of the bottom part are each identical with or greater than the top width of the upper part (claim 6); the upper part of the protruding channel structure tapers downwardly (claim 7); the upper part has a top width and a bottom width smaller than the top width (claim 11); a lateral recess is defined at a bottom of the upper part of each of the first protruding channel structure and the second protruding channel structure (claim 19); and the first gate structure and the second gate structure further extend into the lateral recess of the first protruding channel structure and the lateral recess of the second protruding channel structure respectively (claim 20).
Huang et al. teach in Figs. 1, 2A-2B and related text:
As for claim 1, the upper part has a top width W1 and a bottom width W2 smaller than the top width;
wherein the bottom part of the protruding channel structure has a top width and a bottom width which is equal to the top width of the bottom part;
wherein the upper part 130 of the protruding channel structure 130/(upper portion of) 100 has a top wall 130a and two sidewalls 130b downwardly extended from two ends of the top wall respectively, wherein the two sidewalls of the upper part of the protruding channel are curved walls.
As for claims 2 and 19, a lateral recess 131 is defined at a bottom of the upper part of each of the first protruding channel structure and the second protruding channel structure (Fig. 2A).
As for claims 3 and 20, the gate structure 220/400 further extends into the lateral recess (Fig. 2A).
As for claim 4, the lateral recess is defined by one of the two sidewalls of the upper part and a top surface of an edge region of the bottom part (Fig. 2A).
As for claim 6, the top and bottom widths of the bottom part are each identical with or greater than the top width of the upper part (Fig. 2A).
As for claim 7, the upper part of the protruding channel structure tapers downwardly (Fig. 2A).
Kim et al. and Huang et al. are analogous art because they are directed to a DRAM semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim et al. with the specified feature(s) of Huang et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to include the upper part having a top width and a bottom width smaller than the top width, the bottom part of the protruding channel structure having a top width and a bottom width which being equal to the top width of the bottom part, the upper part of the protruding channel structure having a top wall and two sidewalls downwardly extended from two ends of the top wall respectively, the two sidewalls of the upper part of the protruding channel being curved walls; a lateral recess being defined at a bottom of the upper part of the protruding channel structure; the gate structure further extending into the lateral recess; the lateral recess being defined by one of the two sidewalls of the upper part and a top surface of an edge region of the bottom part; the top and bottom widths of the bottom part being greater than the top width of the upper part; the upper part of the protruding channel structure tapering downwardly; the upper part having a top width and a bottom width smaller than the top width, as taught by Huang et al., in each peripheral transistor of Kim et al.'s device, in order to increase driving current of the transistor, reduce short-channel effects, enhance channel control reduce leakage current and improve performance.
Therefore, the combined device shows:
As for claim 19, a lateral recess is defined at a bottom of the upper part of each of the first protruding channel structure and the second protruding channel structure.
As for claim 20, the first gate structure and the second gate structure further extend into the lateral recess of the first protruding channel structure and the lateral recess of the second protruding channel structure respectively.
As for claim 5, the combined device shows the bottom width of the bottom part is slightly greater than the top width of the upper part (Kim: Fig. 2B: D-D’).
As for claim 8, the combined device shows the bottom part of the protruding channel structure is laterally surrounded by an isolation structure 3c, while the upper part of the protruding channel structure is protruded with respect to the isolation structure (Kim: Fig. 2B: D-D’).
As for claim 9, the combined device shows the protruding channel structure is a surface portion of the semiconductor substrate (Kim: Fig. 2B: D-D’).
As for claim 12, the combined device shows the work function layer is absent in the first transistor (Kim: Fig. 9B).
As for claim 13, the combined device shows each of the first gate structure and the second gate structure further comprises at least one barrier layer 30 extending in between the gate conductor and the gate dielectric layer (Kim: Figs. 9B-9C).
Claim(s) 14-17, as best understood, is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (2014/0327087, hereinafter Kim’087) and Huang et al. (2019/0252549) in view of Kim et al. (2015/0014780, hereinafter Kim’780).
As for claims 14-17, Kim’087 and Huang et al. disclosed substantially the entire claimed invention, as applied to claim 13 above, including the at least one barrier layer comprises a first barrier layer (claim 14), wherein the first barrier layer in the second gate structure extends between the work function layer and the gate dielectric layer (claim 15) (Figs. 9B-9C).
Kim’087 and Huang et al. do not disclose the at least one barrier layer comprises a second barrier layer formed of different conductive materials (claim 14); the second barrier layer in the second gate structure extends between the gate conductor and the work function layer (claim 15); a top surface of the gate conductor in the first gate structure is leveled with a top surface of the gate conductor in the second gate structure (claim 16); and the gate conductor in the first gate structure has a first thickness between the top surface of the gate conductor and the at least one barrier layer; the gate conductor in the second gate structure has a second thickness between the top surface of the gate conductor and the at least one barrier layer; the first thickness is greater than the second thickness; and a difference between the first thickness and the second thickness is equal to a thickness of the work function layer (claim 17).
Lee et al. teach in Fig. 1S and related text:
As for claim 14, the at least one barrier layer 124/224 comprises a first barrier layer (lower portion of) 124/224 and a second barrier layer (upper portion of) 124/224 formed of different conductive materials ([0091]).
As for claim 15, the second barrier layer in the second gate structure extends between the gate conductor and the work function layer (Fig. 7).
As for claim 16, a top surface of the gate conductor in the first gate structure is leveled with a top surface of the gate conductor in the second gate structure (fig. 7).
As for claim 17, the gate conductor in the first gate structure has a first thickness between the top surface of the gate conductor and the at least one barrier layer;
wherein the gate conductor in the second gate structure has a second thickness between the top surface of the gate conductor and the at least one barrier layer;
wherein the first thickness is greater than the second thickness; and
wherein a difference between the first thickness and the second thickness is equal to a thickness of the work function layer (Fig. 7).
Kim’087, Huang et al. and Kim’780 are analogous art because they are directed to a finFET and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim’087 and Huang et al. with the specified feature(s) of Kim’780 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to include the at least one barrier layer comprising a first barrier layer and a second barrier layer formed of different conductive materials; the second barrier layer in the second gate structure extending between the gate conductor and the work function layer; a top surface of the gate conductor in the first gate structure being leveled with a top surface of the gate conductor in the second gate structure; and the gate conductor in the first gate structure having a first thickness between the top surface of the gate conductor and the at least one barrier layer; the gate conductor in the second gate structure having a second thickness between the top surface of the gate conductor and the at least one barrier layer; the first thickness is greater than the second thickness; and a difference between the first thickness and the second thickness being equal to a thickness of the work function layer, as taught by Kim’780, in Kim’087 and Huang et al., in order to reduce threshold voltage and improve the performance, density and scalability of the device.
Response to Arguments
Applicant’s arguments with respect to claim(s) 11-13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Rest of applicant's arguments filed September 12, 2025 have been fully considered but they are not persuasive.
Applicant argues that Kim fails to teach that “the bottom width of the channel part is at least equal to the top width of the upper part”, as disclosed at least in Para [0039] and Figs. 2A-2C of the instant invention.
The examiner respectfully disagrees because based on Cambridge Dictionary, the term “at least” means “as much as, or more than”. Accordingly, the phrase “at least equal to” interpreted as “greater than or equal to”.
Therefore, Kim clearly teaches in Fig. 2B the limitation of “the bottom width of the channel part is at least equal to (i.e. greater than) the top width of the upper part”, as recited in claim 1.
Conclusion
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/MEIYA LI/Primary Examiner, Art Unit 2811
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