DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings were received on January 12, 2026. These drawings are acceptable.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “the bottom width of the bottom part is equal to the top width of the upper part” (claims 1 and 18; note: “at least equal to” means greater than or equal to) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9, 14 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the sidewalls" in line 20. There is insufficient antecedent basis for this limitation in the claim. Also, it is unclear as to whether said limitation is the same as or different from “two sidewalls”, as recited in claim 1, line 16.
Claims 14 and 17 recite the limitation "the barrier layer" in lines 2 and 3, respectively. There is insufficient antecedent basis for this limitation in the claim. Also, it is unclear as to whether said limitation is the same as or different from “at least one barrier layer”, as recited in claim 13.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-9, 11, 13 and 18-20, as best understood, is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (2014/0327087) in view of Huang et al. (2019/0252549).
Kim et al. show in Figs. 2A (B-B’ for 11a structure), 2B (D-D’ for 11b and 11c structures), 7, 9B, 9C and related text:
As for claims 1-4, 6 and 7, a memory device, comprising:
an array of memory cells CAR, each comprising an access transistor CTR and a storage capacitor coupled to the access transistor ([0090]), wherein the access transistor comprises a trench gate structure 9a/11a buried in a semiconductor substrate 1;
a peripheral circuit TR1/TR2, disposed around the array of memory cells, and comprising:
a three-dimensional transistor TR1, formed on the semiconductor substrate, and comprising a protruding channel structure AR2 and a gate structure 11b covering the protruding channel structure, wherein the protruding channel structure has a bottom part and an upper part (Figs. 7; 2B: D-D’; 9B); and
an isolation structure 3a/3b/3c disposed on the semiconductor substrate, wherein the bottom part of the protruding channel structure is surrounded by the isolation structure;
wherein the bottom part of the protruding channel structure has a top width and a bottom width;
wherein the bottom width of the bottom part is at least equal to the top width of the upper part (Figs. 2B: D-D’);
wherein the gate structure comprises:
a gate dielectric layer 9b in contact with the isolation structure, the sidewalls of the upper part of the protruding channel structure, and the top wall of the upper part of the protruding channel structure (Fig. 2B: D-D’);
a barrier layer 30 disposed on and in contact with the gate dielectric layer (Fig. 7; combined Figs. 9B with 2B: D-D’); and
a gate conductor 32 disposed over the barrier layer, wherein the upper part of the protruding channel structure is surrounded by the gate dielectric layer, the barrier layer, and the gate conductor (Fig. 7; combined Figs. 9B with 2B: D-D’).
As for claims 11, 19 and 20, a memory device, comprising:
an array of memory cells CAR, each comprising an access transistor CTR and a storage capacitor coupled to the access transistor ([0090]), wherein the access transistor comprises a trench gate structure 9a/11a buried in a semiconductor substrate 1; and
a peripheral circuit TR1/TR2, disposed around the array of memory cells, and comprising:
a first transistor TR1, formed on the semiconductor substrate, and comprising a first protruding channel structure AR2 having a first conductive type N and a first gate structure 11b covering the first protruding channel structure (Figs. 7; 2B: D-D’; 9B);
a second transistor TR2, formed on the semiconductor substrate, and comprising a second protruding channel structure AR2 having a second conductive type P and a second gate structure 11c covering the second protruding channel structure (Figs. 7; 2B: D-D’; 9C), and
an isolation structure 3a/3b/3c disposed on the semiconductor substrate;
wherein each of the first protruding channel structure and the second protruding channel structure has a bottom part and an upper part, wherein the upper part has a top width and a bottom width;
wherein each of the first gate structure and the second gate structure comprises a gate conductor 32 and a gate dielectric layer 9b/9c lining along a bottom side of the gate conductor, wherein the second gate structure further comprises a work function layer 36 extending in between the gate conductor and the gate dielectric layer (Figs. 7, 9B and 9C);
wherein only the upper part of the first protruding channel structure and the upper part the second protruding channel are surrounded by the gate conductor and the gate dielectric layer while the bottom part of the first protruding channel structure and the bottom part of the second protruding channel structure are surrounded by the isolation structure (Figs. 2B: D-D’ combined with 9B and 9C; Fig. 7);
wherein only the upper part of the second protruding channel is surrounded by the work function layer while the first protruding channel does not have the work function layer (Figs. 2B: D-D’ combined with 9B and 9C; Fig. 7).
Kim et al. do not disclose the bottom width (of the upper part) smaller than the top width; the bottom width (of the bottom part) which is equal to the top width of the bottom part; the upper part of the protruding channel structure has a top wall and two sidewalls downwardly extended from two ends of the top wall respectively, the two sidewalls of the upper part of the protruding channel structure are curved walls (claim 1); a lateral recess is defined at a bottom of the upper part of the protruding channel structure (claim 2); the gate structure further extends into the lateral recess (claim 3); the lateral recess is defined by one of the two sidewalls of the upper part and a top surface of an edge region of the bottom part (claim 4); the top width and the bottom width of the bottom part are greater than the top width of the upper part (claim 6); the upper part of the protruding channel structure tapers downwardly (claim 7); the upper part has a top width and a bottom width smaller than the top width (claim 11); a lateral recess is defined at a bottom of the upper part of each of the first protruding channel structure and the second protruding channel structure (claim 19); and the first gate structure and the second gate structure further extend into the lateral recess of the first protruding channel structure and the lateral recess of the second protruding channel structure respectively (claim 20).
Huang et al. teach in Figs. 1, 2A-2B and related text:
As for claim 1, the upper part has a top width W1 and a bottom width W2 smaller than the top width;
wherein the bottom part of the protruding channel structure has a top width and a bottom width which is equal to the top width of the bottom part;
wherein the upper part 130 of the protruding channel structure 130/(upper portion of) 100 has a top wall 130a and two sidewalls 130b downwardly extended from two ends of the top wall respectively, wherein the two sidewalls of the upper part of the protruding channel are curved walls.
As for claims 2 and 19, a lateral recess 131 is defined at a bottom of the upper part of each of the first protruding channel structure and the second protruding channel structure (Fig. 2A).
As for claims 3 and 20, the gate structure 220/400 further extends into the lateral recess (Fig. 2A).
As for claim 4, the lateral recess is defined by one of the two sidewalls of the upper part and a top surface of an edge region of the bottom part (Fig. 2A).
As for claim 6, the top width and the bottom width of the bottom part are greater than the top width of the upper part (Fig. 2A).
As for claim 7, the upper part of the protruding channel structure tapers downwardly (Fig. 2A).
Kim et al. and Huang et al. are analogous art because they are directed to a DRAM semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim et al. with the specified feature(s) of Huang et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to include the upper part having a top width and a bottom width smaller than the top width, the bottom part of the protruding channel structure having a top width and a bottom width which being equal to the top width of the bottom part, the upper part of the protruding channel structure having a top wall and two sidewalls downwardly extended from two ends of the top wall respectively, the two sidewalls of the upper part of the protruding channel being curved walls; a lateral recess being defined at a bottom of the upper part of the protruding channel structure; the gate structure further extending into the lateral recess; the lateral recess being defined by one of the two sidewalls of the upper part and a top surface of an edge region of the bottom part; the top and bottom widths of the bottom part being greater than the top width of the upper part; the upper part of the protruding channel structure tapering downwardly; the upper part having a top width and a bottom width smaller than the top width, as taught by Huang et al., in each peripheral transistor of Kim et al.'s device, in order to increase driving current of the transistor, reduce short-channel effects, enhance channel control reduce leakage current and improve performance.
Therefore, the combined device shows:
As for claim 19, a lateral recess is defined at a bottom of the upper part of each of the first protruding channel structure and the second protruding channel structure.
As for claim 20, the first gate structure and the second gate structure further extend into the lateral recess of the first protruding channel structure and the lateral recess of the second protruding channel structure respectively.
As for claim 5, the combined device shows the bottom width of the bottom part is greater than the top width of the upper part (Kim: Fig. 2B: D-D’).
As for claim 8, the combined device shows the upper part of the protruding channel structure is protruded with respect to the isolation structure, wherein the gate structure further comprises a work function layer 34 (or 36) disposed on and in contact between the barrier layer and the gate conductor (Kim: Fig. 2B: D-D’ combined with Fig. 9B (or 9C)).
As for claim 9, the combined device shows the protruding channel structure is a surface portion of the semiconductor substrate (Kim: Fig. 2B: D-D’).
As for claim 13, the combined device shows each of the first gate structure and the second gate structure further comprises at least one barrier layer 30 extending in between the gate conductor and the gate dielectric layer (Kim: Figs. 9B-9C).
As for claim 18, the combined device shows a bottom width of the bottom part is at least equal to the top width of the upper part (Kim: Figs. 2B: D-D’).
Claim(s) 12 and 14-17, as best understood, is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (2014/0327087, hereinafter Kim’087) and Huang et al. (2019/0252549) in view of Kim et al. (2015/0014780, hereinafter Kim’780).
As for claims 12 and 14-17, Kim’087 and Huang et al. disclosed substantially the entire claimed invention, as applied to claims 11 above, including the work function layer is absent in the first transistor (claim 12); the at least one barrier layer comprises a first barrier layer (claim 14), wherein the first barrier layer in the second gate structure extends between the work function layer and the gate dielectric layer (claim 15) (Figs. 9B-9C).
Kim’087 and Huang et al. do not disclose the work function layer is formed of titanium carbide, tantalum carbide, or titanium-tantalum carbide (claim 12); the at least one barrier layer comprises a second barrier layer formed of different conductive materials (claim 14); the second barrier layer in the second gate structure extends between the gate conductor and the work function layer (claim 15); a top surface of the gate conductor in the first gate structure is leveled with a top surface of the gate conductor in the second gate structure (claim 16); and the gate conductor in the first gate structure has a first thickness between the top surface of the gate conductor and the at least one barrier layer; the gate conductor in the second gate structure has a second thickness between the top surface of the gate conductor and the at least one barrier layer; the first thickness is greater than the second thickness; and a difference between the first thickness and the second thickness is equal to a thickness of the work function layer (claim 17).
Lee et al. teach in Figs. 6-8 and related text:
As for claim 12, the work function layer 122is formed of titanium carbide, tantalum carbide, or titanium-tantalum carbide ([0019]).
As for claim 14, the at least one barrier layer 124/224 comprises a first barrier layer (lower portion of) 124/224 and a second barrier layer (upper portion of) 124/224 formed of different conductive materials ([0091]).
As for claim 15, the second barrier layer in the second gate structure extends between the gate conductor and the work function layer (Fig. 7).
As for claim 16, a top surface of the gate conductor in the first gate structure is leveled with a top surface of the gate conductor in the second gate structure (fig. 7).
As for claim 17, the gate conductor in the first gate structure has a first thickness between the top surface of the gate conductor and the at least one barrier layer;
wherein the gate conductor in the second gate structure has a second thickness between the top surface of the gate conductor and the at least one barrier layer;
wherein the first thickness is greater than the second thickness; and
wherein a difference between the first thickness and the second thickness is equal to a thickness of the work function layer (Fig. 7).
Kim’087, Huang et al. and Kim’780 are analogous art because they are directed to a finFET and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim’087 and Huang et al. with the specified feature(s) of Kim’780 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to use titanium carbide, tantalum carbide, or titanium-tantalum carbide, as the work function layer, to include the at least one barrier layer comprising a first barrier layer and a second barrier layer formed of different conductive materials; the second barrier layer in the second gate structure extending between the gate conductor and the work function layer; a top surface of the gate conductor in the first gate structure being leveled with a top surface of the gate conductor in the second gate structure; and the gate conductor in the first gate structure having a first thickness between the top surface of the gate conductor and the at least one barrier layer; the gate conductor in the second gate structure having a second thickness between the top surface of the gate conductor and the at least one barrier layer; the first thickness is greater than the second thickness; and a difference between the first thickness and the second thickness being equal to a thickness of the work function layer, as taught by Kim’780, in Kim’087 and Huang et al., in order to reduce threshold voltage and improve the performance, density and scalability of the device.
Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Response to Arguments
Applicant's arguments filed January 12, 2026 have been fully considered but they are not persuasive.
Applicant argues that “regarding the amended claims 1 and 11, Kim fails to teach "any isolation structure 212 disposed on the semiconductor substrate, wherein the bottom part of the protruding channel structure is surrounded by the isolation structure", as disclosed in paragraph [0032] and FIGS. 2A to 2C of the present application” because “at least the peripheral gate insulating layer 9b and 9c as taught by Kim do not have any bottom part surrounded by any isolation structure. Huang only discloses one single protrusion structure 130”.
The examiner respectfully disagrees because Lee clearly shows in Fig. 2B (D-D’) the limitation of “the bottom part of the protruding channel structure is surrounded by the isolation structure”, as recited in amended claims 1 and 11.
Applicant argues that regarding the amended claims 1 and 18, Kim fails to teach that “the bottom width W4 of the bottom part is at least equal to the top width W1 of the upper part”, as disclosed at least in Para [0039] and Figs. 2A-2C of the instant invention”.
The examiner respectfully disagrees because based on Cambridge Dictionary, the term “at least” means “as much as, or more than”. Accordingly, the phrase “at least equal to” interpreted as “greater than or equal to”.
Therefore, Kim clearly teaches in Fig. 2B the limitation of “the bottom width of the bottom part is at least equal to (i.e. greater than) the top width of the upper part”, as recited in the amended claims 1 and 18.
Applicant argues that “the combined structure of Kim and Huang will fail to teach that "the upper part of the protruding channel structure is surrounded by the gate dielectric layer, the barrier layer, and the gate conductor" while "the bottom part of the protruding channel structure is surrounded by the isolation structure", as claimed in the present application” because “Kim never disclosed that the upper portion of the peripheral gate insulating layer 9b is surrounded by the first metal-containing layer 30, the second metal-containing layer 32 and the third metal-containing layer 34 while the bottom portion of the peripheral gate insulating layer 9b is surrounded by any isolation structure”.
The examiner respectfully disagrees because when taking along lines D-D’ of Fig. 7 (similar to Fig. 1), a sectional view along lines D-D’ of Fig. 7 will have a similar structure as shown in Fig. 2D, except 11b has a stack structure.
Therefore, Kim implicitly discloses that “the upper part of the protruding channel structure is surrounded by the gate dielectric layer, the barrier layer, and the gate conductor”, while “the bottom part of the protruding channel structure is surrounded by the isolation structure, as claimed in the present application.
Applicant argues that “regarding the amended claims 8 and 11, Kim fails to teach "any work function layer 224 disposed on and in contact between the barrier layer and the gate conductor 216", as disclosed at least in Para [0044] and FIGS. 2A-2C of the instant invention” and “Kim merely discloses that the second peripheral gate electrode 11c is constructed to have the three different layers, i.e., the first metal-containing layer 30, the second metal-containing layer 32 and the fourth metal-containing layer 36, as shown in paragraph [0120] and FIG. 9C of Kim”.
The examiner respectfully disagrees because it is well known in the art that any underlayer of a stacked metal-containing layers can be used and functioned as “a work function layer”, as recited in claim 1.
Applicant argues that “regarding the amended claim 11, Kim fails to teach that "the first protruding channel structure does not have the work function layer", as disclosed at least in FIGS. 2A-2C of 25 the instant invention” and “the work function layer is only formed to surround the upper part of the second protruding channel structure, such that the first protruding channel structure is free of the work function layer. Neither Kim nor Huang discloses such configuration”.
The examiner respectfully disagrees because Kim clearly shows in Figs. 9B and 9C in combined with Fig. 2B (C-C’) (when taking along lines D-D’ of Fig. 7) that the work function layer 36 is only formed to surround the upper part of the second protruding channel structure while the second protruding channel structure is free of the work function layer 36.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MEIYA LI/Primary Examiner, Art Unit 2811
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