DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 6-8, 13, and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (U.S 2020/0006324 A1) (of record).
As to claim 1, Chen et al. disclose in Fig. 6 a semiconductor structure, comprising: a bottom die (“first die” 100) (see Fig. 6, para. [0013]); a top die (“second die” 200) bonded to the bottom die (“first die” 100) (see Fig. 6, para. [0019]-[0020]), the bottom die (“first die” 100) being wider than the top die (“second die” 200) (see Fig. 6), and a bonding interface (a “bonding interface” is an interface between 100 & 200, Fig. 6) of the top and bottom dies (200 and 100) being substantially flat (Fig. 6); an insulating layer (“dielectric encapsulation” DE) disposed on the bottom die (“first die” 100) and laterally covering the top die (“second die” 200) (Fig. 6, para. [0039]-[0040]); and a first dual-damascene connector (see “first dual-damascene connector” as annotated in Fig. 6 below) overlying the insulating layer (“dielectric encapsulation” DE) and the top die (“second die” 200), and the first dual-damascene connector (see “first dual-damascene connector” as annotated in Fig. 6 below) inserted into the insulating layer (“dielectric encapsulation” DE) to be in electrical and physical contact with the bottom die (“first die” 100) (see annotated Fig. 6 below, para. [0045], [0046]); and a second dual-damascene connector (see “second dual-damascene connector” as annotated in Fig. 6 below) comprising a pad portion (a pad portion is a top horizontal portion of “second dual-damascene connector”, see annotated Fig. 6 below) overlying the top die (“second die” 200) and a via portion (TSVa) inserted into the top die (“second die” 200) (Fig. 6, para. [0022], [0040]).
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As to claim 4, as applied to claim 1 above, Chen et al. disclose in Fig. 6 all claimed limitations including the limitation: wherein the second dual-damascene connector (see “second dual-damascene connector” as annotated in Fig. 6 below) comprises: a conductive liner layer (see “conductive liner layer” as annotated in Fig. 6 below) lining with an inner sidewall of a semiconductor substrate (S2) of the top die (200), a rear surface (bottom surface) of the semiconductor substrate (S2) connected to the inner sidewall of the semiconductor substrate (S2) (Fig. 6); and a conductive material layer (see “conductive material layer” as annotated in Fig. 6 below) overlying the conductive liner layer (see “conductive liner layer” as annotated in Fig. 6 below) (see annotated Fig. 6 below).
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As to claim 6, as applied to claim 1 above, Chen et al. disclose in Fig. 6 all claimed limitations including the structure further comprising: an isolating liner (“at least one dielectric layer” 404) interposed between the semiconductor substrate (S2) of the top die (200) and the second dual-damascene connector (see “second dual-damascene connector” as annotated in Fig. 6 above) (see annotated Fig. 6 above, para. [0040]).
As to claim 7, as applied to claim 1 above, Chen et al. disclose in Fig. 6 all claimed limitations including the structure further comprising: a dielectric layer (“at least one dielectric layer” 404) disposed on the insulating layer (“dielectric encapsulation” DE) and the top die (200) to laterally cover a pad portion of the first dual-damascene connector (see “pad portion of the first dual-damascene connector”) and the pad portion of the second dual-damascene connector (the pad portion is a horizontal pad portion of “the second dual-damascene connector”, annotated Fig. 6) (see annotated Fig. 6 above, para. [0040]), wherein the dielectric layer (“at least one dielectric layer” 404) and the insulating layer (“dielectric encapsulation” DE) are of different materials (see annotated Fig. 6 above, para. [0040], [0045]).
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As to claim 8, Chen et al. disclose in Fig. 6 a semiconductor structure, comprising: a bottom die (“first die” 100) (see Fig. 6, para. [0013]; a top die (second die” 200) stacked upon and fused to the bottom die “first die” 100) (see Fig. 6, para. [0019]-[0020]); an insulating layer (“dielectric encapsulation” DE) disposed on the bottom die (“first die” 100) and laterally covering the top die (second die” 200) (Fig. 6, para. [0039]-[0040]); a first die connector (see “first die connector” as annotated in Fig. 6 below) comprising a first via portion (“through dielectric vias” TDV) laterally covered by the insulating layer (“dielectric encapsulation” DE) and landing on the bottom die (“first die” 100) (Fig. 6, para. [0045]-[0046]) and a first pad portion (see “first pad portion” as annotated in Fig. 6 below) connected with the first via portion (“through dielectric vias” TDV) (Fig. 6, para. [0040], [0045]-[0046]); and a second die connector (see “second die connector” as annotated in Fig. 6 below) comprising a second via portion (TSVa) inserted into the top die (second die” 200) (see annotated Fig. 6).
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As to claim 13, as applied to claim 8 above, Chen et al. disclose in Fig. 6 all claimed limitations including the limitation: wherein the second die connector (see “second die connector” as annotated in Fig. 6 above) comprises: a conductive material layer (see “conductive material layer” as annotated in Fig. 6 above); and a conductive liner layer (see “conductive liner layer” as annotated in Fig. 6 above) lining with a via opening of the top die (200) and extending over a rear surface (bottom surface) of the top die (200) opposite to the bottom die (100), and the conductive liner layer (see “conductive liner layer” as annotated in Fig. 6 above) interposed between the conductive material layer (see “conductive material layer” as annotated in Fig. 6 above) and the top die (200) (see annotated Fig. 6 above).
As to claim 21, as applied to claims 1 and 7 above, Chen et al. disclose in Fig. 6 all claimed limitations including the structure further comprising: a redistribution structure (comprising “passivation layers” 408 & 412, and ”pads” 410) disposed over the dielectric layer (“at least one dielectric layer” 404) and over the first dual- damascene connector (see “first dual-damascene connector” as annotated in Fig. 6 above) and the second dual-damascene connector (see “second dual-damascene connector” as annotated in Fig. 6 above); and conductive terminals (“conductive connectors”, para. [0041]) disposed on the redistribution structure (comprising “passivation layers” 408 & 412, and “pads” 410) (see annotated Fig. 6, para. [0041]-[0042]).
Allowable Subject Matter
Claims 2, 5, 9-12, and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 15-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: a semiconductor structure comprising: a top die bonded to the bottom die, the bottom die being wider than the top die, and a bonding interface of the top and bottom dies being substantially flat; an insulating layer disposed on the bottom die and laterally covering the top die, a surface roughness of an inner sidewall of the insulating layer being greater than that of the bonding interface; and a first dual-damascene connector comprising a via portion surrounded by the inner sidewall of the insulating layer and landing on the bottom die, as recited in independent claim 15. Claims 16-20 are dependent upon independent claim 15, and are therefore allowed.
Response to Arguments
Applicant's arguments filed 02/02/2026 have been fully considered but they are not persuasive.
Applicant argued that: due to the common inventor (Hsien-Wei Chen) of the cited reference Chen (U.S. Pub. 2020/0006324 A1) and of the instant application, the reference Chen should not be regarded as a proper prior art, and should be disqualified under the 35 USC 102(b)(1)(A) exception that the disclosure was made by the inventor(s) or joint inventor(s).
In response, the Applicant’s argument is respectfully traversed because merely having a common owner is not sufficient to overcome the rejection, and the reference Chen (U.S. Pub. 2020/0006324 A1) having an extra/additional inventor (Jie Chen) who is not a joint inventor of application, thus there is no exception. The 35 USC 102(b)(1)(A) exception only applies when the reference does not have/include any extra/additional inventor (who is not a joint inventor of application). See MPEP 2152.01(a).
Regarding MPEP 2152.01(a): “A disclosure made within the grace period is not prior art under AIA 35 U.S.C. 102(a)(1) if it is apparent from the disclosure itself that it is an inventor-originated disclosure. Specifically, Office personnel may not apply a disclosure as prior art under AIA 35 U.S.C. 102(a)(1) if the disclosure: (1) was made one year or less before the effective filing date of the claimed invention; (2) names the inventor or a joint inventor as an author or an inventor; and (3) does not name additional persons as authors on a printed publication or joint inventors on a patent. This means that in circumstances where an application names additional persons as joint inventors relative to the persons named as authors in the publication (e.g., the application names as joint inventors A, B, and C, and the publication names as authors A and B), and the publication is one year or less before the effective filing date, it is apparent that the disclosure is a grace period inventor disclosure, and the publication is not prior art under AIA 35 U.S.C. 102(a)(1). If, however, the application names fewer joint inventors than a publication (e.g., the application names as joint inventors A and B, and the publication names as authors A, B and C), it would not be readily apparent from the publication that it is an inventor-originated disclosure and the publication would be treated as prior art under AIA 35 U.S.C. 102(a)(1) unless there is evidence of record that an exception under AIA 35 U.S.C. 102(b)(1) applies”.
Accordingly, the rejection (for claims 1, 4, 6-8, and 21) under 102(a)(1) (as being anticipated by Chen (U.S. Pub. 2020/0006324 A1)) is proper. Applicant will have to file a declaration or affidavit to explain why Jie Chen (extra/additional inventor) listed on the reference (U.S. Pub. 2020/0006324 A1) to overcome the rejection. See MPEP 717.01(a)(1) for declarations for 102(a)(1).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST).
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/Thanh Y. Tran/Primary Examiner, Art Unit 2817 May 23, 2026
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