DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A2, B2, C2, D1, and II is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dewey et al. (US 2020/0295003 A1) in view of Misaki et al. (US 2021/0119007 A1).
Regarding claim 1, Dewey discloses a method for forming a semiconductor device structure, comprising:
forming a stack (104 and 106 in Fig. 2A) over a substrate (102), wherein the stack has a plurality of sacrificial layers (104) and a plurality of oxide semiconductor layers (106; ¶ 0020) laid out alternately;
partially removing the sacrificial layers to form a recess exposing portions of the oxide semiconductor layers (see Fig. 6B), wherein inner portions of the oxide semiconductor layers exposed by the recess form a plurality of oxide semiconductor nanostructures; and
forming a gate stack (124 in Fig. 16B) wrapped around at least one of the oxide semiconductor layers.
Dewey does not disclose introducing oxygen into the oxide semiconductor nanostructures.
Misaki discloses introducing oxygen into oxide semiconductors (¶ 0150). There was a benefit to introducing oxygen in that it repairs lattice defects (¶ 0150). It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to introduce oxygen into the oxide semiconductor nanostructures of Dewey for this benefit.
Regarding claim 2, Misaki further discloses wherein the introducing of oxygen into the oxide semiconductor is performed by annealing the oxide semiconductor under an oxygen-containing atmosphere (¶ 0150).
Regarding claim 3, Dewey does not explicitly disclose a reduction in an atomic concentration of oxygen of outer portions of the oxide semiconductor layers.
However, Dewey discloses doing an anneal on the gate dielectric 122 (¶ 0023; Fig. 15B) which contacts the outer portions of the oxide semiconductor layers. As such, there will be a reduction in the concentration of oxygen (at least to some extent) in these outer portions as Applicant has stated that an anneal will drive out oxygen in oxide semiconductors. These outer portions of the oxide semiconductor layers sandwich the oxide semiconductor nanostructures (which may be considered the portion the oxide semiconductor interior to the aforementioned outer portions).
Regarding claim 4, as discussed in the rejection of claim 3 above, the reducing is oxygen is performed by annealing the outer portions of the oxide semiconductor layers under an atmosphere containing substantially no oxygen (¶ 0023 of Dewey).
Regarding claim 5, with regards to the relative timing of the introducing of oxygen and the reduction of oxygen, it would have been obvious to one having ordinary skill in the art at the time the application was filed to perform the step of introducing oxygen before the gate dielectric layer is applied as the gate dielectric layer would block oxygen if present. As the step of reducing oxygen occurs after the gate dielectric layer is applied, as discussed above, the reducing of the atomic concentration of oxygen of the outer portions of the oxide semiconductor layers will be performed after the introducing of oxygen into the oxide semiconductor nanostructures.
Regarding claim 6, Dewey does not explicitly disclose a reduction in an atomic concentration of oxygen of outer portions of the oxide semiconductor layers.
However, Dewey discloses forming a plurality of oxygen-scavenging layers (122 in Fig. 15B), wherein each of the oxygen-scavenging layers is formed on a respective oxide semiconductor layer of the oxide semiconductor layers doing an anneal on the oxygen-scavenging layers (¶ 0023; Fig. 15B) which contacts the outer portions of the oxide semiconductor layers. As such, there will be a reduction in the concentration of oxygen (at least to some extent) in these outer portions as Applicant has stated that an anneal will drive out oxygen in oxide semiconductors.
Regarding claim 7, Dewey further discloses wherein the oxygen-scavenging layers comprise titanium (¶ 0023).
Regarding claim 8, Dewey further discloses trimming the oxide semiconductor nanostructures before the gate stack is formed (see transition from Fig. 6B to Fig. 7B).
Regarding claim 9, it would have been obvious to one having ordinary skill in the art before the Application's effective filing date to introduce the oxygen into the oxide semiconductor nanostructures after trimming the oxide semiconductor nanostructures as the portions of the oxide semiconductor nanostructures which remain in the final product are only exposed after trimming (see Fig. 9B).
Regarding claim 10, Dewey further discloses wherein a lower portion of the gate stack is formed under the oxide semiconductor nanostructures and an upper portion of the gate stack is formed above the oxide semiconductor nanostructures (see Fig. 17B).
Regarding claim 11, Dewey further discloses forming a dielectric filling (116 in Fig. 16B) which, in the final form of the product, is wrapped around the oxide semiconductor nanostructures and portions of the gate stack (see Fig. 16B).
Regarding claim 12, Dewey discloses a method for forming a semiconductor device structure, comprising:
forming a stack (104 and 106 in Fig. 2A) over a substrate (102), wherein the stack has a plurality of sacrificial layers (104) and a plurality of oxide semiconductor layers (106; ¶ 0020) laid out alternately;
partially removing the sacrificial layers to form a recess exposing portions of the oxide semiconductor layers (see Fig. 6B), wherein inner portions of the oxide semiconductor layers exposed by the recess form a plurality of oxide semiconductor nanostructures; and
forming a gate stack (124 in Fig. 16B) wrapped around at least one of the oxide semiconductor layers.
Dewey does not disclose introducing oxygen into the oxide semiconductor nanostructures.
Misaki discloses introducing oxygen into oxide semiconductors (¶ 0150). There was a benefit to introducing oxygen in that it repairs lattice defects (¶ 0150). It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to introduce oxygen into the oxide semiconductor nanostructures of Dewey for this benefit.
With regards to the relative timing of the introducing of oxygen and forming the gate stack, it would have been obvious to one having ordinary skill in the art at the time the application was filed to perform the step of introducing oxygen before forming the gate stack as the gate stack would block oxygen if present.
Regarding claim 13, Dewey does not explicitly disclose changing a second atomic concentration of oxygen of outer portions of the oxide semiconductor layers.
However, Dewey discloses doing an anneal on the gate dielectric 122 (¶ 0023; Fig. 15B) which contacts the outer portions of the oxide semiconductor layers. As such, there will be a reduction in the concentration of oxygen (at least to some extent) in these outer portions as Applicant has stated that an anneal will drive out oxygen in oxide semiconductors.
Regarding claim 14, with regards to the relative timing of the first and second changing, it would have been obvious to one having ordinary skill in the art at the time the application was filed to perform the step of introducing oxygen before the gate dielectric layer is applied as the gate dielectric layer would block oxygen if present. As the step of reducing oxygen occurs after the gate dielectric layer is applied, as discussed above, the reducing of the atomic concentration of oxygen of the outer portions of the oxide semiconductor layers will be performed after the introducing of oxygen into the oxide semiconductor nanostructures.
Regarding claim 15, as discussed above the changing of the first atomic concentration of oxygen is performed under an oxygen-containing atmospheres. Further, as there is no disclosure or reasons for the second changing to by in an oxygen atmosphere, it would have been obvious for it to occur under an atmosphere containing substantially no oxygen.
Regarding claim 16, Dewey further discloses trimming the oxide semiconductor nanostructures (see transition from Fig. 6B to Fig. 7B). It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to introduce the oxygen into the oxide semiconductor nanostructures after trimming the oxide semiconductor nanostructures as the portions of the oxide semiconductor nanostructures which remain in the final product are only exposed after trimming (see Fig. 9B).
Regarding claim 17, Dewey discloses a method for forming a semiconductor device structure, comprising:
forming a semiconductor nanostructure (106 in Fig. 3B) over a substrate (102);
trimming an inner portion of the semiconductor nanostructure (see transition from Fig. 6B to Fig. 7B); and
forming a gate stack (124 in Fig. 16B) over the inner portion of the semiconductor nanostructure, wherein a portion of the gate stack is between the semiconductor nanostructure and the substrate.
Dewey does not disclose introducing oxygen into the inner portion of the semiconductor nanostructures.
Misaki discloses introducing oxygen into oxide semiconductors (¶ 0150). There was a benefit to introducing oxygen in that it repairs lattice defects (¶ 0150). It would have been obvious to one having ordinary skill in the art before the Application's effective filing date to introduce oxygen into the oxide semiconductor nanostructures of Dewey for this benefit.
Regarding claim 18, Dewey does not explicitly discloses driving oxygen originally in outer portions of the semiconductor nanostructure to leave the outer portions of the semiconductor nanostructure.
However, Dewey discloses doing an anneal on the gate dielectric 122 (¶ 0023; Fig. 15B) which contacts the outer portions of the semiconductor nanostructure. As such, there will be a driving of oxygen (at least to some extent) in these outer portions as Applicant has stated that an anneal will drive out oxygen in oxide semiconductors.
Regarding claim 19, with regards to the relative timing of the introducing of oxygen and the driving of oxygen, it would have been obvious to one having ordinary skill in the art at the time the application was filed to perform the step of introducing oxygen before the gate dielectric layer is applied as the gate dielectric layer would block oxygen if present. As the step of driving oxygen occurs after the gate dielectric layer is applied, as discussed above, the driving of the atomic concentration of oxygen of the outer portions of the oxide semiconductor layers will be performed after the introducing of oxygen into the oxide semiconductor nanostructures.
Regarding claim 20, with regards to the relative timing of the introducing of oxygen and the driving of oxygen, it would have been obvious to one having ordinary skill in the art at the time the application was filed to perform the step of introducing oxygen before the gate dielectric layer is applied as the gate dielectric layer would block oxygen if present. As the step of driving oxygen occurs after the gate dielectric layer is applied, as discussed above, the driving of the atomic concentration of oxygen of the outer portions of the oxide semiconductor layers will be performed after the introducing of oxygen into the oxide semiconductor nanostructures.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A CULBERT whose telephone number is (571)272-4893. The examiner can normally be reached M-F 9-5.
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/CHRISTOPHER A CULBERT/ Examiner, Art Unit 2815