DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3 November 2025 was filed after the mailing date of the Non-Final Rejection on 9 October 2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
The Office acknowledges receipt on 9 January 2026 of Applicants’ amendments in which claims 14, 22, 23, and 31 are amended, claim 30 is cancelled, and claim 34 is newly added. The Office withdraws the drawing objections and section 112(a) new matter rejections identified in the Office Communication dated 9 October 2025 in view of the amendments.
Response to Arguments
Applicants’ arguments with respect to claim(s) 14, 22, and 31 have been considered but they are not persuasive.
Applicants argue in the penultimate paragraph of page 10 through page 11 that Bi does teach the subject matter newly added to independent claim 14 of “after removing the portions of the first dielectric layer above the first nanostructures and the second nanostructures, depositing a second dielectric layer over the first portion of the first dielectric layer in the first trench and over the second portion of the first dielectric layer in the second trench, the second dielectric layer comprising a second dielectric material.” More specifically, Applicants propose Bi teaches the opposite sequence of operations to that recited in claim 14. The selection of any order of performing process steps is prima facie obvious in the absence of a new or unexpected result. MPEP 2144.04(IV)(C). As this principle applies to the present circumstance, the instant application does not identify a new or unexpected result occurring due to the claimed sequence of operations. Accordingly, the claimed sequence is prima facie obvious.
Applicants argue in the first paragraph of page 12 that Jhang does teach the subject matter newly added to independent claim 22 of “the first lower insulating layer having a first width, the first upper insulating layer having the first width, the second lower insulating layer having a second width, the second upper insulating layer having the second width.” Amended claim 22 is rejected as being unpatentable over the teachings of Jhang. With respect to the above-identified subject matter of amended claim 22, the instant application does not identify any criticality or operational difference obtained by having: (1) the same first width for the first lower insulating layer and the first upper insulating layer and (2) the same second width for the second lower insulating layer and the second upper insulating layer. [Where] the dimensional limitations [of the claimed device] d[o] not specify a device which perform[s] and operate[s] any differently from the prior art, a difference between such claimed dimensional limitations and those existing in the prior art is insufficient to render the claimed device non-obvious over the prior art. Gardner v. TEC Systems, Inc., 725 F.2d 1338, 1345, 1349 (Fed. Cir. 1984); see also MPEP 2144.04(IV)(A).
Applicants argue in the last three paragraphs of page 12 that Bi does not teach the subject matter newly added to independent claim 31 of “after forming the first insulating fin and the second insulating fin ... forming a first metal gate and a second metal gate.” Claim 31 is rejected over the combined teachings of Bi, Bi ‘130, Peng, and Chiang and recites, in relevant part, “after forming the first insulating fin and the second insulating fin, … forming a first metal gate and a second metal gate.” Obviousness can be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so. MPEP §2143.01. As this principle applies to the present circumstance, Chiang further teaches in Fig. 1L-2, IL-3 and paragraphs [0078] and [0079] forming a metal gate (156), the metal gate (156) formed around nanostructures (104) and extending over an insulating fin (116) {which makes implicit the formation of the metal gate after the formation of the insulating fin}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bi’s method based on the teachings of Chiang – to include after forming the first insulating fin and the second insulating fin, … forming a first metal gate and a second metal gate around nanostructures and extending over an insulating fin – to form nanowire structures with a GAA design for n-type FinFETs and/or p-type FinFETs. Chiang ¶0022. Moreover, with respect to the sequence of operations imposed by the recited word “after”: (1) the instant application does not identify a new or unexpected result occurring due to the claimed sequence of operations and (2) the selection of any order of performing process steps is prima facie obvious in the absence of a new or unexpected result. MPEP 2144.04(IV)(C).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 14, 17-19, 31, and 34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bi et al. (US20180053844A1) in view of Bi et al. (US20200295130A1), Peng (US20190385898A1), and Chiang et al. (US20210280709A1).
Regarding claim 14, Bi teaches a method comprising:
depositing a first dielectric layer (200) in the first trench (leftmost entire trench) and the second trench (rightmost entire trench), the first dielectric layer (200) comprising a first dielectric material (implicit) {Fig. 2; ¶0040};
removing portions of the first dielectric layer (200) above the first fin structures (106s adjacent leftmost entire trench) and the second fin structures (106s adjacent rightmost entire trench), a first portion of the first dielectric layer (200) remaining in the first trench (leftmost entire trench), a second portion of the first dielectric layer (200) remaining in the second trench (rightmost entire trench) {Fig. 5; ¶0045};
depositing a second dielectric layer (300) over the first portion of the first dielectric layer (200) in the first trench (leftmost entire trench) and over the second portion of the first dielectric layer (200) in the second trench (rightmost entire trench), the second dielectric layer (300) comprising a second dielectric material (implicit) {Fig. 3; ¶0041};
converting a first portion of the second dielectric layer (300) in the first trench (leftmost entire trench) to a third dielectric material (400), a second portion of the second dielectric layer (300) in the second trench (rightmost entire trench) remaining as the second dielectric material (300), the first portion of the first dielectric layer (200) in the first trench (leftmost entire trench) remaining as the first dielectric material (200), the second portion of the first dielectric layer (200) in the second trench (rightmost entire trench) remaining as the first dielectric material (200) {Fig. 4; ¶0042-0044}.
Bi does not teach patterning a multi-layer stack to form a first trench between first nanostructures and to form a second trench between second nanostructures.
In an analogous art, Bi ‘130 teaches in Fig. 7 and paragraphs [0024] and [0034] patterning a multi-layer stack to form a first trench between first nanostructures and to form a second trench between second nanostructures. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bi’s method based on the teachings of Bi ‘130 – to include patterning a multi-layer stack to form a first trench between first nanostructures and to form a second trench between second nanostructures – to form field effect transistors. Bi ‘130 ¶0002. A consequence of this modification is that Bi’s first and second fin structures become first and second nanostructures.
Bi as modified by Bi ‘130 does not teach the first trench wider than the second trench.
In an analogous art, Peng teaches in Fig. 1A and paragraph [0017] a first trench wider than a second trench. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bi’s method as modified by Bi ‘130 based on the teachings of Peng – such that the first trench wider than the second trench – so adjacent source/drain regions corresponding to trenches having a high aspect ratio may be merged and other adjacent source/drain regions corresponding to trenches having a low aspect ratio may be not merged. Peng ¶0049. Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Bi as modified by Bi ‘130 and Peng does not teach that the operation of depositing a second dielectric layer over the first portion of the first dielectric layer in the first trench and over the second portion of the first dielectric layer in the second trench is necessarily performed after removing the portions of the first dielectric layer above the first nanostructures and the second nanostructures.
However, the instant application does not identify a new or unexpected result occurring due to the claimed sequence of operations and (2) the selection of any order of performing process steps is prima facie obvious in the absence of a new or unexpected result. MPEP 2144.04(IV)(C).
Bi as modified by Bi ‘130 and Peng does not teach removing portions of the second dielectric layer above the first nanostructures and the second nanostructures to form a first insulating fin in the first trench and to form a second insulating fin in the second trench.
In an analogous art, Chiang teaches in Figs. 1B and 1C and paragraphs [0034] and [0037] removing portions of a second dielectric layer (114) above nanostructures to form an insulating fin in a trench. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bi’s method as modified by Bi ‘130 and Peng based on the teachings of Chiang – to include removing portions of the second dielectric layer above each of the first nanostructures and the second nanostructures to form a first insulating fin in the first trench and to form a second insulating fin in the second trench – to expose the upper surfaces of the semiconductor fin structures. Chiang ¶0037. Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 17, Bi as modified by Bi ‘130, Peng, and Chiang teaches the method of claim 14, and Bi further teaches wherein converting the first portion of the second dielectric layer (300) to the third dielectric material (400) comprises: modifying a composition of the first portion of the second dielectric layer (300) {Fig. 4; ¶0042-0044}.
Regarding claim 18, Bi as modified by Bi ‘130, Peng, and Chiang teaches the method of claim 14, and Bi further teaches wherein converting the first portion of the second dielectric layer (300) to the third dielectric material (400) comprises: modifying a density of the first portion of the second dielectric layer (24) {Fig. 4; ¶0042-0044; SiON and SiO2 have different densities}.
Regarding claim 19, Bi as modified by Bi ‘130, Peng, and Chiang teaches the method of claim 14, but Bi does not teach wherein converting the first portion of the second dielectric layer to the third dielectric material comprises: modifying a porosity of the first portion of the second dielectric layer.
Peng teaches in Figs. 2 and 3 and paragraphs [0028] and [0034] converting a first portion of a second dielectric layer (24) to a third dielectric material (26) comprises: modifying a porosity of the first portion of the second dielectric layer (24) {modified porosity is implicit due to increased volume and decreased density}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bi’s method as modified by Bi ‘130, Peng, and Chiang based on the further teachings of Peng – such that converting the first portion of the second dielectric layer to the third dielectric material comprises: modifying a porosity of the first portion of the second dielectric layer – to change the k-value/etch-selectivity of the dielectric material. Peng ¶0034, 0035.
Regarding claim 31, Bi teaches a method comprising:
forming a first insulating fin in the first trench (leftmost entire trench) and second insulating fin in the second trench (rightmost entire trench) by:
depositing a first dielectric layer (300) in the first trench (leftmost entire trench) and the second trench (rightmost entire trench), the first dielectric layer (300) comprising a first dielectric material (implicit) {Fig. 3; ¶0041};
converting a first lower portion of the first dielectric layer (300) in the first trench (leftmost entire trench), a first upper portion of the first dielectric layer (300) in the first trench (leftmost entire trench), and a second upper portion of the first dielectric layer (300) in the second trench (rightmost entire trench) to a second dielectric material (400), a second lower portion of the first dielectric layer (300) in the second trench (rightmost entire trench) remaining as the first dielectric material (300) {Fig. 4, see annotated copies of Bi’s Figs. 3 and 4 below; ¶0042-0044}.
Bi does not teach patterning a multi-layer stack to form a first trench between first nanostructures and to form a second trench between second nanostructures.
Bi ‘130 teaches in Fig. 7 and paragraphs [0024] and [0034] patterning a multi-layer stack to form a first trench between first nanostructures and to form a second trench between second nanostructures. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bi’s method based on the teachings of Bi ‘130 – to include patterning a multi-layer stack to form a first trench between first nanostructures and to form a second trench between second nanostructures – to form field effect transistors. Bi ‘130 ¶0002.
Bi as modified by Bi ‘130 does not teach the first trench wider than the second trench.
Peng teaches in Fig. 1A and paragraph [0017] a first trench wider than a second trench. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bi’s method as modified by Bi ‘130 based on the teachings of Peng – such that the first trench wider than the second trench – so adjacent source/drain regions corresponding to trenches having a high aspect ratio may be merged and other adjacent source/drain regions corresponding to trenches having a low aspect ratio may be not merged. Peng ¶0049. Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Bi as modified by Bi ‘130 and Peng does not teach removing the first upper portion of the first dielectric layer and the second upper portion of the first dielectric layer, the first insulating fin comprising the first lower portion of the first dielectric layer, the second insulating fin comprising the second lower portion of the first dielectric layer.
Chiang teaches in Figs. 1B and 1C and paragraphs [0034] and [0037] removing an upper portion of a first dielectric layer (layer of 116), an insulating fin (116) comprising a lower portion of the first dielectric layer (layer of 116). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bi’s method as modified by Bi ‘130 and Peng based on the teachings of Chiang – to include removing the upper portion of the first dielectric layer, each of first and second insulating fins formed from the unremoved (e.g., lower) portions of the first dielectric layer – to form dielectric fin structures in trenches between adjacent semiconductor fin structures. Chiang ¶0033. Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Bi as modified by Bi ‘130, Peng, and Chiang above does not teach to include after forming the first insulating fin and the second insulating fin, growing first source/drain regions and second source/drain regions, the first source/drain regions grown adjacent the first nanostructures, the first insulating fin disposed between the first source/drain regions, the second source/drain regions grown adjacent the second nanostructures, the second insulating fin disposed between the second source/drain regions.
Chiang further teaches in Fig. 1J and paragraphs [0022] and [0059] growing source/drain regions (144), the source/drain regions (144) grown adjacent nanostructures (104), an insulating fin (116) disposed between the first source/drain regions (144). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bi’s method as modified by Bi ‘130, Peng, and Chiang based on the further teachings of Chiang – to include, for each of first and second nanostructures, to include after forming the first insulating fin and the second insulating fin, growing source/drain regions, the source/drain regions grown adjacent the respective nanostructures, an insulating fin disposed between the first source/drain regions – to form nanowire structures with a GAA design for n-type FinFETs and/or p-type FinFETs. Chiang ¶0022. Moreover, with respect to the sequence of operations imposed by the recited word “after”: (1) the instant application does not identify a new or unexpected result occurring due to the claimed sequence of operations and (2) the selection of any order of performing process steps is prima facie obvious in the absence of a new or unexpected result. MPEP 2144.04(IV)(C).
Bi as modified by Bi ‘130, Peng, and Chiang above does not teach after forming the first insulating fin and the second insulating fin, forming a first metal gate and a second metal gate, the first metal gate formed around the first nanostructures, the first metal gate extending over the first insulating fin, the second metal gate formed around the second nanostructures, the second metal gate extending over the second insulating fin.
Chiang further teaches in Fig. 1L-2, IL-3 and paragraphs [0078] and [0079] forming a metal gate (156), the metal gate (156) formed around nanostructures (104), the metal gate (156) extending over an insulating fin (116). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bi’s method as modified by Bi ‘130, Peng, and Chiang based on the further teachings of Chiang – to include after forming the first insulating fin and the second insulating fin, forming a first metal gate and a second metal gate, the first metal gate formed around the first nanostructures, the first metal gate extending over the first insulating fin, the second metal gate formed around the second nanostructures, the second metal gate extending over the second insulating fin – to form nanowire structures with a GAA design for n-type FinFETs and/or p-type FinFETs. Chiang ¶0022. Moreover, with respect to the sequence of operations imposed by the recited word “after”: (1) the instant application does not identify a new or unexpected result occurring due to the claimed sequence of operations and (2) the selection of any order of performing process steps is prima facie obvious in the absence of a new or unexpected result. MPEP 2144.04(IV)(C).
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Regarding claim 34, Bi as modified by Bi ‘130, Peng, and Chiang teaches the method of claim 31, but Bi does not teach wherein converting the first lower portion of the first dielectric layer, the first upper portion of the first dielectric layer, and the second upper portion of the first dielectric layer to the second dielectric material comprises performing a treatment process to modify a composition of the first dielectric material.
Peng teaches in Figs. 2 and 3 and paragraph [0033] converting a first dielectric material (24) to a second dielectric material (26) comprises performing a radical treatment to modify a composition of the first dielectric material (24). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bi’s method as modified by Bi ‘130, Peng, and Chiang based on the further teachings of Peng – such that converting the first lower portion of the first dielectric layer, the first upper portion of the first dielectric layer, and the second upper portion of the first dielectric layer to the second dielectric material comprises performing a treatment process to modify a composition of the first dielectric material – so an oxygen radical … may have better penetration. Peng ¶0033. Moreover, applying a known improvement technique in the same way (as taught by Peng) to a known method (as taught by Jhan and Bi) to produce predictable results (e.g., a change of k-value and/or etch resistance) is within the ordinary skill in the art.
Claim(s) 15, 16, 32, 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bi in view of Bi ‘130, Peng, Chiang as applied to claims 14 (for claims 15 and 16) and 31 (for claims 32 and 33) above, and further in view of Ching et al. (US20190067417A1).
Regarding claim 15, Bi as modified by Bi ‘130, Peng, and Chiang teaches the method of claim 14, but Bi does not teach further comprising:
etching a first recess in the first insulating fin with a first etching process, the first etching process selectively etching the third dielectric material at a faster rate than the second dielectric material; and
etching a second recess in the second insulating fin with a second etching process, the second etching process selectively etching the second dielectric material at a faster rate than the third dielectric material.
Ching teaches in Figs. 5-7 and paragraphs [0038] and [0039] etching a first recess (304a) in a first insulating fin (fin corresponding to 304a) with a first etching process, the first etching process selectively etching a third dielectric material (106a; ¶0020) at a faster rate than a second dielectric material (502; ¶0038); and etching a second recess (304c) in a second insulating fin (fin corresponding to 304c) with a second etching process, the second etching process selectively etching the second dielectric material (502) at a faster rate than the third dielectric material (106a). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bi’s method as modified by Bi ‘130, Peng, and Chiang based on the teachings of Ching – such that a first recess is etched in the first insulating fin with a first etching process, the first etching process selectively etching the third dielectric material at a faster rate than the second dielectric material; and a second recess is etched in the second insulating fin with a second etching process, the second etching process selectively etching the second dielectric material at a faster rate than the third dielectric material – because a uniformity of fin density is improved and [such] provides better structur[al] fidelity. Ching ¶0016.
Regarding claim 16, Bi as modified by Bi ‘130, Peng, Chiang, and Ching teaches the method of claim 15, but Bi does not teach wherein the first insulating fin is exposed to the second etching process and the second insulating fin is exposed to the first etching process.
Ching teaches in Figs. 5-7 and paragraphs [0038] and [0039] the first insulating fin (fin corresponding to 304a) is exposed to the second etching process and the second insulating fin (fin corresponding to 304c) is exposed to the first etching process. This feature is a consequence of the modification of the teachings of Bi as modified by Bi ‘130, Peng, and Chiang based on the teachings of Ching as discussed with respect to intermediate claim 15. Accordingly, the motivation for the modification is identified with respect to claim 15.
Regarding claim 32, Bi as modified by Bi ‘130, Peng, and Chiang teaches the method of claim 31, but Bi does not teach further comprising:
depositing a dummy gate layer over the first insulating fin and the second insulating fin; and
patterning the dummy gate layer to form a first dummy gate and a second dummy gate, the first dummy gate formed over the first insulating fin, the second dummy gate formed over the second insulating fin, wherein patterning the dummy gate layer comprises:
etching the dummy gate layer and the first insulating fin with a first etching process, the first etching process selectively etching the second dielectric material at a faster rate than the first dielectric material; and
etching the dummy gate layer and the second insulating fin with a second etching process, the second etching process selectively etching the first dielectric material at a faster rate than the second dielectric material.
Peng teaches:
depositing a dummy gate layer (32) over the first insulating fin (26 corresponding to W2) and the second insulating fin (26 corresponding to W1) {Fig. 6; ¶0044}; and
patterning the dummy gate layer (32) to form a first dummy gate (32) and a second dummy gate (32), the first dummy gate (32) formed over the first insulating fin (26 corresponding to W2), the second dummy gate (32) formed over the second insulating fin (26 corresponding to W1) {Figs. 6, 7A, B; ¶0044, 0045}, wherein patterning the dummy gate layer comprises:
etching the dummy gate layer (32) and the first insulating fin (26 corresponding to W2) with a first etching process {Figs. 8A, 8B; ¶0053}; and
etching the dummy gate layer (32) and the second insulating fin (26 corresponding to W1) with a second etching process {Figs. 8A, 8B; ¶0053, the dummy gates 32 are removed, such as by … etch processes}.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bi’s method as modified by Bi ‘130, Peng, and Chiang based on the teachings of Peng for forming the first dummy gate and the second dummy gate as identified above because applying a known improvement technique in the same way (as taught by Peng) to a known method (as taught by Bi, Bi ‘130, Peng, and Chiang) to produce predictable results is within the ordinary skill in the art.
Examiner’s Note: Peng teaches in paragraph [0053] that both the first and second insulating fins are etched by multiple etch processes (i.e., not by multiple instances of the same etch process).
Bi as modified by Peng above does not teach the first etching process selectively etching the second dielectric material at a faster rate than the first dielectric material; and the second etching process selectively etching the first dielectric material at a faster rate than the second dielectric material.
Ching teaches in Figs. 5-7 and paragraphs [0038] and [0039] etching a first recess (304a) in a first insulating fin (fin corresponding to 304a) with a first etching process, the first etching process selectively etching the second dielectric material (106a; ¶0020) at a faster rate than the first dielectric material (502; ¶0038); and etching a second recess (304c) in the second insulating fin (fin corresponding to 304c) with a second etching process, the second etching process selectively etching the first dielectric material (502) at a faster rate than the second dielectric material (106a). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bi’s method as modified by Bi ‘130, Peng, and Chiang based on the teachings of Ching – such that the first etching process selectively etches the second dielectric material at a faster rate than the first dielectric material; and the second etching process selectively etching the first dielectric material at a faster rate than the second dielectric material – because a uniformity of fin density is improved and [such] provides better structur[al] fidelity. Ching ¶0016.
Regarding claim 33, Bi as modified by Bi ‘130, Peng, Chiang, and Ching teaches the method of claim 32, but Bi does not teach wherein the first insulating fin is exposed to the second etching process and the second insulating fin is exposed to the first etching process.
Ching teaches in Figs. 5-7 and paragraphs [0038] and [0039] the first insulating fin (fin corresponding to 304a) is exposed to the second etching process and the second insulating fin (fin corresponding to 304c) is exposed to the first etching process. This feature is a consequence of the modification of the teachings of Bi as modified by Bi ‘130, Peng, and Chiang based on the teachings of Ching as discussed with respect to intermediate claim 32. Accordingly, the motivation for the modification is identified with respect to claim 32.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bi, Bi ‘130, Peng, and Chiang as applied to claim 14 above, and further in view of LaVoie et al. (US20160233081A1) and Pham et al. (US8728885B1).
Regarding claim 20, Bi as modified by Bi ‘130, Peng, and Chiang teaches the method of claim 14, but Bi does not teach wherein converting the first portion of the second dielectric layer to the third dielectric material comprises: modifying a stress of the first portion of the second dielectric layer.
In an analogous art, LaVoie teaches that the SiC/SiCN stoichiometry of the as-deposited film may be tuned with a nitrogen or amine plasma {¶0046} to modify the film’s internal stress {¶0045}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bi’s method as modified by Bi ‘130, Peng, and Chiang based on the teachings of LaVoie – such that converting the first portion of the second dielectric layer to the third dielectric material comprises modifying a stress of the first portion of the second dielectric layer – so that the trenches may be filled with highly stressed dielectric materials to isolate the fins and induce an appropriate stress in the fins to increase device performance capability. Pham col. 2 ll. 42-45.
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bi, Bi ‘130, Peng, and Chiang as applied to claim 14 above, and further in view of LaVoie and Liu et al. (US20190189445A1).
Regarding claim 21, Bi as modified by Bi ‘130, Peng, and Chiang teaches the method of claim 14, but Bi does not teach
wherein the second dielectric material comprises silicon carbide, the third dielectric material comprises silicon oxycarbide or silicon carbonitride, and the method further comprises:
etching a first recess in the first insulating fin with a first etching process, the first etching process comprising a dry etch performed with a first mixture of gases comprising argon, methane, and hydrogen fluoride; and
etching a second recess in the second insulating fin with a second etching process, the second etching process comprising a dry etch performed with a second mixture of gases comprising argon, methane, and hydrogen fluoride, a ratio of the gases in the second mixture being different from a ratio of the gases in the first mixture.
Peng teaches a dielectric material comprises silicon oxycarbide or silicon carbonitride {¶0036}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bi’s method as modified by Bi ‘130, Peng, and Chiang based on the further teachings of Peng – such that the third dielectric material comprises silicon oxycarbide or silicon carbonitride – because [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
LaVoie teaches that the SiC/SiCN stoichiometry of the as-deposited film may be tuned with a nitrogen or amine plasma {¶0046} to modify the film’s internal film stress, etch resistance, density, hardness, optical properties (refractive index, reflectivity, optical density, etc.), dielectric constant, carbon content, electrical properties (Vfb spread, etc.), and the like. {¶0045}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bi’s method as modified by Bi ‘130, Peng, and Chiang based on the teachings of LaVoie – such that the second dielectric material comprises silicon carbide – to modulate a film's dielectric constant and/or a film etch rate. LaVoie ¶0090.
In an analogous art, Liu teaches in Figs. 5B and 5C and paragraph [0062] etching a dielectric layer 122 (e.g., silicon oxide, silicon nitride) with an etching process comprising a dry etch performed with a first mixture of gases comprising argon, methane, and hydrogen fluoride. Additionally, Liu teaches in Figs. 5C and 5D and paragraph [0063] etching a high-stress dielectric film 402 (e.g., silicon oxide, silicon nitride) with another etching process comprising a dry etch performed with a second mixture of gases comprising argon, methane, and hydrogen fluoride, and nitrogen, which is a different mixture of gases and a different ratio of the gases than that used to etch the dielectric layer 122 {the ratio of gases is necessarily different because the second mixture includes an additional gas to the first mixture}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bi’s method as modified by Bi ‘130, Peng, Chiang, and LaVoie based on the teachings of Liu – so as to etch a first recess in the first insulating fin with a first etching process, the first etching process comprising a dry etch performed with a first mixture of gases comprising argon, methane, and hydrogen fluoride; and etch a second recess in the second insulating fin with a second etching process, the second etching process comprising a dry etch performed with a second mixture of gases comprising argon, methane, and hydrogen fluoride, a ratio of the gases in the second mixture being different from a ratio of the gases in the first mixture – because applying a known improvement technique in the same way (as taught by Liu) to a known method (as taught by Bi, Bi ‘130, Peng, Chiang, and LaVoie) to produce predictable results (e.g., etching of dielectric materials having different properties) is within the ordinary skill in the art.
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhan et al. (CN113539807A) using Jhan et al. (US20220059678A1) as the English Translation.
Regarding claim 22, Jhan teaches a method comprising:
forming first nanostructures (leftmost 18:[14, 16]) and second nanostructures (rightmost 18:[14, 16]) {Fig. 4; ¶0015};
forming a first insulating fin (34, 36 between leftmost 18:[14, 16]) and a second insulating fin (34, 36, 38, 40 between rightmost 18:[14, 16]), the first insulating fin (34, 36 between leftmost 18:[14, 16]) formed between the first nanostructures (leftmost 18:[14, 16]), the second insulating fin (34, 36, 38, 40 between rightmost 18:[14, 16]) formed between the second nanostructures (rightmost 18:[14, 16]), the first insulating fin (34, 36 between leftmost 18:[14, 16]) comprising a first lower insulating layer (34 between leftmost 18:[14, 16]) and a first upper insulating layer (36 between leftmost 18:[14, 16]), the second insulating fin (34, 36, 38, 40 between rightmost 18:[14, 16]) comprising a second lower insulating layer (34 between rightmost 18:[14, 16]) and a second upper insulating layer (36/38/40 between rightmost 18:[14, 16]), the first lower insulating layer (34 between leftmost 18:[14, 16]) and the second lower insulating layer (34 between rightmost 18:[14, 16]) comprising the same dielectric material (e.g., SiO, etc.), the first upper insulating layer (34 between leftmost 18:[14, 16]) and the second upper insulating layer (36/38/40 between rightmost 18:[14, 16]) comprising different dielectric materials (e.g., SiONC, SiCN respectively, etc.), the first lower insulating layer (34 between leftmost 18:[14, 16]) having a width (implicit), the first upper insulating layer (36 between leftmost 18:[14, 16]) having a width (implicit), the second lower insulating layer (34 between rightmost 18:[14, 16]) having a width (implicit), the second upper insulating layer (36/38/40 between rightmost 18:[14, 16]) having a width (implicit) {Fig. 6; ¶0029, 0030}; and
forming a first metal gate (70 around leftmost 18:[14, 16]) and a second metal gate (70 around rightmost 18:[14, 16]), the first metal gate (70 around leftmost 18:[14, 16]) formed around the first nanostructures (leftmost 18:[14, 16]), the second metal gate (70 around rightmost 18:[14, 16]) formed around the second nanostructures (rightmost 18:[14, 16]), the first metal gate (70 around leftmost 18:[14, 16]) extending along a sidewall of the first lower insulating layer (34 between leftmost 18:[14, 16]) of the first insulating fin (34, 36 between leftmost 18:[14, 16]), the first metal gate (70 around leftmost 18:[14, 16]) extending along a top surface and sidewall of the first upper insulating layer (36 between leftmost 18:[14, 16]) of the first insulating fin (34, 36 between leftmost 18:[14, 16]), the second metal gate (70 around rightmost 18:[14, 16]) extending along a sidewall of the second lower insulating layer (34 between rightmost 18:[14, 16]) of the second insulating fin (34, 36, 38, 40 between rightmost 18:[14, 16]) the second metal gate (70 around rightmost 18:[14, 16]) extending along a top surface and sidewall of the second upper insulating layer (36/38/40 between rightmost 18:[14, 16]) of the second insulating fin (34, 36, 38, 40 between rightmost 18:[14, 16]) {Figs. 25B, 25D; ¶0074}.
Jhan does not teach the first lower insulating layer having a first width, the first upper insulating layer having the first width, the second lower insulating layer having a second width, the second upper insulating layer having the second width.
However, the instant application does not identify any criticality or operational difference obtained by having: (1) the same first width for the first lower insulating layer and the first upper insulating layer and (2) the same second width for the second lower insulating layer and the second upper insulating layer. [Where] the dimensional limitations [of the claimed device] d[o] not specify a device which perform[s] and operate[s] any differently from the prior art, a difference between such claimed dimensional limitations and those existing in the prior art is insufficient to render the claimed device non-obvious over the prior art. Gardner v. TEC Systems, Inc., 725 F.2d 1338, 1345, 1349 (Fed. Cir. 1984); see also MPEP 2144.04(IV)(A).
Moreover, Jhan teaches in Fig. 6 that: (1) the widths for the first lower insulating layer (34 between leftmost 18:[14, 16]) and the first upper insulating layer (36 between leftmost 18:[14, 16]) are close in size and (2) the widths for the second lower insulating layer (34 between rightmost 18:[14, 16]) and the second upper insulating layer (36/38/40 between rightmost 18:[14, 16]) are close in size. [A] prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close. MPEP §2144.05(I).
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhan using Jhan as the English Translation as applied to claim 22 above, and further in view of Peng.
Regarding claim 23, Jhan teaches the method of claim 22, and Jhan further teaches further comprising forming a first dummy gate (46 around leftmost 18:[14, 16]) and a second dummy gate (46 around rightmost 18:[14, 16]) {Fig. 10; ¶0034}.
Jhan does not teach wherein forming the first dummy gate and the second dummy gate comprises:
depositing a dummy gate layer over the first insulating fin and the second insulating fin;
etching a first recess in the dummy gate layer and the first insulating fin with a first etching process; and
etching a second recess in the dummy gate layer and the second insulating fin with a second etching process, the second etching process different from the first etching process.
Peng teaches wherein forming the first dummy gate (leftmost portion of 32 along axes B; Fig. 6) and the second dummy gate (rightmost portion of 32 along axes B; Fig. 6) comprises:
depositing a dummy gate layer (32) over the first insulating fin (leftmost trench) and the second insulating fin (rightmost trench) {Fig. 6; ¶0044};
etching a first recess in the dummy gate layer (32) and the first insulating fin (leftmost trench) with a first etching process {Figs. 8A, 8B; ¶0053}; and
etching a second recess in the dummy gate layer (32) and the second insulating fin (leftmost trench) with a second etching process, the second etching process different from the first etching process {Figs. 8A, 8B; ¶0053, the dummy gates 32 are removed, such as by … etch processes; i.e., Peng teaches in paragraph [0053] that both the first and second insulating fins are etched by multiple etch processes (i.e., not by multiple instances of the same etch process)}.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jhan’s method based on the teachings of Peng for forming the first dummy gate and the second dummy gate as identified above because applying a known improvement technique in the same way (as taught by Peng) to a known method (as taught by Jhan) to produce predictable results (e.g., etching of dielectric materials having different properties) is within the ordinary skill in the art.
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhan using Jhan as the English Translation in view of Peng as applied to claim 23 above, and further in view of Ching.
Regarding claim 24, Jhan as modified by Peng teaches the method of claim 23, but Jhan does not teach wherein the first etching process selectively etches a material of the first upper insulating layer at a faster rate than a material of the second upper insulating layer, and the second etching process selectively etches the material of the second upper insulating layer at a faster rate than the material of the first upper insulating layer.
Ching teaches in Figs. 5-7 and paragraphs [0038] and [0039] etching a first recess (304a) in a first insulating fin (fin corresponding to 304a) with a first etching process, the first etching process selectively etching the second dielectric material (106a; ¶0020) at a faster rate than the first dielectric material (502; ¶0038); and etching a second recess (304c) in the second insulating fin (fin corresponding to 304c) with a second etching process, the second etching process selectively etching the first dielectric material (502) at a faster rate than the second dielectric material (106a). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jhan’s method as modified by Peng based on the teachings of Ching – such that the first etching process selectively etches a material of the first upper insulating layer at a faster rate than a material of the second upper insulating layer, and the second etching process selectively etches the material of the second upper insulating layer at a faster rate than the material of the first upper insulating layer – because a uniformity of fin density is improved and [such] provides better structur[al] fidelity. Ching ¶0016.
Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhan using Jhan as the English Translation as applied to claim 22 above, and further in view of Bi.
Regarding claim 25, Jhan teaches the method of claim 22, but Jhan does not teach wherein forming the first insulating fin and the second insulating fin comprises:
forming a first dielectric material between the first nanostructures and between the second nanostructures; and
converting the first dielectric material between the second nanostructures to a second dielectric material while the first dielectric material remains between the first nanostructures.
Bi teaches in Figs. 3 and 4 and paragraphs [0043] and [0044] wherein forming a first insulating fin and a second insulating fin comprises: forming a first dielectric material (300) between a first set of fin structures (106, 114) and between a second set of fin structures (106, 114); and converting the first dielectric material (300) between the second set of fin structures (106, 114) to a second dielectric material (400) while the first dielectric material (300) remains between the first set of fin structures (106, 114) {see annotated copy of Bi’s Figs. 3 and 4 below}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jhan’s method based on the teachings of Bi – such that forming the first insulating fin and the second insulating fin comprises: forming a first dielectric material between the first fin structures and between the second fin structures; and converting the first dielectric material between the second fin structures to a second dielectric material while the first dielectric material remains between the first fin structures – so the second dielectric material has a higher etch resistance for protecting the underlying materials during a subsequent etching operation. Bi ¶0042. A consequence of this modification is that Bi’s first and second fin structures become first and second nanostructures.
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Claim(s) 26 and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhan using Jhan as the English Translation in view of Bi as applied to claim 25 above, and further in view of Peng.
Regarding claim 26, Jhan as modified by Bi teaches the method of claim 25, but Jhan does not teach wherein converting the first dielectric material to the second dielectric material comprises performing a radical treatment to modify a composition of the first dielectric material.
Peng teaches in Figs. 2 and 3 and paragraph [0033] converting a first dielectric material (24) to a second dielectric material (26) comprises performing a radical treatment to modify a composition of the first dielectric material (24). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jhan’s method as modified by Bi based on the teachings of Peng – such that converting the first dielectric material to the second dielectric material comprises performing a radical treatment to modify a composition of the first dielectric material – because an oxygen radical … may have better penetration. Peng ¶0033. Moreover, applying a known improvement technique in the same way (as taught by Peng) to a known method (as taught by Jhan and Bi) to produce predictable results (e.g., a change of k-value and/or etch resistance) is within the ordinary skill in the art.
Regarding claim 28, Jhan as modified by Bi teaches the method of claim 25, but Jhan does not teach wherein converting the first dielectric material to the second dielectric material comprises performing an anneal process to increase a porosity of the first dielectric material.
Peng teaches in Figs. 2 and 3 and paragraphs [0033] and [0034] converting the first dielectric material (24) to the second dielectric material (26) comprises performing an anneal process to increase a porosity of the first dielectric material (24) {Figs. 2, 3; ¶0033, 0034; dielectric (26) is necessarily more porous than dielectric (24) because the former has greater volume and less density than the latter}. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jhan’s method as modified by Bi based on the teachings of Peng – such that converting the first dielectric material to the second dielectric material comprises performing an anneal process to increase a porosity of the first dielectric material – for changing the k-value and/or etch resistance of the second dielectric. Peng ¶0035. Moreover, applying a known improvement technique in the same way (as taught by Peng) to a known method (as taught by Jhan and Bi) to produce predictable results (e.g., a change of k-value and/or etch resistance) is within the ordinary skill in the art.
Claim(s) 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhan using Jhan as the English Translation in view of Bi as applied to claim 25 above, and further in view of Citla et al. (US20210090883A1).
Regarding claim 27, Jhan as modified by Bi teaches the method of claim 25, but Jhan does not teach wherein converting the first dielectric material to the second dielectric material comprises performing a radical treatment to increase a density of the first dielectric material.
In an analogous art, Citla et al. (20210090883) teaches in Figs. 4A and 4B and paragraphs [0053] and [0058] converting the first dielectric material (404) to the second dielectric material (404 and/or 406) comprises performing a radical treatment to increase a density of the first dielectric material (404). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jhan’s method as modified by Bi based on the teachings of Citla – such that converting the first dielectric material to the second dielectric material comprises performing a radical treatment to increase a density of the first dielectric material – to: (1) densify a deposited flowable film material {¶0006} and (2) maintain[] the flowability of the dielectric material improving gap fill from the bottom up advantageously increasing device yield and maintaining the dielectric constant of the deposited material {¶0019}.
Claim(s) 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhan using Jhan as the English Translation in view of Bi as applied to claim 25 above, and further in view of LaVoie and Pham.
Regarding claim 29, Jhan as modified by Bi teaches the method of claim 25, but Jhan does not teach wherein converting the first dielectric material to the second dielectric material comprises performing a radical treatment to decrease a stress of the first dielectric material.
LaVoie teaches that the SiC/SiCN stoichiometry of the as-deposited film may be tuned with a nitrogen or amine plasma {¶0046} to modify the film’s internal stress {¶0045}. LaVoie further teaches in paragraph [0086] that the plasma creates free electrons that collide with reactant molecules to form radical species. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jhan’s method as modified by Bi based on the teachings of LaVoie – such that converting the second upper insulating layer to the second dielectric material comprises performing a radical treatment to decrease a stress of the first dielectric material – so that the trenches may be filled with highly stressed dielectric materials to isolate the fins and induce an appropriate stress in the fins to increase device performance capability. Pham col. 2 ll. 42-45.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891