The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-14, 17-18 and 21-24 are rejected under 35 U.S.C. 103 as being unpatentable over Takei et al. (2005/0082640) in view of Mori et al. (EP 0338312 B1).Regarding claims 1, 17 and 21, Takei et al. teach in figure 1b and related text an insulated gate bipolar transistor (IGBT) comprising:
a semiconductor substrate 100 having a top surface extending in a horizontal plane;
a collector region 15/2 of a first conductive type P disposed on and in direct contact with the substrate wherein the collector region comprises a continuous region of the first conductive type and is free of regions of a second conductive type;
a collector electrode 16 disposed on and in direct contact with the collector region;
a buffer region (the bottom region of element 1) of the second conductive type N opposite to the first conductive type disposed on the collector region;
a drift region (the top region of element 1) of the second conductive type N disposed on the buffer region;
a body region 3 of the first conductive type P disposed in the drift region; and
at least one source region 6 of the second conductive type N disposed in the body region,
wherein the collector electrode 16 is spaced apart from the buffer region 1 in the horizontal plane.
Takei et al. do not teach having a three-dimensional (3D) isolation region comprising a silicon compound having a bottom portion and a sidewall portion, wherein the collector region disposed on and in direct contact with the 3D isolation region.
Mori et al. teach in figure 7A and related text a three-dimensional (3D) isolation region (located between substrate 2 and collector 21) comprising a compound having a bottom portion and a sidewall portion, wherein the collector region 21 disposed on and in direct contact with the 3D isolation region.
Mori et al. and Takei et al. are analogous art because they are directed to IGBT semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Takei et al. because they are from the same field of endeavor.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a three-dimensional (3D) isolation region having a bottom portion and a sidewall portion, wherein the collector region disposed on and in direct contact with the 3D isolation region, as taught by Mori et al., and to form the three-dimensional (3D) isolation region comprising a silicon compound, in Takei et al.’s device, in order to improve isolation of the device and in order to simplify the processing steps of the device.
In the combined device, the 3D isolation region and the top surface of the semiconductor substrate enclose the collector region, the buffer region, the drift region, the body region, and the at least one source region.
Regarding claim 17, the combined device teaches substantially the entire claimed structure including a 3D isolation region having a bottom portion and a sidewall portion and wherein the sidewall portion separates the collector region, the buffer region, the drift region, the body region, and the at least one source region from the semiconductor substrate in the horizontal plane, while the bottom portion separates the collector region, the buffer region, the drift region, the body region, and the at least one source region from the semiconductor substrate in a vertical direction. The combined device does not teach an integrated circuit (IC) embedded in the semiconductor substrate. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to embed an integrated circuit (IC) in the semiconductor substrate in prior art’s device in order to reduce the size of the device.
Regarding claims 2 and 22, in the combined device, the sidewall portion extends upwardly from a perimeter of the bottom portion and reaches the top surface of the semiconductor substrate.
Regarding claim 3, in the combined device, the sidewall portion and the bottom portion define an angle.
Regarding claims 4-5, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the angle is between 85 degrees and 120 degrees in prior art’s device in order to adjust the device characteristics according to the requirements of the application at hand.
Regarding claims 6-7, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the sidewall portion and the bottom portion define a round corner wherein a radius of the round corner is larger than 0.05 pm, in prior art’s device in order to adjust the device characteristics according to the requirements of the application at hand.
Regarding claims 8-10, in the combined device, the sidewall portion encircles the collector region, the buffer region, the drift region, the body region, and the at least one source region in the horizontal plane, and wherein the collector region and the top surface of the semiconductor substrate enclose the buffer region, the drift region, the body region, and the at least one source region, and wherein the buffer region and the top surface of the semiconductor substrate enclose the drift region, the body region, and the at least one source region.
Regarding claims 11-12, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the silicon compound to be silicon dioxide and silicon nitride in prior art’s device in order to simplify the processing steps of making the device.
Regarding claim 13, Takei et al. teach in figure 1b and related text that the semiconductor substrate is a silicon substate.
Regarding claim 14, Takei et al. teach in figure 1b and related text at least one emitter electrode 6 disposed on the top surface of the semiconductor substrate; at least one collector electrode 14 disposed on the top surface of the semiconductor substrate; at least one gate dielectric structure 7 disposed on the top surface of the semiconductor substrate; and at least one gate electrode 8 disposed on the at least one gate dielectric structure.
Regarding claim 18, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the integrated circuit lateral to the IGBT in the horizontal plane, and the integrated circuit and the IGBT are separated by a shallow trench isolation structure and the 3D isolation region in prior art’s device in order to prevent current interference from the IGBT and the IC.
Regarding claim 23, in the combined device, the sidewall portion encircles the collector region, the buffer region, the drift region, the body region, and the at least one source region in the horizontal plane.
Regarding claim 24, in the combined device, the collector region and the top surface of the semiconductor substrate enclose the buffer region, the drift region, the body region, and the at least one source region.
Response to Arguments
Applicants argue that prior art does not teach that the collector electrode is spaced apart from the buffer region in the horizontal plane, because “Mori explicitly teaches that the collector electrode (4) must short- circuit the p-type collector (11) and the n-type buffer (34/21). Mori states this is essential to "shorten the lifetime of minority carriers thereby enhancing the switching speed" and to prevent latch-up. In contrast, amended claim 1 recites that the collector electrode is "spaced apart from the buffer region in the horizontal plane". This structural limitation physically prevents the short- circuiting that Mori teaches is necessary”.
Mori was not cited to teach that the collector electrode is spaced apart from the buffer region in the horizontal plane. Mori was cited to teach an artisan that Takei et al.’s structure can be surrounded by a three-dimensional (3D) isolation region which comprises a silicon compound having a bottom portion and a sidewall portion, and wherein the collector region disposed on and in direct contact with the 3D isolation region.
The primary reference to Takei teaches collector electrode 16 is spaced apart from the buffer region 1 in the horizontal plane, as required by the claims.
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O.N. /ORI NADAV/
4/27/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800
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