DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
The following office action is in response to the amendment and remarks filed on 1/12/26.
Claims 1-15 are cancelled.
Claims 16-35 are pending and subject to examination at this time.
Response to Arguments
Regarding claim 16 and the Kitaichi reference:
Applicant's arguments with respect to claim 16 have been considered but are moot in view of the new ground(s) of rejection.
Regarding claim 16 and the Daubenspeck reference:
Applicant's arguments filed 1/12/16 have been fully considered but they are not persuasive.
Applicant submits at page 8:
Thus, Daubenspeck teaches that a conductive path is formed between the test structure 221 and the probe pad 255c. If there is no conductive path (i.e., the metal wires and vias of the metal interconnect 217 are not electrically connected), the test structure 221 would be useless.
Thus, to modify Werner by using Daubenspeck's test structure 221 with the metal interconnect 217 would render Werner, the prior art invention being modified, unsatisfactory for its intended purpose…
In response-
The 35 USC 103 rejection does not propose to modify Werner’s test structures with Daubenspeck’s test structures, as asserted by the Applicant.
The 35 USC 103 rejection proposes to modify Werner by forming his test structures in a scribe line region.
Applicant submits at page 9:
Therefore, a person skilled in the art would not be motivated to combine the teachings of Werner and Daubenspeck, because the test structure of Werner would not form an electrical connection between the test structure of Daubenspeck and the top of the stack. As a result, the wafer-level testing taught by Daubenspeck cannot be performed.
In response-
In Werner’s fig. 3, at least one of the vias (107) forms an electrical connection to metal-filled trenches (103) so an electrical connection is made.
The 35 USC 103 rejection does not propose to modify Werner with the wafer-level testing taught by Daubenspeck. The primary reference, Werner already performs wafer-level testing as disclosed in fig. 3, so there is no proposal to apply Daubenspeck’s wafer-leveling testing to Werner.
Relevant Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Liao et al., US Publication No. 2019/0181063 (e.g. See figs. 1-3 disclosing test structures 110 in a scribe line region 101.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 16 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Werner et al., US Publication No. 2008/0131796 A1 (of record) in view of Kitaichi et al, JP 2014007351 A (see attached English machine translation)
Regarding claim 16:
Referring to MPEP § 2141, Examination Guidelines for Determining Obviousness Under 35 U.S.C. 103:
“A person of ordinary skill in the art is also a person of ordinary creativity, not an automaton.” KSR, 550 U.S., 82 USPQ2d at 1397. “[I]n many cases a person of ordinary skill will be able to fit the teachings of multiple patents together like pieces of a puzzle.” Office personnel may also take into account “the inferences and creative steps that a person of ordinary skill in the art would employ.”, 82 USPQ2d at 1396.
Werner does not expressly teach all the features of claim 16 in a single figure.
However, one of ordinary skill in the art, who is a person of ordinary creativity, modifying the test features (251) in fig. 2 to be the different pattern densities shown in the semiconductor device 100 in fig. 1 would arrive at the claim limitations.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to make this modification in order to advantageously detect if a chemical mechanical polishing (CMP) process is within specifications (e.g. see fig. 3, step 333). See Werner at para. [0034], [0041].
Thus, Werner teaches:
16. A method, comprising (see figs. 1-3):
forming one or more dielectric layers (201/203/204+ dielectric layer of 251; e.g. see “dielectric layers” and “lower lying material layer” of 251 at para. [0035]) including a test structure (251 in fig. 2; 110A, 110B in fig. 1) and a plurality of conductive features (e.g. “metal material” in layer 203, para. [0039]; shown as vias in fig. 2e) over a first substrate (101 in fig. 1; 201 in fig. 2)…
forming a dielectric layer (103 in fig. 1) on the one or more dielectric layers…;
forming a first photoresist layer (105 in fig. 1) over the dielectric layer;
patterning the first photoresist layer by focusing a light (106 in fig. 1 is photolithography) on a first image plane (e.g. “focus plane” at para. [0031], [0035]);
transferring a pattern of the first photoresist layer to the dielectric layer (e.g. pattern transfer forms openings 107, 108 in fig. 1);
forming conductive features (e.g. “interconnect structures”, para. [0011]) in the dielectric layer;
performing a process to identify defects (e.g. See fig. 3, steps 332-333); and
patterning a photoresist layer disposed over a second substrate by focusing the light on a second image plane different from the first image plane using information provided by the test structure (e.g. See fig. 3, feedback loop of steps 335 to steps 330-331. See para. [0041] disclosing, “In this case, the corresponding measurement results obtained in step 332 may be used, with or without a preceding evaluation, as respective feedback data for the focus controller 336, which may then supply updated focus parameter values to be used for further substrates to be processed in the module 330.” Also see “focus plane” at para. [0031], [0035]). See Werner at para. [0001] – [0044], figs. 1-3.
Further regarding claim 16:
Werner is silent:
wherein the test structure is disposed in a scribe line located between dies;
wherein the dielectric layer is formed in the scribe line and over the dies.
In an analogous art, Kitaichi teaches:
(see figs. 2, 4, 6 and 8) wherein the test structure (8; e.g. see page 13 “Alternatively, a TEG (Test Element Group) pattern 8 (for measurement) is provided (usually provided in plural).“) is disposed in a scribe line (4) located between dies (1s, 2a, 2b);
wherein the dielectric layer (6s) is formed in the scribe line (4) and over the dies (1s, 2a, 2b). See Kitaichi at pages 13-15.
Regarding claims 18:
Werner further teaches:
“wherein the defects comprise first defects located over the test structure and second defects…(e.g. The first and second defects are the “different heights” from CMP at para. [0031] – [0034])”.
Werner is silent that the second defects are ”located in regions without the test structure”.
However, it would have been obvious to one of ordinary skill in the art to form the second defects “located in regions without the test structure” because Werner teaches there may be “substantially metal-free regions” or “0%”. See Werner at para. [0039].
Regarding claim 19:
Werner further teaches:
“wherein the second defects are greater than a threshold number” (e.g. See fig. 3 the advanced process control (APC, 336) adjusts focus parameter values based on a “threshold value” comparison at step 333. See Werner at para. [0041].)
Werner further teaches:
20. The method of claim 18, the information provided by the test structure comprises thickness differences among portions of the test structure (e.g. “different heights” at para. [0031] – [0034]).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Werner with the teachings of Kitaichi because the test structures (TEG) can be simultaneously removed with the dicing of the wafer. See Kitaichi fig. 12, pages 15-16, “Even if there is a TEG containing a metal film on the dicing line, it can be processed without any problem.”
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Werner in view of Kitaichi, as applied to claim 16 above, and further in view of Abdo et al., US Publication No. 2019/0227427 A1 (of record).
Regarding claim 17:
Werner and Kitaichi teach all the limitations of claim 16 above, but are silent the light is EUV light.
In an analogous art, Abdo teaches “In contrast to conventional lithography techniques, EUV lithography utilizes extreme ultraviolet (EUV) light to transfer a circuit reflective portions of an EUV photomask (referred to herein as an “EUV mask”) to a semiconductor die”, para. [0003].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Werner with the teachings of Lin because “Extreme ultraviolet (EUV) lithography enables the fabrication of semiconductor devices having critical dimensions less than 28 nanometers (nm) in width”. See Abdo at para. [0003].
Claim(s) 21-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Werner et al., US Publication No. 2008/0131796 A1 (of record) in view of Kitaichi et al, JP 2014007351 A (see attached English machine translation) and Lin, US Patent No. 6,149,830 (of record).
Regarding claim 21:
Referring to MPEP § 2141, Examination Guidelines for Determining Obviousness Under 35 U.S.C. 103:
“A person of ordinary skill in the art is also a person of ordinary creativity, not an automaton.” KSR, 550 U.S., 82 USPQ2d at 1397. “[I]n many cases a person of ordinary skill will be able to fit the teachings of multiple patents together like pieces of a puzzle.” Office personnel may also take into account “the inferences and creative steps that a person of ordinary skill in the art would employ.”, 82 USPQ2d at 1396.
Werner does not expressly teach all the features of claim 21 in a single figure.
However, one of ordinary skill in the art, who is a person of ordinary creativity, modifying the vias in layer 203 of fig. 2e to be the different pattern densities shown in the semiconductor device 100 in fig. 1 would arrive at the claim limitations.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to make this modification in order to advantageously detect if a chemical mechanical polishing (CMP) process is within specifications (e.g. see fig. 3, step 333). See Werner at para. [0034], [0041].
Thus, Werner teaches:
21. A method, comprising (see figs. 1-3; also see fig. 2e annotated below for claim 21):
depositing a first dielectric layer (203 in fig. 2; analogous to 102 in fig. 1) over a substrate (201 in fig. 1; analogous to 101 in fig. 1);
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forming a first conductive feature (e.g. 1st conductive feature labeled) in the first dielectric layer in a first portion (e.g. region 210C) of a test structure, wherein the first conductive feature has a first dimension…;
forming a second conductive feature (e.g. 2nd conductive feature labeled) in the first dielectric layer in a second portion (e.g. region 210D) of the test structure, wherein the second conductive feature has a second dimension greater than the first dimension; and
performing a first chemical mechanical polishing process (e.g. CMP at para. [0009] – [0010], para. [0033] – [0034]) on the test structure,
wherein the thickness of the first portion (e.g. region 210C) of the test structure is less than a thickness of a third portion (e.g. region 210A) of the test structure (e.g. The thickness of first portion 210C is less than a thickness of third portion 210A because Werner teaches in fig. 1B that higher density areas experience greater removal in a CMP process at para. [0009] – [0010]), and
the third portion (e.g. region 210A) of the test structure is free of conductive features.
Regarding claim 21:
Werner is silent:
wherein the test structure is disposed in a scribe line located between dies;
In an analogous art, Kitaichi teaches:
(see figs. 2, 4, 6 and 8) wherein the test structure (8; e.g. see page 13 “Alternatively, a TEG (Test Element Group) pattern 8 (for measurement) is provided (usually provided in plural).“) is disposed in a scribe line (4) located between dies (1s, 2a, 2b). See Kitaichi at pages 13-15.
Further regarding claim 21:
Werner is silent:
wherein a thickness of the first portion of the test structure is greater than a thickness of the second portion of the test structure.
In an analogous art, Lin teaches (see figs. 3-4) larger metal features experience greater dishing under a chemical mechanical polishing process (CMP). See Lin at col 4, ln 45–55.
In Werner’s fig. 2e, the second portion (210D) of the test structure is a larger metal feature so it will experience greater dishing compared to the smaller metal feature in the first portion (210C) of the test structure.
It would have been obvious to ordinary skill in the art to form in Werner’s fig. 23 “a thickness of the first portion (210C) of the test structure is greater than a thickness of the second portion (210D) of the test structure” because Lin teaches it experiences less dishing under CMP.
Werner further teaches:
22. The method of claim 21, further comprising forming a third conductive feature (e.g. In fig. 2e, there are a plurality of 1st conductive features) in the first portion of the test structure, wherein the first and third conductive features have a pitch smaller (e.g. pitch between 1st conductive features in region 210C) than the second dimension of the second conductive feature (e.g. 2nd conductive feature in region 210D), fig. 2e.
23. The method of claim 22, wherein the second dimension of the second conductive feature (e.g. 2nd conductive feature in region 210D) is about 3 times to about 5 times the pitch of the first and third conductive features smaller (e.g. pitch between 1st conductive features in region 210C), fig. 2e.
Regarding claim 24-27:
The limitations of forming additional conductive features and performing a second chemical mechanical polishing process (CMP) is obvious because Werner teaches forming additional, upper level metal features (107, 108) over lower level features (103, 104) in fig. 1b-1c. Also see additional, upper level metal features (251) over lower level features (e.g. conductive features in layer 203) in fig. 2e.
Thus, Werner teaches:
24. The method of claim 21, further comprising depositing a second dielectric layer (103 in fig. 1; 204 in fig. 2e) on the first dielectric layer....
Werner is silent:
wherein the second dielectric layer is formed in the scribe line and over the dies.
In an analogous art, Kitaichi teaches:
(see figs. 2, 4, 6 and 8) wherein the second dielectric layer (6s) is formed in the scribe line (4) and over the dies (1s, 2a, 2b). See Kitaichi at pages 13-15.
Werner further teaches:
25. The method of claim 24, further comprising forming a fourth conductive feature (107 in fig. 1; 251 in fig. 2) in the first portion of the test structure, wherein the fourth conductive feature has a third dimension.
26. The method of claim 25, further comprising forming a fifth conductive feature (108 in fig. 1; 251 in fig. 2) in the second portion of the test structure, wherein the fifth conductive feature has a fourth dimension greater than the third dimension (e.g. Werner teaches the regions 210A-210D in fig. 2 can have conductive features of different dimensions in the disclosure at para. [0034] “For example, the dimension and/or the density of respective features, such as lines and the like, may be selected differently in the first and second areas 210A, 210B…)
27. The method of claim 26, further comprising performing a second chemical mechanical polishing process on the test structure (e.g. A second CMP results in height difference between 107, 108 in fig. 1c. Also see para. [0009] – [0010] and para. [0034] disclosing “For example, the dimension and/or the density of respective features…may thus result in a different degree of height level due to a certain degree of pattern dependence…of a CMP process, as previously explained with reference to the semiconductor device 100.”)
28. The method of claim 21, wherein the first conductive feature comprises a barrier layer and a conductive material formed on the barrier layer, para. [0006], [0008] – [0009].
Regarding claim 29:
Referring to MPEP § 2141, Examination Guidelines for Determining Obviousness Under 35 U.S.C. 103:
“A person of ordinary skill in the art is also a person of ordinary creativity, not an automaton.” KSR, 550 U.S., 82 USPQ2d at 1397. “[I]n many cases a person of ordinary skill will be able to fit the teachings of multiple patents together like pieces of a puzzle.” Office personnel may also take into account “the inferences and creative steps that a person of ordinary skill in the art would employ.”, 82 USPQ2d at 1396.
Werner teaches:
29. A method, comprising (see figs. 1-3; also see fig. 2e annotated below for claim 21):
depositing a first dielectric layer over a substrate;
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forming a plurality of first conductive features (e.g. 1st conductive feature labeled) in the first dielectric layer (203) in a first portion (210B) of a test structure;
forming a plurality of second conductive features (e.g. 2nd conductive feature labeled) in the first dielectric layer (203) in a second portion (210C) of the test structure;
forming a third conductive feature (e.g. 3rd conductive feature labeled) in the first dielectric layer (203) in a third portion (210D) of the test structure, wherein the test structure comprises a fourth portion (210A) that is free of conductive features in the first dielectric layer (203);
depositing a second dielectric layer (e.g. dielectric layer of 251; e.g. see “dielectric layers” and “lower lying material layer” of 251 at para. [0035]) over the first dielectric layer;
forming a plurality of fourth conductive features (251, e.g. 4th conductive feature labeled) in the second dielectric layer (e.g. dielectric of 251) in the first portion (210B) of the test structure;
forming a plurality of fifth conductive features (251, e.g. 5th conductive feature labeled) in the second dielectric layer (e.g. dielectric of 251) in the second portion (210C) of the test structure;
forming a sixth conductive feature (251, e.g. 6thconductive feature labeled) in the second dielectric layer in the third portion (210D) of the test structure; and
forming a plurality of seventh conductive features (251, e.g. 7thconductive feature labeled) in the second dielectric layer in the fourth portion (210A) of the test structure,
wherein a thickness of the fourth portion of the test structure is greater than a thickness of the first portion of the test structure, which is greater than a thickness of the second portion of the test structure (e.g. The thickness of fourth portion 210A is greater than a thickness of the first portion 210B, which is greater than a thickness of the second portion 210C because (i) Werner teaches in fig. 1B that higher density areas experience greater removal in a CMP process at para. [0009] – [0010]; and (ii) and Werner teaches in fig. 1c the height differences in the lower layer 102 transfer to the upper layer 103 during subsequent lithographic processing at para. [0010], “Thus, during a lithography process 106, the difference in planarity in the regions 110A, 110B, as indicated by 111, may cause respective non-uniformities of the imaging process and subsequently respective non-uniformities during the patterning of the dielectric layer 103.” Also see para. [0031], “For example, the areas 210A, 210B may represent areas of different height levels with respect to at least one underlying portion or sub-layer of the material layer 203, which may intentionally be generated in order to represent a corresponding range of different height levels in corresponding product areas of an actual microstructure device.”).
Regarding claim 29:
Werner is silent:
wherein the test structure is disposed in a scribe line located between dies;
wherein the second dielectric layer is formed in the scribe line and over the dies.
In an analogous art, Kitaichi teaches:
(see figs. 2, 4, 6 and 8) wherein the test structure (8; e.g. see page 13 “Alternatively, a TEG (Test Element Group) pattern 8 (for measurement) is provided (usually provided in plural).“) is disposed in a scribe line (4) located between dies (1s, 2a, 2b);
wherein the second dielectric layer (6s) is formed in the scribe line (4) and over the dies (1s, 2a, 2b). See Kitaichi at pages 13-15.
Further regarding claim 29:
Werner is silent:
which is greater than a thickness of the third portion of the test structure
In an analogous art, Lin teaches (see figs. 3-4) larger metal features experience greater dishing under a chemical mechanical polishing process (CMP). See Lin at col 4, ln 45–55.
In Werner’s fig. 2e, the third portion (210D) of the test structure is the largest metal feature so it will experience the greatest dishing compared to the smaller metal feature in the first portion (210B) and second portion (210C) of the test structure.
It would have been obvious to one of ordinary skill in the art to form in Werner’s fig. 23 “a thickness of the fourth portion (210A) of the test structure is greater than a thickness of the first portion (210B) of the test structure, which is greater than a thickness of the second portion (210C) of the test structure, which is greater than a thickness of the third portion (210D) of the test structure” because Lin teaches it experiences less dishing under CMP.
Werner further taches:
30. The method of claim 29, further comprising depositing a third dielectric layer (204) on the first dielectric layer (203), wherein the second dielectric layer (e.g. dielectric of 251) is deposited on the third dielectric layer (204), fig. 2e.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Werner with the teachings of Kitaichi because the test structures (TEG) can be simultaneously removed with the dicing of the wafer. See Kitaichi fig. 12, pages 15-16, “Even if there is a TEG containing a metal film on the dicing line, it can be processed without any problem.”
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Werner with the teachings of Lin because “…when the metal is a large surface that is part of a patterned metal design embedded in a dielectric on which other layers and a substrate are attached, the use of a CMP process to polish the patterned metal creates a severe amount of dishing in the larger metal features.” See Lin at col 1, ln 33–37.
Claim(s) 31-34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Werner in view of Kitaichi and Lin as applied to claim 29 above, and further in view of Satya et al., US Publication No. 2002/0187582 A1 (of record).
Regarding claim 31:
Werner, Kitaichi and Lin teach all the limitations of claim 29 above, but are silent regarding conductive features in the third dielectric.
However, forming conductive features in the third dielectric (204) is considered duplication of essential working parts, -i.e. duplicating the formation of conductive features Werner has already formed in layer (203).
Thus, it would have been obvious to one having ordinary skill in the art to form ”an eighth conductive feature in the third dielectric layer in the second portion of the test structure, wherein the plurality of fifth conductive features are disposed over the eight conductive feature”, since duplication of essential working parts of a device involve only routine skill in the art. See MPEP 2144.04, Legal Precedent as Source of Supporting Rationale, VI. Reversal, Duplication, or Rearrangement of Parts.
Furthermore, in an analogous art, Satya teaches (see fig. 10, also see fig. 13) a test structure can comprising comprise conductive features (M!-M4) formed in dielectric layers (444). Satya teaches four dielectric layers and each of the dielectric layers has a conductive feature. See Satya at para. [0089], para. [0131] – [0132].
The conductive feature (M3) is sandwiched between (M2) and (M4). Thus, Satya teaches (see fig. 10) ”an eighth conductive feature (M3) in the third dielectric layer (e.g. dielectric layer 444 at level M3) in the second portion of the test structure, wherein the plurality of fifth conductive features (M4) are disposed over the eighth conductive feature (M3)”, as recited in the claim.
Satya further teaches:
32. The method of claim 31, (see fig. 10 annotated below) wherein the plurality of fifth conductive features (M4) comprises an edge conductive feature (e.g. edge dual damascene) disposed over an edge portion of the eight conductive feature (M3) and a center conductive feature (e.g. center via of dual damascene) disposed over a center portion of the eighth conductive feature (M3)
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Satya further teaches:
33. The method of claim 32, wherein a thickness of the edge conductive feature (e.g. edge dual damascene) is less than a thickness of the center conductive feature (e.g. center via of dual damascene), fig. 10
Regarding claim 34:
It would have been obvious to one having ordinary skill in the art to form ” a nineth conductive feature in the third dielectric layer in the third portion of the test structure, wherein the sixth conductive feature is disposed over the nineth conductive feature”, since duplication of essential working parts of a device involve only routine skill in the art. See MPEP 2144.04, Legal Precedent as Source of Supporting Rationale, VI. Reversal, Duplication, or Rearrangement of Parts.
Furthermore, in an analogous art, Satya teaches (see fig. 10, also see fig. 13) a test structure can comprising comprise conductive features (M!-M4) formed in dielectric layers (444). Satya teaches four dielectric layers and each of the dielectric layers has a conductive feature. See Satya at para. [0089], para. [0131] – [0132].
The conductive feature (M3) is sandwiched between (M2) and (M4). Thus, Satya teaches (see fig. 10) “a nineth conductive feature (M3) in the third dielectric layer (e.g. dielectric layer 444 at level M3) in the third portion of the test structure, wherein the sixth conductive feature (M4) is disposed over the nineth conductive feature (M3)”.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Werner with the teachings of Satya because “The defect test structures are fabricated such that they are sensitive to defects that occur in IC product, but are designed so that the presence of defects is more readily ascertained.” (e.g. Satya para. [0007], also see para. [0006]); “One example of a defect test structure is found in the Copper CMP Test Mask Set designed at MIT. This test mask set is designed to quantify the dependence of the resulting copper line profile on parameters such as line pitch, line width and line aspect ratio” (e.g. Satya at para. [0008]); and “During the electron beam inspection of the scanned swath, a proximal end of the M3 interconnect may be scanned. Similarly, as shown in FIG. 10…shorts between the M1 and M2 interconnects, can still be inspected through scan element 454” (Satya at para. [0131])
Claim(s) 35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Werner in view of Kitaichi and Lin as applied to claim 29 above, and further in view of Lo, US Publication No. 2022/0165618 A1 (of record).
Regarding claim 35:
Werner, Kitaichi and Lin teach all the limitations of claim 29 above, but do not expressly teach
wherein the sixth conductive feature comprises a top portion and bottom portions extending downward from the top portion, and bottoms of the bottom portions are located at different levels in the second dielectric layer.
In an analogous art, Lo teaches:
(see fig. 14) wherein the sixth conductive feature comprises a top portion (720) and bottom portions (501, 502) extending downward from the top portion, and bottoms of the bottom portions (501, 502) are located at different levels in the second dielectric layer (120/220). See Lo at para. [0019] – [0026].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Werner with the teachings of Lo because a damascene having via holes of different heights enables connection to more than one conductive pad in the device. See Lo disclosing “The damascene structure includes a first via hole and a second via hole that respectively land on the first conductive pad and the second conductive pad at the same time, in which a first critical dimension of the first via hole is different from a second critical dimension of the second via hole” at Abstract.
Claim(s) 16 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Werner et al., US Publication No. 2008/0131796 A1 (of record) in view of Daubenspeck et al., US Publication No. 2014/0319522 A1 (of record).
Regarding claim 16:
Referring to MPEP § 2141, Examination Guidelines for Determining Obviousness Under 35 U.S.C. 103:
“A person of ordinary skill in the art is also a person of ordinary creativity, not an automaton.” KSR, 550 U.S., 82 USPQ2d at 1397. “[I]n many cases a person of ordinary skill will be able to fit the teachings of multiple patents together like pieces of a puzzle.” Office personnel may also take into account “the inferences and creative steps that a person of ordinary skill in the art would employ.”, 82 USPQ2d at 1396.
Werner does not expressly teach all the features of claim 16 in a single figure.
However, one of ordinary skill in the art, who is a person of ordinary creativity, modifying the test features (251) in fig. 2 to be the different pattern densities shown in the semiconductor device 100 in fig. 1 would arrive at the claim limitations.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to make this modification in order to advantageously detect if a chemical mechanical polishing (CMP) process is within specifications (e.g. see fig. 3, step 333). See Werner at para. [0034], [0041].
Thus, Werner teaches:
16. A method, comprising (see figs. 1-3):
forming one or more dielectric layers (201/203/204+ dielectric layer of 251; e.g. see “dielectric layers” and “lower lying material layer” of 251 at para. [0035]) including a test structure (251 in fig. 2; 110A, 110B in fig. 1) and a plurality of conductive features (e.g. “metal material” in layer 203, para. [0039]; shown as vias in fig. 2e) over a first substrate (101 in fig. 1; 201 in fig. 2)…
forming a dielectric layer (103 in fig. 1) on the one or more dielectric layers…;
forming a first photoresist layer (105 in fig. 1) over the dielectric layer;
patterning the first photoresist layer by focusing a light (106 in fig. 1 is photolithography) on a first image plane (e.g. “focus plane” at para. [0031], [0035]);
transferring a pattern of the first photoresist layer to the dielectric layer (e.g. pattern transfer forms openings 107, 108 in fig. 1);
forming conductive features (e.g. “interconnect structures”, para. [0011]) in the dielectric layer;
performing a process to identify defects (e.g. See fig. 3, steps 332-333); and
patterning a photoresist layer disposed over a second substrate by focusing the light on a second image plane different from the first image plane using information provided by the test structure (e.g. See fig. 3, feedback loop of steps 335 to steps 330-331. See para. [0041] disclosing, “In this case, the corresponding measurement results obtained in step 332 may be used, with or without a preceding evaluation, as respective feedback data for the focus controller 336, which may then supply updated focus parameter values to be used for further substrates to be processed in the module 330.” Also see “focus plane” at para. [0031], [0035]). See Werner at para. [0001] – [0044], figs. 1-3.
Further regarding claim 16:
Werner is silent:
wherein the test structure is disposed in a scribe line located between dies;
wherein the dielectric layer is formed in the scribe line and over the dies.
In an analogous art, Daubenspeck teaches:
wherein the test structure (221, 217) is disposed in a scribe line (220) located between dies (210);
wherein the dielectric layer (202) is formed in the scribe line (220) and over the dies (210). See Daubenspeck at para. [0047] – [0055].
Regarding claims 18:
Werner further teaches:
“wherein the defects comprise first defects located over the test structure and second defects…(e.g. The first and second defects are the “different heights” from CMP at para. [0031] – [0034])”.
Werner is silent that the second defects are ”located in regions without the test structure”.
However, it would have been obvious to one of ordinary skill in the art to form the second defects “located in regions without the test structure” because Werner teaches there may be “substantially metal-free regions” or “0%”. See Werner at para. [0039].
Regarding claim 19:
Werner further teaches:
“wherein the second defects are greater than a threshold number” (e.g. See fig. 3 the advanced process control (APC, 336) adjusts focus parameter values based on a “threshold value” comparison at step 333. See Werner at para. [0041].)
Werner further teaches:
20. The method of claim 18, the information provided by the test structure comprises thickness differences among portions of the test structure (e.g. “different heights” at para. [0031] – [0034]).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Werner with the teachings of Daubenspeck because forming the test structures in the scribe line region (i) enables the test structures to be formed concurrently with the active structures in the die region (e.g. Daubenspeck at para. [0049] – [0050]); and (ii) enables the test structures to be removed or “destroyed during semiconductor wafer structure dicing to form the integrated circuit chips” after testing is complete (e.g. Daubenspeck at para. [0021], [0050])
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Werner in view of Daubenspeck, as applied to claim 16 above, and further in view of Abdo et al., US Publication No. 2019/0227427 A1 (of record).
Regarding claim 17:
Werner and Daubenspeck teach all the limitations of claim 16 above, but are silent the light is EUV light.
In an analogous art, Abdo teaches “In contrast to conventional lithography techniques, EUV lithography utilizes extreme ultraviolet (EUV) light to transfer a circuit reflective portions of an EUV photomask (referred to herein as an “EUV mask”) to a semiconductor die”, para. [0003].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Werner with the teachings of Lin because “Extreme ultraviolet (EUV) lithography enables the fabrication of semiconductor devices having critical dimensions less than 28 nanometers (nm) in width”. See Abdo at para. [0003].
Claim(s) 21-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Werner et al., US Publication No. 2008/0131796 A1 (of record) in view of Daubenspeck et al., US Publication No. 2014/0319522 A1 (of record) and Lin, US Patent No. 6,149,830 (of record).
Regarding claim 21:
Referring to MPEP § 2141, Examination Guidelines for Determining Obviousness Under 35 U.S.C. 103:
“A person of ordinary skill in the art is also a person of ordinary creativity, not an automaton.” KSR, 550 U.S., 82 USPQ2d at 1397. “[I]n many cases a person of ordinary skill will be able to fit the teachings of multiple patents together like pieces of a puzzle.” Office personnel may also take into account “the inferences and creative steps that a person of ordinary skill in the art would employ.”, 82 USPQ2d at 1396.
Werner does not expressly teach all the features of claim 21 in a single figure.
However, one of ordinary skill in the art, who is a person of ordinary creativity, modifying the vias in layer 203 of fig. 2e to be the different pattern densities shown in the semiconductor device 100 in fig. 1 would arrive at the claim limitations.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to make this modification in order to advantageously detect if a chemical mechanical polishing (CMP) process is within specifications (e.g. see fig. 3, step 333). See Werner at para. [0034], [0041].
Thus, Werner teaches:
21. A method, comprising (see figs. 1-3; also see fig. 2e annotated below for claim 21):
depositing a first dielectric layer (203 in fig. 2; analogous to 102 in fig. 1) over a substrate (201 in fig. 1; analogous to 101 in fig. 1);
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forming a first conductive feature (e.g. 1st conductive feature labeled) in the first dielectric layer in a first portion (e.g. region 210C) of a test structure, wherein the first conductive feature has a first dimension…;
forming a second conductive feature (e.g. 2nd conductive feature labeled) in the first dielectric layer in a second portion (e.g. region 210D) of the test structure, wherein the second conductive feature has a second dimension greater than the first dimension; and
performing a first chemical mechanical polishing process (e.g. CMP at para. [0009] – [0010], para. [0033] – [0034]) on the test structure,
wherein the thickness of the first portion (e.g. region 210C) of the test structure is less than a thickness of a third portion (e.g. region 210A) of the test structure (e.g. The thickness of first portion 210C is less than a thickness of third portion 210A because Werner teaches in fig. 1B that higher density areas experience greater removal in a CMP process at para. [0009] – [0010]), and
the third portion (e.g. region 210A) of the test structure is free of conductive features.
Regarding claim 21:
Werner is silent:
wherein the test structure is disposed in a scribe line located between dies;
In an analogous art, Daubenspeck teaches:
wherein the test structure (221, 217) is disposed in a scribe line (220) located between dies (210). See Daubenspeck at para. [0047] – [0055].
Further regarding claim 21:
Werner is silent:
wherein a thickness of the first portion of the test structure is greater than a thickness of the second portion of the test structure.
In an analogous art, Lin teaches (see figs. 3-4) larger metal features experience greater dishing under a chemical mechanical polishing process (CMP). See Lin at col 4, ln 45–55.
In Werner’s fig. 2e, the second portion (210D) of the test structure is a larger metal feature so it will experience greater dishing compared to the smaller metal feature in the first portion (210C) of the test structure.
It would have been obvious to ordinary skill in the art to form in Werner’s fig. 23 “a thickness of the first portion (210C) of the test structure is greater than a thickness of the second portion (210D) of the test structure” because Lin teaches it experiences less dishing under CMP.
Werner further teaches:
22. The method of claim 21, further comprising forming a third conductive feature (e.g. In fig. 2e, there are a plurality of 1st conductive features) in the first portion of the test structure, wherein the first and third conductive features have a pitch smaller (e.g. pitch between 1st conductive features in region 210C) than the second dimension of the second conductive feature (e.g. 2nd conductive feature in region 210D), fig. 2e.
23. The method of claim 22, wherein the second dimension of the second conductive feature (e.g. 2nd conductive feature in region 210D) is about 3 times to about 5 times the pitch of the first and third conductive features smaller (e.g. pitch between 1st conductive features in region 210C), fig. 2e.
Regarding claim 24-27:
The limitations of forming additional conductive features and performing a second chemical mechanical polishing process (CMP) is obvious because Werner teaches forming additional, upper level metal features (107, 108) over lower level features (103, 104) in fig. 1b-1c. Also see additional, upper level metal features (251) over lower level features (e.g. conductive features in layer 203) in fig. 2e.
Thus, Werner teaches:
24. The method of claim 21, further comprising depositing a second dielectric layer (103 in fig. 1; 204 in fig. 2e) on the first dielectric layer....
Werner is silent:
wherein the second dielectric layer is formed in the scribe line and over the dies.
In an analogous art, Daubenspeck teaches:
wherein the second dielectric layer (202) is formed in the scribe line (220) and over the dies (210). See Daubenspeck at para. [0047] – [0055].
Werner further teaches:
25. The method of claim 24, further comprising forming a fourth conductive feature (107 in fig. 1; 251 in fig. 2) in the first portion of the test structure, wherein the fourth conductive feature has a third dimension.
26. The method of claim 25, further comprising forming a fifth conductive feature (108 in fig. 1; 251 in fig. 2) in the second portion of the test structure, wherein the fifth conductive feature has a fourth dimension greater than the third dimension (e.g. Werner teaches the regions 210A-210D in fig. 2 can have conductive features of different dimensions in the disclosure at para. [0034] “For example, the dimension and/or the density of respective features, such as lines and the like, may be selected differently in the first and second areas 210A, 210B…)
27. The method of claim 26, further comprising performing a second chemical mechanical polishing process on the test structure (e.g. A second CMP results in height difference between 107, 108 in fig. 1c. Also see para. [0009] – [0010] and para. [0034] disclosing “For example, the dimension and/or the density of respective features…may thus result in a different degree of height level due to a certain degree of pattern dependence…of a CMP process, as previously explained with reference to the semiconductor device 100.”)
28. The method of claim 21, wherein the first conductive feature comprises a barrier layer and a conductive material formed on the barrier layer, para. [0006], [0008] – [0009].
Regarding claim 29:
Referring to MPEP § 2141, Examination Guidelines for Determining Obviousness Under 35 U.S.C. 103:
“A person of ordinary skill in the art is also a person of ordinary creativity, not an automaton.” KSR, 550 U.S., 82 USPQ2d at 1397. “[I]n many cases a person of ordinary skill will be able to fit the teachings of multiple patents together like pieces of a puzzle.” Office personnel may also take into account “the inferences and creative steps that a person of ordinary skill in the art would employ.”, 82 USPQ2d at 1396.
Werner teaches:
29. A method, comprising (see figs. 1-3; also see fig. 2e annotated below for claim 21):
depositing a first dielectric layer over a substrate;
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forming a plurality of first conductive features (e.g. 1st conductive feature labeled) in the first dielectric layer (203) in a first portion (210B) of a test structure;
forming a plurality of second conductive features (e.g. 2nd conductive feature labeled) in the first dielectric layer (203) in a second portion (210C) of the test structure;
forming a third conductive feature (e.g. 3rd conductive feature labeled) in the first dielectric layer (203) in a third portion (210D) of the test structure, wherein the test structure comprises a fourth portion (210A) that is free of conductive features in the first dielectric layer (203);
depositing a second dielectric layer (e.g. dielectric layer of 251; e.g. see “dielectric layers” and “lower lying material layer” of 251 at para. [0035]) over the first dielectric layer;
forming a plurality of fourth conductive features (251, e.g. 4th conductive feature labeled) in the second dielectric layer (e.g. dielectric of 251) in the first portion (210B) of the test structure;
forming a plurality of fifth conductive features (251, e.g. 5th conductive feature labeled) in the second dielectric layer (e.g. dielectric of 251) in the second portion (210C) of the test structure;
forming a sixth conductive feature (251, e.g. 6thconductive feature labeled) in the second dielectric layer in the third portion (210D) of the test structure; and
forming a plurality of seventh conductive features (251, e.g. 7thconductive feature labeled) in the second dielectric layer in the fourth portion (210A) of the test structure,
wherein a thickness of the fourth portion of the test structure is greater than a thickness of the first portion of the test structure, which is greater than a thickness of the second portion of the test structure (e.g. The thickness of fourth portion 210A is greater than a thickness of the first portion 210B, which is greater than a thickness of the second portion 210C because (i) Werner teaches in fig. 1B that higher density areas experience greater removal in a CMP process at para. [0009] – [0010]; and (ii) and Werner teaches in fig. 1c the height differences in the lower layer 102 transfer to the upper layer 103 during subsequent lithographic processing at para. [0010], “Thus, during a lithography process 106, the difference in planarity in the regions 110A, 110B, as indicated by 111, may cause respective non-uniformities of the imaging process and subsequently respective non-uniformities during the patterning of the dielectric layer 103.” Also see para. [0031], “For example, the areas 210A, 210B may represent areas of different height levels with respect to at least one underlying portion or sub-layer of the material layer 203, which may intentionally be generated in order to represent a corresponding range of different height levels in corresponding product areas of an actual microstructure device.”).
Regarding claim 29:
Werner is silent:
wherein the test structure is disposed in a scribe line located between dies;
wherein the second dielectric layer is formed in the scribe line and over the dies.
In an analogous art, Daubenspeck teaches:
wherein the test structure (221, 217) is disposed in a scribe line (220) located between dies (210);
wherein the second dielectric layer (202) is formed in the scribe line (220) and over the dies (210). See Daubenspeck at para. [0047] – [0055].
Further regarding claim 29:
Werner is silent:
which is greater than a thickness of the third portion of the test structure
In an analogous art, Lin teaches (see figs. 3-4) larger metal features experience greater dishing under a chemical mechanical polishing process (CMP). See Lin at col 4, ln 45–55.
In Werner’s fig. 2e, the third portion (210D) of the test structure is the largest metal feature so it will experience the greatest dishing compared to the smaller metal feature in the first portion (210B) and second portion (210C) of the test structure.
It would have been obvious to one of ordinary skill in the art to form in Werner’s fig. 23 “a thickness of the fourth portion (210A) of the test structure is greater than a thickness of the first portion (210B) of the test structure, which is greater than a thickness of the second portion (210C) of the test structure, which is greater than a thickness of the third portion (210D) of the test structure” because Lin teaches it experiences less dishing under CMP.
Werner further taches:
30. The method of claim 29, further comprising depositing a third dielectric layer (204) on the first dielectric layer (203), wherein the second dielectric layer (e.g. dielectric of 251) is deposited on the third dielectric layer (204), fig. 2e.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Werner with the teachings of Daubenspeck because forming the test structures in the scribe line region (i) enables the test structures to be formed concurrently with the active structures in the die region (e.g. Daubenspeck at para. [0049] – [0050]); and (ii) enables the test structures to be removed or “destroyed during semiconductor wafer structure dicing to form the integrated circuit chips” after testing is complete (e.g. Daubenspeck at para. [0021], [0050])
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Werner with the teachings of Lin because “…when the metal is a large surface that is part of a patterned metal design embedded in a dielectric on which other layers and a substrate are attached, the use of a CMP process to polish the patterned metal creates a severe amount of dishing in the larger metal features.” See Lin at col 1, ln 33–37.
Claim(s) 31-34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Werner in view of Daubenspeck Lin as applied to claim 29 above, and further in view of Satya et al., US Publication No. 2002/0187582 A1 (of record).
Regarding claim 31:
Werner, Daubenspeck and Lin teach all the limitations of claim 29 above, but are silent regarding conductive features in the third dielectric.
However, forming conductive features in the third dielectric (204) is considered duplication of essential working parts, -i.e. duplicating the formation of conductive features Werner has already formed in layer (203).
Thus, it would have been obvious to one having ordinary skill in the art to form ”an eighth conductive feature in the third dielectric layer in the second portion of the test structure, wherein the plurality of fifth conductive features are disposed over the eight conductive feature”, since duplication of essential working parts of a device involve only routine skill in the art. See MPEP 2144.04, Legal Precedent as Source of Supporting Rationale, VI. Reversal, Duplication, or Rearrangement of Parts.
Furthermore, in an analogous art, Satya teaches (see fig. 10, also see fig. 13) a test structure can comprising comprise conductive features (M!-M4) formed in dielectric layers (444). Satya teaches four dielectric layers and each of the dielectric layers has a conductive feature. See Satya at para. [0089], para. [0131] – [0132].
The conductive feature (M3) is sandwiched between (M2) and (M4). Thus, Satya teaches (see fig. 10) ”an eighth conductive feature (M3) in the third dielectric layer (e.g. dielectric layer 444 at level M3) in the second portion of the test structure, wherein the plurality of fifth conductive features (M4) are disposed over the eighth conductive feature (M3)”, as recited in the claim.
Satya further teaches:
32. The method of claim 31, (see fig. 10 annotated below) wherein the plurality of fifth conductive features (M4) comprises an edge conductive feature (e.g. edge dual damascene) disposed over an edge portion of the eight conductive feature (M3) and a center conductive feature (e.g. center via of dual damascene) disposed over a center portion of the eighth conductive feature (M3)
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Satya further teaches:
33. The method of claim 32, wherein a thickness of the edge conductive feature (e.g. edge dual damascene) is less than a thickness of the center conductive feature (e.g. center via of dual damascene), fig. 10
Regarding claim 34:
It would have been obvious to one having ordinary skill in the art to form ” a nineth conductive feature in the third dielectric layer in the third portion of the test structure, wherein the sixth conductive feature is disposed over the nineth conductive feature”, since duplication of essential working parts of a device involve only routine skill in the art. See MPEP 2144.04, Legal Precedent as Source of Supporting Rationale, VI. Reversal, Duplication, or Rearrangement of Parts.
Furthermore, in an analogous art, Satya teaches (see fig. 10, also see fig. 13) a test structure can comprising comprise conductive features (M!-M4) formed in dielectric layers (444). Satya teaches four dielectric layers and each of the dielectric layers has a conductive feature. See Satya at para. [0089], para. [0131] – [0132].
The conductive feature (M3) is sandwiched between (M2) and (M4). Thus, Satya teaches (see fig. 10) “a nineth conductive feature (M3) in the third dielectric layer (e.g. dielectric layer 444 at level M3) in the third portion of the test structure, wherein the sixth conductive feature (M4) is disposed over the nineth conductive feature (M3)”.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Werner with the teachings of Satya because “The defect test structures are fabricated such that they are sensitive to defects that occur in IC product, but are designed so that the presence of defects is more readily ascertained.” (e.g. Satya para. [0007], also see para. [0006]); “One example of a defect test structure is found in the Copper CMP Test Mask Set designed at MIT. This test mask set is designed to quantify the dependence of the resulting copper line profile on parameters such as line pitch, line width and line aspect ratio” (e.g. Satya at para. [0008]); and “During the electron beam inspection of the scanned swath, a proximal end of the M3 interconnect may be scanned. Similarly, as shown in FIG. 10…shorts between the M1 and M2 interconnects, can still be inspected through scan element 454” (Satya at para. [0131])
Claim(s) 35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Werner in view of Daubenspeck and Lin as applied to claim 29 above, and further in view of Lo, US Publication No. 2022/0165618 A1 (of record).
Regarding claim 35:
Werner and Lin teach all the limitations of claim 29 above, but do not expressly teach
wherein the sixth conductive feature comprises a top portion and bottom portions extending downward from the top portion, and bottoms of the bottom portions are located at different levels in the second dielectric layer.
In an analogous art, Lo teaches:
(see fig. 14) wherein the sixth conductive feature comprises a top portion (720) and bottom portions (501, 502) extending downward from the top portion, and bottoms of the bottom portions (501, 502) are located at different levels in the second dielectric layer (120/220). See Lo at para. [0019] – [0026].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Werner with the teachings of Lo because a damascene having via holes of different heights enables connection to more than one conductive pad in the device. See Lo disclosing “The damascene structure includes a first via hole and a second via hole that respectively land on the first conductive pad and the second conductive pad at the same time, in which a first critical dimension of the first via hole is different from a second critical dimension of the second via hole” at Abstract.
Conclusion
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/Michele Fan/
Primary Examiner, Art Unit 2818
12 March 2026