DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over JAIN (US 20230268389) in view of XIE ‘033 (US 20230086033).
Regarding claim 17, JAIN discloses a method, comprising:
forming a transistor (the transistor comprising semiconductor channels 212, source and drain 236, and gate 240, see fig 11, para 72, 82 and 83) over a substrate (substrate 206, see fig 11, para 71), wherein the transistor comprises a gate structure (gate 240, see fig 11, para 83), a channel structure (channel 212, see fig 14, para 72) embedded in the gate structure, and a source epitaxial structure (right epitaxial structure 236, see fig 11, para 82) and a drain epitaxial structure (left epitaxial structure 236, see fig 11, para 82) connected to the channel structure;
forming a source contact at a front-side surface of the source epitaxial structure (source contact 244 is formed on a top side surface of 236, see fig 12, para 89);
forming a front-side interconnection structure (fig 12, 246, para 89) over the source contact;
removing the substrate (206 is removed in fig 16, see para 92) to expose a back-side surface of the drain epitaxial structure (the back side of 236 is exposed in fig 19, see para 95);
forming a drain contact (fig 20, 258, para 96) at the back-side surface of the drain epitaxial structure;
wherein an entirety of the gate contact via is misaligned with the channel structure in a vertical direction (the gate contact via 244 on 240 is misaligned with channel 212 in the vertical direction, see fig 14B, para 89);
forming a back-side interconnection structure (fig 20, 262, para 96) over the drain contact.
JAIN fails to explicitly disclose a method wherein after forming the front-side interconnection structure, forming a gate contact via on a back surface of the gate structure,
and forming a back-side interconnection structure over the drain contact and the gate contact via.
XIE ‘033 teaches a method wherein after forming the front-side interconnection structure (the source interconnect 130 over source 122, see fig 9A, para 53), forming a gate contact via on a back surface of the gate structure (gate contact 1438 formed over gate 126, see fig 14, para 62); and
forming a back-side interconnection structure over the gate contact via (backside via 1442, see fig 15A, para 63).
JAIN and XIE ‘033 are analogous art because they both are directed towards methods of making gate-all-around transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of JAIN with the back side gate interconnect of XIE ‘033 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of JAIN with the back side gate interconnect of XIE ‘033 in order to avoid issues such as SDB etch-induced epitaxial layer damage (see XIE '033 para 32).
Regarding claim 18, JAIN and XIE ‘033 disclose the method of claim 17.
JAIN further discloses a method, further comprising: performing a silicidation process to form a silicide region on the front-side surface of the source epitaxial structure (the silicide layer formed on 236 as part of 244, see fig 12, para 89).
Regarding claim 19, JAIN and XIE ‘033 disclose the method of claim 17.
JAIN further discloses a method, further comprising: performing a silicidation process to form a silicide region on the back-side surface of the drain epitaxial structure (the silicide layer formed on the bottom of 236 as part of 258, see fig 20, para 96).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over JAIN (US 20230268389) in view of XIE ‘033 (US 20230086033) and further in view of LI (US 20210399098).
Regarding claim 20, JAIN and XIE ‘033 disclose the method of claim 17.
JAIN and XIE ‘033 fail to explicitly disclose a method, further comprising:
doping the source epitaxial structure prior to forming the source contact, such that a dopant concentration of the source epitaxial structure is higher than a dopant concentration of the drain epitaxial structure.
LI teaches a method, further comprising:
doping the source epitaxial structure prior to forming the source contact, such that a dopant concentration of the source epitaxial structure is higher than a dopant concentration of the drain epitaxial structure (the implant performed to form a higher doping 1602 in source/drain 906' that is not formed in the other source/drain 906, see fig 16, para 66-68).
JAIN, XIE ‘033 and LI are analogous art because they both are directed towards methods for making gate-all-around transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of JAIN and XIE ‘033 with the epitaxial source/drain structure doping of LI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of JAIN and XIE ‘033 with the epitaxial source/drain structure doping of LI in order to avoid an increased contact resistance (see LI para 70).
Claim(s) 21, 26 and 29-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over JAIN (US 20230268389) in view of KIM (US 20210375722).
Regarding claim 21, JAIN discloses a method, comprising:
forming a transistor (the transistor comprising semiconductor channels 212, source and drain 236, and gate 240, see fig 11, para 72, 82 and 83) comprising a gate structure (gate 240, see fig 11, para 83), a source epitaxial structure (right epitaxial structure 236, see fig 11, para 82), and a drain epitaxial structure (left epitaxial structure 236, see fig 11, para 82),
wherein each of the source and drain epitaxial structures has a front-side surface (the top surfaces of 236 in fig 10) and a back-side surface (the bottom surface of 236 in fig 10), the front-side surface is wider than the back-side surface (the top surface of 236 in fig 10A is wider than the bottom surface of 236), and
the gate structure extends in a first direction in a top view (222 extends in the horizontal direction in fig 10A);
forming a source contact over the front-side surface of the source epitaxial structure (source contact 244 is formed on a top side surface of 236, see fig 12, para 89);
forming a front-side interconnection structure (fig 12, 246, para 89),
wherein the front-side interconnection structure comprises a power rail (246 can be a power rail, see fig 63) electrically connected to the source contact;
forming a drain contact (fig 20, 258, para 96) over the back-side surface of the drain epitaxial structure and having a first width along the first direction (258 has a width along the horizontal direction in fig 20A); and
forming a back-side interconnection structure (fig 20, 262, para 96),
wherein the back-side interconnection structure comprises a first metal line (fig 20, 262, para 96) electrically connected to the drain contact and having a second width along the first direction (262 has a width in the horizontal direction in fig 20A0.
JAIN fails to explicitly disclose a method wherein the first width of the drain contact is greater than the second width of the first metal line.
KIM teaches a method wherein the first width of the drain contact is greater than the second width of the first metal line (the width of the drain contact 255 in the horizontal direction in fig 2 is larger than the width of V2 in the horizontal direction in fig 2, see para 33 and 55).
JAIN and KIM are analogous art because they both are directed towards methods of making gate-all-around transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of JAIN with the specific element widths of KIM because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of JAIN with the specific element widths of KIM in order to lower the contact resistance (see KIM para 120).
Regarding claim 26, JAIN and KIM disclose the method of claim 21.
JAIN fails to disclose a method, wherein forming the source contact is performed such that a vertical distance between a bottommost surface of the source contact and a topmost surface of the gate structure is in a range from about 5 nanometers to about 25 nanometers.
However, parameters such as the specific sizes and spacings of device elements in the art of methods of manufacturing semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characteristics during fabrication. It would have been obvious to one of ordinary skill in the art at the time the invention was made to adjust the spacing between the bottom surface of the source contact and the top surface of the gate structure in the method of JAIN in order to increase contact between the gate and the channel (see JAIN para 53).
Regarding claim 29, JAIN and KIM disclose the method of claim 21.
JAIN further discloses a method, further comprising: forming a source silicide region on the front-side surface of the source epitaxial structure (the silicide layer formed on 236 as part of 244, see fig 12, para 89); and
after forming the front-side interconnection structure (after the formation of 246, see fig 12), forming a drain silicide region on the back-side surface of the drain epitaxial structure (the silicide layer formed on the bottom of 236 as part of 258, see fig 20, para 96).
Regarding claim 30, JAIN and KIM disclose the method of claim 21.
JAIN further discloses a method, wherein forming the drain contact is performed such that the drain contact is wider than the back-side surface of the drain epitaxial structure (256 is wider than 236, see fig 20C).
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over JAIN (US 20230268389) in view of KIM (US 20210375722) and further in view of LIN (US 20220135644).
Regarding claim 22, JAIN and KIM disclose the method of claim 21.
JAIN and KIM fail to explicitly disclose a method, further comprising:
forming a front-side via over the source contact,
wherein a bottom surface of the front-side via is in contact with the source contact, and
forming the front-side interconnection structure is performed such that a top surface of the front-side via is in contact with the power rail.
LIN teaches a method, further comprising:
forming a front-side via (fig 2C, 260A, para 34) over the source contact,
wherein a bottom surface of the front-side via is in contact with the source contact (a bottom surface of 260A is in contact with 220B, see fig 2C), and
forming the front-side interconnection structure is performed such that a top surface of the front-side via is in contact with the power rail (via 260A is in direct contact with power rails 270B, see fig 2C, para 34).
JAIN, KIM and LIN are analogous art because they both are directed towards methods of making gate-all-around transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of JAIN and KIM with the contact geometry of LIN because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of JAIN and KIM with the contact geometry of LIN in order to improve yield (see LIN para 63).
Claim(s) 23 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over JAIN (US 20230268389) in view of KIM (US 20210375722) and further in view of WANG (US 20210305262).
Regarding claim 23, JAIN and KIM disclose the method of claim 21.
JAIN and KIM fails to explicitly disclose a method, wherein forming the drain contact is performed such that a first vertical distance between a topmost surface of the drain contact and a bottommost surface of the gate structure is less than a second vertical distance between a bottommost surface of the source contact and a topmost surface of the gate structure.
WANG teaches a method, wherein forming the drain contact is performed such that a first vertical distance between a topmost surface of the drain contact and a bottommost surface of the gate structure (the top surface of drain contact 716 is level with the bottom surface of gate 708, so the vertical distance between them is zero, see fig 8, para 50) is less than a second vertical distance between a bottommost surface of the source contact and a topmost surface of the gate structure (the bottom surface of the source contact 806 is not level with the top surface of gate 708, so the distance will be more than zero, see fig 8, para 50).
JAIN, KIM and WANG are analogous art because they both are directed towards methods of making gate-all-around transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of JAIN and KIM with the electrode geometry of WANG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of JAIN and KIM with the electrode geometry of WANG in order to improve performance without increasing size, see WANG para 60).
Regarding claim 25, JAIN and KIM disclose the method of claim 21.
JAIN and KIM fails to explicitly disclose a method, wherein forming the drain contact is performed such that a topmost surface of the drain contact is level with or higher than a bottom surface of the gate structure, and
a vertical distance between the topmost surface of the drain contact and the bottom surface of the gate structure is in a range from about 0 nanometer to about 3 nanometers.
WANG teaches a method, wherein forming the drain contact is performed such that a topmost surface of the drain contact is level with (the top surface of 716 is level with the bottom surface of gate structure 708, see fig 8, para 50) or higher than a bottom surface of the gate structure, and
a vertical distance between the topmost surface of the drain contact and the bottom surface of the gate structure is in a range from about 0 nanometer (since the top surface of 716 is level with the bottom of 708, the distance is 0 nm, see fig 8) to about 3 nanometers.
JAIN, KIM and WANG are analogous art because they both are directed towards methods of making gate-all-around transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of JAIN and KIM with the electrode geometry of WANG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of JAIN and KIM with the electrode geometry of WANG in order to improve performance without increasing size, see WANG para 60).
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over JAIN (US 20230268389) in view of KIM (US 20210375722) and further in view of KIM ‘331 (US 20200373331).
Regarding claim 24, JAIN and KIM disclose the method of claim 21.
JAIN and KIM fail to explicitly disclose a method, wherein forming the drain contact is performed such that a topmost surface of the drain contact is lower than a bottommost surface of the gate structure.
KIM ‘331 teaches a method, wherein forming the drain contact is performed such that a topmost surface of the drain contact is lower than a bottommost surface of the gate structure (at topmost surface of drain contact 154 is lower than a bottom surface of gate GL, see fig 1C, para 18).
JAIN, KIM and KIM ‘331 are analogous art because they both are directed towards methods of making gate-all-around transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of JAIN and KIM with the electrode geometry of KIM ‘331 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of JAIN and kIM with the electrode geometry of KIM ‘331 in order to improve the degree of freedom in arranging the conductors (see KIM para 38).
Claim(s) 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over JAIN (US 20230268389) in view of KIM (US 20210375722) and further in view of XIE ‘033 (US 20230086033).
Regarding claim 27, JAIN and KIM disclose the method of claim 21.
JAIN and KIM fail to explicitly disclose a method, further comprising:
after forming the front-side interconnection structure, forming a gate contact via on a back surface of the gate structure,
wherein forming the back-side interconnection structure is performed such that the gate structure is electrically connected to a second metal line of the back-side interconnection structure.
XIE ‘033 teaches a method, further comprising:
after forming the front-side interconnection structure (the source interconnect 130 over source 122, see fig 9A, para 53), forming a gate contact via on a back surface of the gate structure (gate contact 1438 formed over gate 126, see fig 14, para 62),
wherein forming the back-side interconnection structure is performed such that the gate structure is electrically connected to a second metal line of the back-side interconnection structure (the gate interconnect 1438 is electrically connected to the metal line 1446, see fig 15, para 63).
JAIN, KIM and XIE ‘033 are analogous art because they both are directed towards methods of making gate-all-around devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of JAIN and KIM with the electrode geometry of XIE ‘033 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of JAIN and KIM with the electrode geometry of XIE ‘033 in order to avoid issues such as SDB etch-induced epitaxial layer damage (see XIE '033 para 32).
Claim(s) 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over JAIN (US 20230268389) in view of KIM (US 20210375722) and further in view of LI (US 20210399098).
Regarding claim 28, JAIN and KIM disclose the method of claim 21.
JAIN and KIM fail to explicitly disclose a method, wherein forming the transistor is performed such that a dopant concentration of the source epitaxial structure is higher than a dopant concentration of the drain epitaxial structure.
LI teaches a method, wherein forming the transistor is performed such that a dopant concentration of the source epitaxial structure is higher than a dopant concentration of the drain epitaxial structure (the implant performed to form a higher doping 1602 in source/drain 906' that is not formed in the other source/drain 906, see fig 16, para 66-68).
JAIN, KIM and LI are analogous art because they both are directed towards methods for making gate-all-around transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of JAIN and KIM with the epitaxial source/drain structure doping of LI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of JAIN and KIM with the epitaxial source/drain structure doping of LI in order to avoid an increased contact resistance (see LI para 70).
Claim(s) 31-32 and 35-36 is/are rejected under 35 U.S.C. 103 as being unpatentable over JAIN (US 20230268389) in view of LI (US 20210399098) and further in view of LIN (US 20200135644).
Regarding claim 31, JAIN discloses a method, comprising:
forming a first transistor (the transistor comprising semiconductor channels 212, source and drain 236, and gate 240, see fig 11, para 72, 82 and 83) comprising a first semiconductor layer (semiconductor 212, see fig 10, para 72),
a first gate structure (gate 240, see fig 11, para 83) around the first semiconductor layer,
a first source epitaxial structure and a drain epitaxial structure (right and left epitaxial structure 236, see fig 11, para 82) at opposite sides of the first semiconductor layer (the two structures 236 are at the side of 212, see fig 10), and
an interlayer dielectric layer (fig 11, 238, para 83) covering the first source epitaxial structure and the drain epitaxial structure (238 covers top surfaces of 236, see fig 11),
wherein the first source epitaxial structure has a front-side surface (the top surfaces of 236 in fig 10) and a back-side surface (the bottom surface of 236 in fig 10), the front-side surface is wider than the back-side surface (the top surface of 236 in fig 10A is wider than the bottom surface of 236);
performing an etching process to form an opening in the interlayer dielectric layer to expose a top surface of the first source epitaxial structure (the openings in 238 which 244 is formed, see fig 12, para 89);
forming a front-side interconnection structure (fig 12, 246, para 89) comprising a first power rail (246 can be a power rail, see fig 63), wherein the first front-side via has a top surface in contact with the first power rail (the via 244 has a top surface in direct contact with 246, see fig 12).
JAIN and LI fails to explicitly disclose a method comprising performing an etching process to form an opening in the interlayer dielectric layer to expose a top surface of the first source epitaxial structure;
after forming the opening in the interlayer dielectric layer, performing an implantation process to the first source epitaxial structure such that a dopant concentration of the first source epitaxial structure is higher than a dopant concentration of the drain epitaxial structure;
forming a first source contact over the front-side surface of the first source epitaxial structure;
forming a first front-side via having a bottom surface in contact with the first source contact.
LIN teaches a method comprising performing an etching process to form an opening in the interlayer dielectric layer to expose a top surface of the first source epitaxial structure (the contact trench 1304 etched in ILD 908 to expose source/drain 906', see fig 13, para 65);
after forming the opening in the interlayer dielectric layer, performing an implantation process to the first source epitaxial structure such that a dopant concentration of the first source epitaxial structure is higher than a dopant concentration of the drain epitaxial structure (the implant performed to form a higher doping 1602 in source/drain 906' that is not formed in the other source/drain 906, see fig 16, para 66-68).
JAIN, LIN and LI are analogous art because they both are directed towards methods for making gate-all-around transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of JAIN and LIN with the epitaxial source/drain structure doping of LI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of JAIN with the epitaxial source/drain structure doping of LI in order to avoid an increased contact resistance (see LI para 70).
JAIN and LI fails to explicitly disclose a method comprising forming a first source contact over the front-side surface of the first source epitaxial structure;
forming a first front-side via having a bottom surface in contact with the first source contact.
LIN teaches a method comprising forming a first source contact over the front-side surface of the first source epitaxial structure (contact 220B is formed over 232B, see fig 2C, para 52);
forming a first front-side via having a bottom surface in contact with the first source contact (via 260 is formed over 220B, see fig 2C, para 34).
JAIN and LIN are analogous art because they both are directed towards methods of making gate-all-around transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of JAIN and LI with the contact geometry of LIN because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of JAIN and LI with the contact geometry of LIN in order to improve yield (see LIN para 63).
Regarding claim 32, JAIN, LI and LIN disclose the method of claim 31.
JAIN further discloses a method, wherein forming the front-side interconnection structure is performed such that the front-side interconnection structure comprises no metallization layer between the first power rail and the first source contact (there is no metallization layer between 246 and 244 since they are in direct contact, see fig 20).
Regarding claim 35, JAIN, LI and LIN disclose the method of claim 31.
JAIN further discloses a method, further comprising: forming a source silicide region on the front-side surface of the first source epitaxial structure (the top side of 236 can have a silicide liner formed on it as the first layer of 244, see fig 12, para 89),
and a front-side surface of the drain epitaxial structure is free of a silicide region (the front side surface of the drain 236 does not have 244 formed on it, and so does not have a silicide layer, see fig 12).
Regarding claim 36, JAIN, LI and LIN disclose the method of claim 31.
JAIN further discloses a method, wherein forming the first transistor is performed such that the first transistor further comprises a gate spacer (SiO spacer 226, see fig 6, para 77) between the first source contact and the first gate structure and an inner spacer (inner spacer 230 can be SIOCN, see fig 7C, para 80) between the first semiconductor layer and the first gate structure, and a k value of the inner spacer is greater than a k value of the gate spacer.
Claim(s) 33-34 is/are rejected under 35 U.S.C. 103 as being unpatentable over JAIN (US 20230268389) in view of LI (US 20210399098) and LIN (US 20200135644) and further in view of XIE (US 20230369219).
Regarding claim 33, JAIN and LI disclose the method of claim 31.
JAIN further discloses a method further comprising:
forming a second transistor (an adjacent transistor in the device of fig 1 and 20 to the first transistor comprising semiconductor channels 212, source and drain 236, and gate 240, see fig 11, para 72, 82 and 83) comprising a second semiconductor layer (semiconductor 212, see fig 10, para 72), a second gate structure around the second semiconductor layer (gate 240, see fig 11, para 83), and a second source epitaxial structure (right epitaxial structure 236, see fig 11, para 82) at a side of the second semiconductor layer.
JAIN, LI fail to explicitly disclose a method comprising forming a second source contact over a front-side surface of the second source epitaxial structure; and
forming a second front-side via over and in contact with the second source contact,
wherein forming the front-side interconnection structure is performed such that the front-side interconnection structure further comprises a second power rail at a voltage level different from that of the first power rail, and the second power rail is in contact with the second front-side via.
LIN teaches a method comprising forming a second source contact over a front-side surface of the second source epitaxial structure (contact 220B is formed over 232B, see fig 2C, para 52); and
forming a second front-side via over and in contact with the second source contact (via 260 is formed over 220B, see fig 2C, para 34),
JAIN, LEE, and LIN are analogous art because they both are directed towards methods of making gate-all-around transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of JAIN, LI with the two-layer via structure of LIN because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of JAIN, LI with the two-layer via structure of LIN in order to improve yield (see LIN para 63).
JAIN, LI and LIN fails to explicitly disclose a method comprising wherein forming the front-side interconnection structure is performed such that the front-side interconnection structure further comprises a second power rail at a voltage level different from that of the first power rail, and the second power rail is in contact with the second front-side via.
XIE teaches a method comprising wherein forming the front-side interconnection structure is performed such that the front-side interconnection structure further comprises a second power rail at a voltage level different from that of the first power rail (the second power plane 210 and 262 can have a different voltage than the first power plane 208 for controlling a different transistor, see fig 11, para 37), and the second power rail is in contact with the second front-side via (fig 11, 236b, para 37).
JAIN, LI, LIN and XIE are analogous art because they both are directed towards methods of making gate-all-around transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of JAIN, LI and LIN with the second power rail of XIE because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of JAIN with the second power rail of XIE in order to apply different voltages to pFET and nFET transistors (see XIE para 37).
Regarding claim 34, JAIN and LI disclose the method the method of claim 33.
JAIN fails to explicitly disclose a method comprising, wherein the first and second power rails are at a same level in a vertical direction.
XIE teaches a method comprising, wherein the first and second power rails are at a same level in a vertical direction (a horizontal line can be drawn that passes through both 208 and 210/262, see fig 11).
JAIN and XIE are analogous art because they both are directed towards methods of making gate-all-around transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of JAIN with the second power rail of XIE because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of JAIN with the second power rail of XIE in order to apply different voltages to pFET and nFET transistors (see XIE para 37).
Response to Arguments
Applicant’s arguments with respect to claim(s) 21 and 31 have been considered but are moot because the new ground of rejection does not rely on the combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed 12/8/2025 regarding claim 17 have been fully considered but they are not persuasive. The applicant argues that neither JAIN nor XIE ‘033 discloses a device “wherein an entirety of the gate contact via is misaligned with the channel structure in a vertical direction”. This argument is unpersuasive because JAIN discloses, in figure 14B, a device with a gate contact via 244 which contacts gate 240 is not aligned with the semiconductor channels 212 along a vertical direction.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/LYNNE A GURLEY/Supervisory Patent Examiner, Art Unit 2811