DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Claims 1-10, 12-19, 22, and 23 remain pending in this application. Acknowledgement is made of the amendment received 12/04/2025. Claims 11 and 21 are canceled, claims 1, 9, and 16 are amended, and claims 22 and 23 are added for consideration.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-6, 22, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al (US 20230207553 A1, hereafter Xie) in view of Liaw (US 20200105761 A1) and Endo et al (US 20100202208 A1, hereafter Endo).
Regarding claim 1, Xie teaches: A semiconductor device (Xie 100, fig 1A, 1B), comprising:
a logic cell (Xie C1, ¶0051) in a device region (Xie fig 1A, region between 170 and 190, best shown as 140), comprising:
a first P-type gate-all-around (GAA) nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116, “PFET”, ¶0039, 0044, 0045, a singular PFET formed by 124, G2 within 120-3, fig 1B, “plurality of PFET devices” ¶0044);
a second P-type GAA nanosheet transistor (Xie G1, 120-3, 124, 112, 114, 116, “PFET”, ¶0039, 0044, 0045); and
an N-type GAA nanosheet transistor (Xie G2, 120-2, 122, 112, 114, 116, “NFET”, ¶0039, 0044, a singular NFET formed by 122, G1 within 120-2, fig 1B, “plurality of NFET devices” ¶0044, 0045);
wherein each of the first P-type GAA nanosheet transistor, the second P-type GAA nanosheet transistor and the N-type GAA nanosheet transistor has two channel members (Xie 112, 114, 116, ¶0046, at least two) vertically stacked in the device region (Xie fig 1A);
a back-side interconnect structure (Xie 105, 181-184, 190, ¶0049) on a back-side of the device region (Xie fig 1A, ¶0049, 105, 190 are formed below 140), comprising:
a first back-side contact (Xie 184, ¶0049), a second back-side contact (Xie 183, ¶0049);
a VDD line (Xie 196, ¶0050, “VDD”) formed in a back-side metal layer (layer best shown as Xie 192 in fig 1A, in at least one embodiment 194 containing metal, ¶0099), coupled to a source feature (Xie 124 right of G2 with respect to fig 1B, ¶0044, 0050) of the first P-type GAA nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116) through the first back-side contact (Xie 184)(Xie fig 1B, ¶0050, similar to 182 fig 1A), wherein the first P-type GAA nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116) and the second P-type GAA nanosheet transistor (Xie G1, 120-3, 124, 112, 114, 116) share a common drain feature (Xie 124 between G1 and G2 in C1 with respect to fig 1B, ¶0044, 0050), wherein a longest dimension of the VDD line extends in a first direction (Xie Y dir, fig 1B)(Xie fig 1B); and
a VSS line (Xie 194, 198, ¶0050, “VSS”) formed in the back-side metal layer (layer best shown as Xie 192 in fig 1A) and coupled to a source feature (Xie 122 right of G2 with respect to fig 1B, ¶0044) of the N-type GAA nanosheet transistor (Xie G2, 120-2, 122, 112, 114, 116) through the second back-side contact (Xie 183)(Xie fig 1B, ¶0050, the examiner interprets “the backside source/drain contacts 181 and 184 (which are connected to the backside power rail 194)” to be a typo based on fig 1B and the context of the paragraph, and that it should read “backside source/drain contacts 181 and 183”, similar to 181 fig 1A); and
a front-side interconnect structure (Xie 160-163, 170, ¶0047) on a front-side of the device region (Xie fig 1A, ¶0047, 170 is formed above 140), comprising:
a first front-side contact (Xie 161, ¶0048) and a second front-side contact (Xie 160, ¶0048); and
at least one metal line (Xie T6 or T3, ¶0048) coupled to the common drain feature (Xie 124 between G1 and G2 in C1 with respect to fig 1B) of the first P-type GAA nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116) and the second P-type GAA nanosheet transistor (Xie G1, 120-3, 124, 112, 114, 116) through the first front-side contact (Xie 161)(Xie fig 1A, T6 is coupled to 161 at least via 175, ¶0048, 0054) or coupled to a drain feature (Xie 122 between G1 and G2 in C1 with respect to fig 1B) of the N-type GAA nanosheet transistor (Xie G2, 120-2, 122, 112, 114, 116) through the second front-side contact (Xie 160)(Xie fig 1A, T3 is coupled to 160 at least via 174, ¶0048, 0054);
an inter-layer dielectric (Xie 140, 142, 171) over the source feature (Xie 124 right of G2 with respect to fig 1B) of the first P-type GAA nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116)(Xie fig 1A) and contiguous with the first back-side contact (Xie 184)(Xie fig 1A, Xie 140 and 184 share a common boundary at the interface of 105/140, and therefore meets a broadest reasonable interpretation of “contiguous with”).
Xie does not explicitly teach: a third back-side contact;
a VDD line coupled to a source feature of the second P-type GAA nanosheet transistor through the third back-side contact.
Liaw, in the same field of endeavor of semiconductor device manufacturing, teaches: A semiconductor device (Liaw 500, 510SP, fig 5A), comprising:
a first P-type GAA nanosheet transistor (Liaw left 510SP with respect to fig 5A, fig 5D, ¶0039-0044, 535SP, 530S, 545S);
a second P-type GAA nanosheet transistor (Liaw right 510SP with respect to fig 5A, fig 5D); and an N-type GAA nanosheet transistor (Liaw 510SN);
a first contact (Liaw left most 550 within 510SP with respect to fig 5A, fig 5D), a second contact (Liaw center 550 within 510SP with respect to fig 5A, fig 5D), and a third contact (Liaw right most 550 within 510SP with respect to fig 5A, fig 5D).
Xie further teaches: a plurality of P-type GAA nanosheet transistors (Xie 120-3, 124, 112, 114, 116, “PFET”) within a channel (Xie C1), the channel comprising a standard logic cell (Xie ¶0051), wherein;
a VDD line (Xie 196, ¶0050, “VDD”) coupled to a source feature (Xie 124 ¶0044, 0050) of a P-type GAA nanosheet transistor through a back-side contact (Xie 184, ¶0049)(Xie fig 1A, 1B); and
adjusting the configuration of source drain contacts and adjusting a layout of contacts of standard logic cell to form logic gates (Xie ¶0051).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to duplicate the first back-side contact of Xie (Xie 184) such that it is coupled to the source feature of the second P-type GAA nanosheet transistor (Xie G1, 120-3, 124, 112, 114, 116), in order to provide functionality to the second P-type GAA nanosheet transistor, and/or in order to form a half a NAND gate of a CMOS device (Liaw ¶0037, Xie ¶0005, 0051).
Further, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to duplicate first back-side contact of Xie, in order to form a transistor, since mere duplication of the essential working parts of a device involves only routine skill in the art (see MPEP 2144.04 VI).
Xie in view of Liaw does not teach: a first back-side via disposed between the VDD line and the first back-side contact and coupling the VDD line to the first back-side contact, wherein a longest dimension of the first back-side via extends in a second direction different than the first direction.
Xie further teaches: using a via (Xie 174) to couple a contact (Xie 160) and a metal line (Xie T3) within an interconnect structure (Xie 170)(Xie fig 1A).
Endo, in the same field of endeavor of semiconductor device manufacturing, and in at least one embodiment, teaches: a first via (CP10, BRI of “via”, ¶0083), wherein a longest dimension of the via (Endo dp_rect) extends in a second direction (Endo Gate width direction, fig 4, 11B, similar to Xie X-dir)(Endo fig 11B) different than a first direction (Endo Gate length direction, fig 4, 11B, ¶0079, similar to Xie Y-dir)(Endo fig 11B).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the first via of Endo, between the VDD line and first back-side contact of Xie in view of Liaw, such that “a first back-side via disposed between the VDD line and the first back-side contact and coupling the VDD line to the first back-side contact, wherein a longest dimension of the first back-side via extends in a second direction different than the first direction”, in order to increase an alignment margin in the second direction (Endo ¶0099), thereby ensuring sufficient contact and/or suppressing an increase in contact resistance (Endo ¶0156) between the VDD line and the first back-side contact of Xie in view of Liaw due to misalignment.
Regarding claim 2, Xie in view of Liaw and Endo teaches: The semiconductor device as claimed in claim 1, wherein the VSS line (Xie 194, ¶0050, “VSS”) is coupled to the second back-side contact (Xie 183, ¶0049); and
wherein the first back-side via (Endo CP10) has a rectangular shape or an elliptical shape (Endo fig 4, 11B).
Xie in view of Liaw and Endo does not explicitly teach: wherein the back-side interconnect structure further comprises: a second back-side via formed between the back-side metal layer and the back-side of the device region, wherein the VSS line is coupled to the second back-side contact through the second back-side via;
wherein the second back-side via have a rectangular shape or an elliptical shape.
Endo further teaches: a plurality of vias (Endo CP-10, BRI of “via”, ¶0083).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to duplicate the first via of Xie in view of Liaw and Endo, such that “the back-side interconnect structure further comprises: a second back-side via formed between the back-side metal layer and the back-side of the device region, wherein the VSS line is coupled to the second back-side contact through the second back-side via; wherein the second back-side via have a rectangular shape or an elliptical shape”, in order to increase an alignment margin in the second direction (Endo ¶0099), thereby ensuring sufficient contact and/or suppressing an increase in contact resistance (Endo ¶0156) between the VSS line and the second back-side contact of Xie in view of Liaw and Endo due to misalignment.
Further, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to duplicate the first via of Xie in view of Liaw and Endo, since mere duplication of the essential working parts of a device involves only routine skill in the art (see MPEP 2144.04 VI).
Regarding claim 3, Xie in view of Liaw and Endo teaches: The semiconductor device as claimed in claim 2, wherein the first back-side via and second back-side via (Xie 181-184, 190, as modified to include Endo CP10) have a dimension ratio of long side (Endo dp_rect, ¶0154, 0079, similar to c1, ¶0083) to short side (Endo dp_min, ¶0154, 0079, similar to a3, ¶0083) that is within a range of 1.2 to 5 (¶0080-0083, dp_rect=2*dp_min+Sp_min=(2*70nm)+(200nm)=340nm → ratio dp_rect:dp_min=340nm:70nm=4.85:1, similar to ratio c1:a3=290nm:60nm=4.83:1, fig 10).
Regarding claim 4, Xie in view of Liaw and Endo teaches: The semiconductor device as claimed in claim 1, wherein the VSS line (Xie 194, ¶0050, “VSS”) extends in the first direction (Xie Y dir, fig 1B), and a gate electrode (Xie 150, G1-G3) wrapping around the two channel members (Xie 112, 114, 116, ¶0046, at least two)(Xie fig 5B) of the first P-type GAA nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116) or the N-type GAA nanosheet transistor (Xie G2, 120-2, 122, 112, 114, 116)(Xie fig 5B) extends in the second direction (Xie X dir, ¶0045, fig 1B), wherein the first direction is perpendicular to the second direction (Xie fig 1B, 5B).
Regarding claim 5, Xie in view of Liaw and Endo teaches: The semiconductor device as claimed in claim 4, wherein the first P-type GAA nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116) and the N-type GAA nanosheet transistor (Xie G2, 120-2, 122, 112, 114, 116) share the gate electrode (Xie 150, G1-G3).
Regarding claim 6, Xie in view of Liaw and Endo teaches: The semiconductor device as claimed in claim 1, wherein the logic cell (Xie C1, ¶0051) is an inverter, a NAND gate, a NOR gate, an AND gate, an OR gate, a Flip-Flop, a SCAN, or a combination thereof (Xie “AND, NAND, OR, NOR … flip-flops” ¶0051, similar to Liaw ¶0024, 0037).
Regarding claim 22, Xie in view of Liaw, Endo, and Gomes teaches: The semiconductor device as claimed in claim 1, wherein the inter-layer dielectric (Xie 140, 142, 171) overlies the first front-side contact (Xie 161)(Xie fig 7).
Regarding claim 23, Xie in view of Liaw, Endo, and Gomes teaches: The semiconductor device as claimed in claim 1, wherein the inter-layer dielectric (Xie 140, 142, 171) is in contact with the first front-side contact (Xie 161)(Xie fig 7).
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al (US 20230207553 A1, hereafter Xie) in view of Liaw (US 20200105761 A1) and Endo et al (US 20100202208 A1, hereafter Endo), as applied to claim 1 above, and further in view of Gomes et al (US 20210134802 A1, hereafter Gomes).
Regarding claim 7, Xie in view of Liaw and Endo teaches: The semiconductor device as claimed in claim 1, including the front-side interconnect structure (Xie 160-163, 170, ¶0047), the back-side interconnect structure (Xie 105, 181-184, 190 as modified to include Endo CP10), the VDD line (Xie 196, ¶0050, “VDD”), and the VSS line (Xie 194, ¶0050, “VSS”),
wherein the VDD or VSS line is coupled to a power source (Xie ¶0002, 0050, “positive power supply voltage … and negative power supply voltage”).
Xie in view of Liaw and Endo does not teach: a power tap structure, comprising:
a tap via formed in an isolation layer between the front-side interconnect structure and the back-side interconnect structure,
wherein the VDD line or the VSS line is coupled to a power source of the front-side interconnect structure through the tap via.
Gomes, in the same field of endeavor of semiconductor device manufacturing, and in at least one embodiment, teaches: a power tap structure (Gomes 658, ¶0072, “power through electrically conductive vias extending in the z-direction”), comprising:
a tap via (Gomes 658, ¶0072, 0100, and/or BRI of “via”) formed in an isolation layer (Gomes 630 within 634, 636, 638, 656, ¶0090, at least electrically isolating) between a front-side interconnect structure (Gomes 656, similar to 634, ¶0088, 0023) and a back-side interconnect structure (Gomes 624, ¶0100, “interconnect structure 624”, 634, ¶0088, 0023)(Gomes ¶0100, fig 6E).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of Xie in view of Liaw and Endo to include the power tap structure of Gomes connected to the VDD or VSS line of Xie, and such that “wherein the VDD or VSS line is coupled to a power source of the front-side interconnect structure through the tap via”, in order to distribute power across to other vertically stacked cells (Gomes ¶0074), and/or to allow power to be distributed via front-side contacts via the front-side interconnect structure, and/or improving flexibility of electrical connections to transistors (Gomes ¶0027).
Regarding claim 8, Xie in view of Liaw, Endo, and Gomes teaches: The semiconductor device as claimed in claim 7, wherein a depth (Xie Z dir, fig 1A) of the tap via (Xie as modified to include Gomes 658) is greater than depths of the first back-side contact (Xie 184), the second back-side contact (Xie 183), the first front-side contact (Xie 161), and the second front-side contact (Xie 160)(a depth of the tap via must be greater than a depth from a top surface of Xie 190 to a bottom surface Xie 170, fig 1A, therefore the tap has a depth greater than the back-side and the front side contacts by at least the depth of Xie 124).
Claims 9, and 12-16, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al (US 20230207553 A1, hereafter Xie) in view of Liaw (US 20200105761 A1).
Regarding claim 9, Xie teaches: A semiconductor device (Xie 100, fig 1A, 1B), comprising:
a plurality of cells (Xie C1-C3, ¶0051) arranged in a cell array (Xie fig 1B) of a device region (Xie fig 1A, region between 170 and 190, best shown as 140), wherein at least one of the cells comprises:
at least one gate-all-around (GAA) nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116, “PFET”, ¶0039, 0044, 0045, a singular PFET formed by 124, G2 within 120-3, fig 1B, “plurality of PFET devices” ¶0044) having two channel members (Xie 112, 114, 116, ¶0046, at least two) vertically stacked in the device region (Xie fig 1A) and extending in a first direction (Xie, Y dir, fig 1B) from a source feature (Xie 124 right of G2 with respect to fig 1B, ¶0044, 0050) to a drain feature (Xie 124 between G1 and G2 in C1 with respect to fig 1B, ¶0044, 0050) of the at least one GAA nanosheet transistor (Xie ¶0046, 112, 114, 116 at least extend within G1-G3, between the two source/drain features 124 in the Y dir);
a dielectric layer (Xie 105, ¶0044, “insulating substrate layer 105 (e.g., buried oxide (BOX) layer 105)”) under isolation structures (Xie 137)(Xie fig 5B), wherein a sidewall of the source feature (Xie 124 right of G2 with respect to fig 1B) of the GAA nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116) is contiguous with the dielectric layer (Xie fig 1A, Xie 105 and a sidewall of 124 share a common point at an intersection of a sidewall of 124 and 105, and therefore meets a broadest reasonable interpretation of “contiguous with”);
a back-side interconnect structure (Xie 105, 181-184, 190, ¶0049) on a back-side of the device region (Xie fig 1A, ¶0049, 105, 190 are formed below 140), comprising:
a power line (Xie 196, 198, ¶0050, “backside power rails”, similar to 194) formed in a back-side metal layer (layer best shown as Xie 192 in fig 1A, in at least one embodiment 194 containing metal, ¶0099) and extending in a first direction (Xie Y dir, fig 1B),
wherein the source feature of the GAA nanosheet transistor (Xie 124 right of G2 with respect to fig 1B) is coupled to the power line (Xie 196) through a back-side contact (Xie 184, ¶0049)(Xie fig 1A, 1B) extending through the dielectric layer (Xie fig 1A); and
a front-side interconnect structure (Xie 160-163, 170, ¶0047) on a front-side of the device region (Xie fig 1A, ¶0047, 170 is formed above 140), comprising:
a front-side contact (Xie 161, ¶0047),
wherein the front-side contact is coupled to the drain feature of the GAA nanosheet transistor (Xie 124 between G1 and G2 in C1 with respect to fig 1B)(Xie fig 1A, 1B, ¶0048, 0054, 124 is coupled to 161).
Xie does not teach: a plurality of isolation structures at cell boundaries of the cells, wherein the cells in a row of the cell array are separated from each other by the isolation structures, the row extends in the first direction, a first isolation structure of the isolation structures has a first plurality of nanostructures disposed on two sides of the first isolation structure, and a second isolation structure of the isolation structures has a second plurality of nanostructures disposed on two sides of the second isolation structure; the dielectric layer under the first isolation structure and the second isolation structure;
wherein the source feature of the GAA nanosheet transistor in each of the cells in the row is coupled to the power line through a respective back-side contact; and
a plurality of front-side contacts,
wherein each of the front-side contacts is coupled to the drain feature of the GAA nanosheet transistor in each of the cells in the row.
Liaw, in the same field of endeavor of semiconductor device manufacturing, teaches: A semiconductor device (Liaw 500, fig 5A, 5D), comprising:
a plurality of cells (Liaw 260, 360, 460, 501, at least cells 1-2, 1-3, 1-4, figs 2-4, ¶0030, ¶0041) arranged in a cell array (Liaw ¶0024 “cells in an array of cells”) of a device region (Liaw ¶0037-0038);
a plurality of isolation structures (Liaw 530D, 270, 470, ¶0041) at cell boundaries of the cells (fig 5A, 2, 4, 530D at boundaries of 501), wherein the cells in a row (Liaw fig 2-4, ¶0024, Cell 1-3 and 1-4 in row, X dir, similar to Xie Y dir) of the cell array are separated from each other by the isolation structures (Liaw fig 2-4, ¶0024, 0041, 270 and 470 separate adjacent cells 1-3 and 1-4, similar to 530D separating adjacent cells 501 and 502), the row extends in a first direction (Liaw X dir)(Liaw fig 2-5), a first isolation structure (Liaw center 530D, with respect to fig 5D, ¶0041) of the isolation structures has a first plurality of nanostructures (Liaw 535SN, 535WN, fig 5A, 5D, nanosheets and nanowire both being nanostructures, ¶0002, further Applicant discloses “nanostructures 120 may also be referred to as channels, channel layers, nanosheets, or nanowires”, spec ¶0032) disposed on two sides of the first isolation structure (Liaw fig 5A, 5D), a second isolation structure (Liaw left 530D, with respect to fig 5D) of the isolation structures has a second plurality (Liaw 535SN, fig 5A, 5D) of nanostructures disposed on one side of the second isolation structure (Liaw fig 5A, 5D),
wherein a source feature (Liaw, left most 545S with respect to fig 5D, ¶0041, 0051, best shown by 550 in fig 5A) of a GAA nanosheet transistor (Liaw left 510SP with respect to fig 5A, fig 5D, ¶0039-0044, 535SP, 530S, 545S) in each of the cells in the row (Liaw ¶0024, cells 1-2, 1-3, 1-4 having at least a transistor, and therefore a source) is coupled to an interconnect layer (Liaw ¶0055-0056, at least via 570, similar to Xie 170) through a respective contact (Liaw left most 550 within 510SP with respect to fig 5A, fig 5D); and
a plurality of front-side contacts (Liaw center 550 with respect to fig 5D, fig 5A, 5D, ¶0024, cells 1-3 and 1-4 having at least a single transistor, and therefore a plurality by sum of the cells)
wherein each of the front-side contacts is coupled to a drain feature (Liaw center 545S with respect to fig 5D, ¶0051, best shown by 550 in fig 5A) of the GAA nanosheet transistor in each of the cells in the row (Liaw fig 5A, 5D, cells 1-3 and 1-4 having at least a transistor, and therefore a drain).
Xie further teaches: a plurality of cells (Xie C1-C3, ¶0051), a plurality of isolation structures (Xie 137) at cell boundaries of the cells (Xie fig 1B, CH, ¶0045),
a plurality of GAA nanosheet transistors (Xie 120-3, 124, 112, 114, 116, “PFET”) within a channel (Xie C1), the channel comprising a standard logic cell (Xie ¶0051), wherein;
a power line (Xie 196, 198, ¶0050, “backside power rails”, similar to 194) coupled to a source feature (Xie 124 ¶0044, 0050) of a P-type GAA nanosheet transistor through a back-side contact (Xie 184, ¶0049)(Xie fig 1A, 1B); and
adjusting a layout of contacts of standard logic cells to form logic gates (Xie ¶0051).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to duplicate the cell of Xie (Xie C1, similar to Liaw cells 1-2, 1-3, 1-4) in the first direction (Xie Y dir), as taught by Liaw, in order to allow combining differing types (such as nanosheet, nanowire, etc.) and/or differing circuits (such as NAND, NOR, etc.) within the same row, thereby combining the advantages within a single IC layout to improve performance and/or reduce size (Liaw ¶0015-0016, 0024, Xie ¶0005, 0051), and further to include the isolation structures (Liaw 530D, 270, 470) between cell boundaries and above the dielectric layer, and such that each isolation structure of the isolation structures has a plurality of nanostructures disposed on two sides of the each of the first and second isolation structures, in order to electrically isolate the cells (Xie ¶0045, Liaw ¶0041).
Further, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to duplicate the cell of Xie, in order to combine multiple logic gates or parts thereof, within a single device, since mere duplication of the essential working parts of a device involves only routine skill in the art (see MPEP 2144.04 VI).
Regarding claim 12, Xie in view of Liaw teaches: The semiconductor device as claimed in claim 9, wherein a gate electrode (Xie 150, G1-G3) wraps around the two channel members (Xie 112, 114, 116, ¶0046, at least two) of the at least one GAA nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116) Xie fig 5B), the gate electrode extends in a second direction (Xie, X dir, ¶0045, fig 1B, 5B, similar to Liaw Y dir), and the first direction (Xie Y dir, fig 1B, similar to Liaw X dir) is perpendicular to the second direction (Xie fig 1B, 5B, similar to Liaw 5A, 5B).
Regarding claim 13, Xie in view of Liaw teaches: The semiconductor device as claimed in claim 12, wherein at least one of the isolation structures (Xie as modified to include Liaw 530D, similar to Liaw 270, 470, and Xie 137) comprises a dielectric-base dummy gate (Liaw ¶0048, similar to Xie 137, ¶0082) extending in the second direction (Xie X dir, ¶0045, fig 5B, similar to Liaw Y dir, ¶0041 fig 5B).
Regarding claim 14, Xie in view of Liaw teaches: The semiconductor device as claimed in claim 9, wherein at least one of the isolation structures (Xie as modified to include Liaw 530D, similar to Liaw 270, 470, and Xie 137) is an oxide diffusion break (OD-break) structure (Liaw ¶0048 “530D configured as a single gate OD break”) comprising two dummy gates (Liaw 530D, fig 5A, a plurality of 530D) and a OD-break region between the two dummy gates (the region formed between active areas 535SP and 535SN, wherein 530D is disposed between, similar to applicant spec ¶0053, similar to Xie fig 1B, 6A).
Additionally, claim 14 recites the performance properties of the device, specifically “the isolation structures is an oxide diffusion break (OD-break) structure”. This functional limitation does not distinguish the claimed device over the prior art, since it appears that this limitation can be performed by the prior art structure of Xie and Liaw. While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429,1431-32 (Fed. Cir. 1997)(See MPEP 2114).
Regarding claim 15, Xie in view of Liaw teaches: The semiconductor device as claimed in claim 9, wherein at least one of the cells (Xie C1, at least as pluralized by duplication of cell C1, similar to Xie C1-C3 and Liaw 1-2, 1-3, 1-4) is an inverter, a NAND gate, a NOR gate, an AND gate, an OR gate, a Flip-Flop, a SCAN, or a combination thereof (Xie “AND, NAND, OR, NOR … flip-flops” ¶0051, similar to Liaw ¶0024, 0037).
Regarding claim 16, Xie teaches: A semiconductor device (Xie 100, fig 1A, 1B), comprising:
a logic cell (Xie C1, ¶0051) in a device region (Xie fig 1A, region between 170 and 190, best shown as 140), comprising:
a first gate-all-around (GAA) nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116, “PFET”, ¶0039, 0044, 0045, a singular PFET formed by 124, G2 within 120-3, fig 1B, “plurality of PFET devices” ¶0044); and
a second GAA nanosheet transistor (Xie G1, 120-3, 124, 112, 114, 116, “PFET”, ¶0039, 0044, 0045); and
wherein each of the first GAA nanosheet transistor and the second GAA nanosheet transistor has two channel members (Xie 112, 114, 116, ¶0046, at least two) vertically stacked in the device region (Xie fig 1A);
a dielectric layer (Xie 105, ¶0044, “insulating substrate layer 105 (e.g., buried oxide (BOX) layer 105)”) underlying the two channel members (Xie 112, 114, 116) of the first GAA nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116)(Xie fig 1A);
a back-side interconnect structure (Xie 105, 181-184, 190, ¶0049) on a back-side of the device region (Xie fig 1A, ¶0049, 105, 190 are formed below 140), comprising:
a first back-side contact (Xie 184, ¶0049) extending through the dielectric layer (Xie fig 1A); and
a power line (Xie 196, 198, ¶0050, “backside power rails”, similar to 194) formed in a back-side metal layer (layer best shown as Xie 192 in fig 1A, in at least one embodiment 194 containing metal, ¶0099), coupled to a source feature (Xie 124 right of G2 with respect to fig 1B, ¶0044, 0050) of the first GAA nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116) through the first back-side contact (Xie 184)(Xie fig 1B, ¶0050, similar to 182 fig 1A), a source feature of the second GAA nanosheet transistor (Xie 124 left of G1 with respect to fig 1B),wherein the first GAA nanosheet transistor and the second GAA nanosheet transistor share a common drain feature (Xie 124 between G1 and G2 in C1 with respect to fig 1B, ¶0044, 0050) disposed between the source feature of the first GAA nanosheet transistor (Xie 124 right of G2 with respect to fig 1B) and the source feature of the second GAA nanosheet transistor in a first direction (Xie Y-direction, fig 1B, 4A, 6A); and
a front-side interconnect structure (Xie 160-163, 170, ¶0047) on a front-side of the device region (Xie fig 1A, ¶0047, 170 is formed above 140), comprising:
a first front-side contact (Xie 161, ¶0048) coupled to the common drain feature (Xie 124 between G1 and G2 in C1 with respect to fig 1B) of the first GAA nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116) and the second GAA nanosheet transistor (Xie G1, 120-3, 124, 112, 114, 116)(Xie fig 1A, 1B, ¶0048, 0054, 124 is coupled to 161);
a first gate via (Xie 152, ¶0047) coupled to a gate (Xie G2, 150) of the first GAA nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116)(Xie fig 1B, 6A); and
a second gate via (Xie 151, ¶0047) coupled to a gate (Xie G1, 150) of the second GAA nanosheet transistor (Xie G1, 120-3, 124, 112, 114, 116)(Xie fig 1B, 6A, 6C); and
an inner spacer (Xie 136, ¶0074) disposed between the gate (Xie G2, 150) of the first GAA nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116) and the source feature (Xie 124 left of G1 with respect to fig 1B) of the first GAA nanosheet transistor (Xie fig 4B, ¶0074), wherein the inner spacer is in contact with the dielectric layer (Xie fig 4B, at least the bottom most 136 is in direct contact with 105),
wherein the common drain feature (Xie 124 between G1 and G2 in C1 with respect to fig 1B) of the first GAA nanosheet transistor and the second GAA nanosheet transistor comprises epitaxially- grown materials (Xie ¶0075, “epitaxial growth of the source/drain elements 124”), and the source feature of the first GAA nanosheet transistor (Xie 124 right of G2 with respect to fig 1B, ¶0044, 0050) comprises the epitaxially- grown materials (Xie ¶0075, “epitaxial growth of the source/drain elements 124”) and an additional implant (Xie ¶0078).
Xie does not explicitly teach: a second back-side contact;
a power line coupled to the source feature of the second GAA nanosheet transistor through the second back-side contact.
Liaw, in the same field of endeavor of semiconductor device manufacturing, teaches: A semiconductor device (Liaw 500, 510SP, fig 5A), comprising:
a first GAA nanosheet transistor (Liaw left 510SP with respect to fig 5A, fig 5D, ¶0039-0044, 535SP, 530S, 545S);
a second GAA nanosheet transistor (Liaw right 510SP with respect to fig 5A, fig 5D);
a first contact (Liaw left most 550 within 510SP with respect to fig 5A, fig 5D) and a second contact (Liaw right most 550 within 510SP with respect to fig 5A, fig 5D).
Xie further teaches: a plurality of GAA nanosheet transistors (Xie 120-3, 124, 112, 114, 116, “PFET”) within a channel (Xie C1), the channel comprising a standard logic cell (Xie ¶0051), wherein;
a power line (Xie 196, 198, ¶0050, “backside power rails”, similar to 194) coupled to a source feature (Xie 124 ¶0044, 0050) of a P-type GAA nanosheet transistor through a back-side contact (Xie 184, ¶0049)(Xie fig 1A, 1B); and
adjusting the configuration of source drain contacts and adjusting a layout contacts of standard logic cell to form logic gates (Xie ¶0051).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to duplicate first back-side contact of Xie (Xie 184) such that it is coupled to the source feature of the second GAA nanosheet transistor (Xie G1, 120-3, 124, 112, 114, 116), in order to provide functionality to the second GAA nanosheet transistor, and/or in order to form a half a NAND gate of a CMOS device (Liaw ¶0037, Xie ¶0005, 0051).
Further, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to duplicate the first back-side contact of Xie, in order to form a transistor, since mere duplication of the essential working parts of a device involves only routine skill in the art (see MPEP 2144.04 VI).
Xie in view of Liaw does not explicitly teach: wherein the front-side contact is disposed between the first gate via and the second gate via in a second direction different than the first direction.
Xie further teaches: a first gate via (Xie 152, ¶0047) coupled to a gate (Xie G2, 150) of the first GAA nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116)(Xie fig 1B, 6A); and
a second gate via (Xie 151, ¶0047) coupled to a gate (Xie G1, 150) of the second GAA nanosheet transistor (Xie G1, 120-3, 124, 112, 114, 116)(Xie fig 1B, 6A, 6C), wherein a front-side contact (Xie 160, ¶0048) is disposed between the first gate via and the second gate via in a second direction (Xie X-direction, fig 1B, 4A, 6A) different than a first direction (Xie Y-direction, fig 1B, 4A, 6A)(Xie fig 6A, at least a portion of 160 is between 151 and 152).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the relative position of the first gate via of Xie in view of Liaw, such that “the front-side contact is disposed between the first gate via and the second gate via in a second direction different than the first direction”, in order to connect the gate via to a different metal track, thereby allowing flexibility of connection and/or function of the gate (Xie ¶0048, 0093).
Regarding claim 18, Xie in view of Liaw teaches: The semiconductor device as claimed in claim 16, wherein when the first GAA nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116) is a P-type transistor (Xie “PFET”, ¶0039, 0044, 0045), the additional implant comprises Boron, BF2, Ge, or a combination thereof (Xie ¶0078, “Ge-containing source gas … boron (B) …for P-type FETs”).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Xie et al (US 20230207553 A1, hereafter Xie) in view of Liaw (US 20200105761 A1), as applied to claim 9 above, and further in view of Endo et al (US 20100202208 A1, hereafter Endo).
Regarding claim 10, Xie in view of Liaw teaches: The semiconductor device as claimed in claim 9, including the back-side interconnect structure (Xie 105, 181-184, 190, ¶0049), back-side contacts (Xie 184, ¶0049, at least as pluralized by duplication of cell C1), and the power line (Xie 196, ¶0050, “backside power rails”, similar to 194).
Xie in view of Liaw does not teach: wherein the back-side interconnect structure further comprises:
a plurality of back-side vias formed between the back-side metal layer and the back-side of the device region, wherein the power line is coupled to the back-side contacts through the back-side vias,
wherein the back-side vias are rectangular or ellipse-shaped vias.
Endo, in the same field of endeavor of semiconductor device manufacturing, and in at least one embodiment, teaches: a plurality of vias (Endo CP-10, BRI of “via”, ¶0083) formed between a metal layer (Endo 110, the layer at least contains metal, ¶0153) and a device region (Endo a region containing the device comprising at least 30-34)(Endo fig 18), wherein contacts (Endo CP30) are coupled to one of the plurality of vias (Endo fig 18),
wherein the plurality of vias are rectangular or ellipse-shaped vias (Endo fig 19).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the back-side interconnect structure of Xie in view of Liaw to include the plurality of vias of Endo, between the power line (Xie 194 and/or 196) and the back-side contacts (Xie 183, 184), and such that the limitations of the claim are met, in order to improve manufacturing yield and/or prevent an increase in contact resistance by reducing the effects of misalignment between layers of the device (Endo ¶0099, 0156).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Xie et al (US 20230207553 A1, hereafter Xie) in view of Liaw (US 20200105761 A1), as applied to claim 16 above, and further in view of Gomes et al (US 20210134802 A1, hereafter Gomes).
Regarding claim 19, Xie in view of Liaw teaches: The semiconductor device as claimed in claim 16, including the front-side interconnect structure (Xie 160-163, 170, ¶0047), the back-side interconnect structure (Xie 105, 181-184, 190, as modified to include duplicated Xie 184), and the power line (Xie 196, 198, ¶0050, “backside power rails”, similar to 194).
wherein the power line is coupled to a power source (Xie ¶0002, 0050, “positive power supply voltage … and negative power supply voltage”).
Xie in view of Liaw does not teach: a power tap structure, comprising:
a tap via formed in an isolation layer between the front-side interconnect structure and the back-side interconnect structure, wherein a power line is coupled to a power source of the front-side interconnect structure through the tap via.
Gomes, in the same field of endeavor of semiconductor device manufacturing, and in at least one embodiment, teaches: a power tap structure (Gomes 658, ¶0072, “power through electrically conductive vias extending in the z-direction”), comprising:
a tap via (Gomes 658, ¶0072, 0100, and/or BRI of “via”) formed in an isolation layer (Gomes 630 within 634, 636, 638, 656, ¶0090, at least electrically isolating) between a front-side interconnect structure (Gomes 656, similar to 634, ¶0088, 0023) and a back-side interconnect structure (Gomes 624, ¶0100, “interconnect structure 624”, 634, ¶0088, 0023)(Gomes ¶0100, fig 6E).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of Xie to include the power tap structure of Gomes connected to the power line of Xie in view of Liaw, and such that “wherein the power line is coupled to a power source of the front-side interconnect structure through the tap via”, in order to distribute power across to other vertically stacked cells (Gomes ¶0074), and/or to allow power to be distributed via front-side contacts via the front-side interconnect structure, and/or improving flexibility of electrical connections to transistors (Gomes ¶0027).
SECOND INTERPRETATION
Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al (US 20230207553 A1, hereafter Xie) in view of Liaw (US 20200105761 A1).
Regarding claim 16, Xie teaches: A semiconductor device (Xie 100, fig 1A, 1B), comprising:
a logic cell (Xie C1, ¶0051) in a device region (Xie fig 1A, region between 170 and 190, best shown as 140), comprising:
a first gate-all-around (GAA) nanosheet transistor (Xie G2, 120-2, 122, 112, 114, 116, “NFET”, ¶0039, 0044, 0045, a singular NFET formed by 122, G2 within 120-2, fig 1B, “plurality of NFET devices” ¶0044); and
a second GAA nanosheet transistor (Xie G1, 120-2, 122, 112, 114, 116, “NFET”, ¶0039, 0044, 0045); and
wherein each of the first GAA nanosheet transistor and the second GAA nanosheet transistor has two channel members (Xie 112, 114, 116, ¶0046, at least two) vertically stacked in the device region (Xie fig 1A);
a dielectric layer (Xie 105, ¶0044, “insulating substrate layer 105 (e.g., buried oxide (BOX) layer 105)”) underlying the two channel members (Xie 112, 114, 116) of the first GAA nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116)(Xie fig 1A);
a back-side interconnect structure (Xie 105, 181-184, 190, ¶0049) on a back-side of the device region (Xie fig 1A, ¶0049, 105, 190 are formed below 140), comprising:
a first back-side contact (Xie 183, ¶0049) extending through the dielectric layer (Xie fig 1A); and
a power line (Xie 194, 198, ¶0050, “backside power rails”, similar to 196) formed in a back-side metal layer (layer best shown as Xie 192 in fig 1A, in at least one embodiment 194 containing metal, ¶0099), coupled to a source feature (Xie 122 right of G2 with respect to fig 1B, ¶0044, 0050) of the first GAA nanosheet transistor (Xie G2, 120-2, 122, 112, 114, 116) through the first back-side contact (Xie 183)(Xie fig 1B, ¶0050, similar to 181 fig 1A), a source feature of the second GAA nanosheet transistor (Xie 122 left of G1 with respect to fig 1B), wherein the first GAA nanosheet transistor and the second GAA nanosheet transistor share a common drain feature (Xie 122 between G1 and G2 in C1 with respect to fig 1B, ¶0044, 0050) disposed between the source feature of the first GAA nanosheet transistor (Xie 122 right of G2 with respect to fig 1B) and the source feature of the second GAA nanosheet transistor in a first direction (Xie Y-direction, fig 1B, 4A, 6A); and
a front-side interconnect structure (Xie 160-163, 170, ¶0047) on a front-side of the device region (Xie fig 1A, ¶0047, 170 is formed above 140), comprising:
a first front-side contact (Xie 160, ¶0048) coupled to the common drain feature (Xie 122 between G1 and G2 in C1 with respect to fig 1B) of the first GAA nanosheet transistor (Xie G2, 120-2, 122, 112, 114, 116) and the second GAA nanosheet transistor (Xie G1, 120-2, 122, 112, 114, 116)(Xie fig 1A, 1B, ¶0048, 0054, 122 is coupled to 160),
a first gate via (Xie 152, ¶0047) coupled to a gate (Xie G2, 150) of the first GAA nanosheet transistor (Xie G2, 120-2, 122, 112, 114, 116)(Xie fig 1B, 6A); and
a second gate via (Xie 151, ¶0047) coupled to a gate (Xie G1, 150) of the second GAA nanosheet transistor (Xie G1, 120-2, 122, 112, 114, 116)(Xie fig 1B, 6A, 6C), wherein the front-side contact (Xie 160, ¶0048) is disposed between the first gate via and the second gate via in a second direction (Xie X-direction, fig 1B, 4A, 6A) different than the first direction (Xie Y-direction, fig 1B, 4A, 6A)(Xie fig 6A, at least a portion of 160 is between 151 and 152); and
an inner spacer (Xie 136, ¶0074) disposed between the gate (Xie G2, 150) of the first GAA nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116) and the source feature (Xie 122 left of G1 with respect to fig 1B) of the first GAA nanosheet transistor (Xie fig 4B, ¶0074), wherein the inner spacer is in contact with the dielectric layer (Xie fig 4B, at least the bottom most 136 is in direct contact with 105),
wherein the common drain feature (Xie 122 between G1 and G2 in C1 with respect to fig 1B) of the first GAA nanosheet transistor and the second GAA nanosheet transistor comprises epitaxially- grown materials (Xie ¶0075, “epitaxial growth of the source/drain elements 122”), and the source feature of the first GAA nanosheet transistor (Xie 122 right of G2 with respect to fig 1B, ¶0044, 0050) comprises the epitaxially- grown materials (Xie ¶0075, “epitaxial growth of the source/drain elements 122”) and an additional implant (Xie ¶0078).
Xie does not explicitly teach: a second back-side contact;
a power line coupled to a source feature of the second GAA nanosheet transistor through the second back-side contact.
Liaw, in the same field of endeavor of semiconductor device manufacturing, teaches: A semiconductor device (Liaw 500, 510SN, fig 5A), comprising:
a first GAA nanosheet transistor (Liaw left 510SN with respect to fig 5A, fig 5D, ¶0039-0044, 535SN, 530S, 545S);
a second GAA nanosheet transistor (Liaw right 510SN with respect to fig 5A, fig 5D);
a first contact (Liaw left most 550 within 510SN with respect to fig 5A, fig 5D) and a second contact (Liaw right most 550 within 510SN with respect to fig 5A, fig 5D).
Xie further teaches: a plurality of GAA nanosheet transistors (Xie 120-2, 122, 112, 114, 116, “NFET”) within a channel (Xie C1), the channel comprising a standard logic cell (Xie ¶0051), wherein;
a power line (Xie 194, 198, ¶0050, “backside power rails”, similar to 196) coupled to a source feature (Xie 122 ¶0044, 0050) of a N-type GAA nanosheet transistor through a back-side contact (Xie 183, ¶0049)(Xie fig 1A, 1B); and
adjusting the configuration of source drain contacts and adjusting a layout contacts of standard logic cell to form logic gates (Xie ¶0051).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to duplicate the first back-side contact of Xie (Xie 183) such that it is coupled to the source feature of the second GAA nanosheet transistor (Xie G1, 120-2, 122, 112, 114, 116), in order to provide functionality to the second GAA nanosheet transistor, and/or in order to form a half a NAND gate of a CMOS device (Liaw ¶0037, Xie ¶0005, 0051).
Further, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to duplicate the first back-side contact of Xie, in order to form a transistor, since mere duplication of the essential working parts of a device involves only routine skill in the art (see MPEP 2144.04 VI).
Regarding claim 17, Xie in view of Liaw teaches: The semiconductor device as claimed in claim 16, wherein when the first GAA nanosheet transistor (Xie G2, 120-2, 122, 112, 114, 116) is an N-type transistor (Xie “NFET”, ¶0039, 0044, 0045), the additional implant comprises phosphorus, Arsenic, Ge, or a combination thereof (Xie ¶0078, “Ge-containing source gas … phosphorus (P) or arsenic (As) … for N-type FETs”).
Response to Arguments
Applicant's arguments filed 12/04/2025 have been fully considered but they are not persuasive. Applicant argues that the prior cited art does not teach or suggest the amended claims. The Examiner respectfully disagrees, it appears that Xie teaches the amended limitations of independent claims 1, 9, and 16, as set forth in the above rejections.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS B. MICHAUD whose telephone number is (703)756-1796. The examiner can normally be reached Monday-Friday, 0800-1700 Eastern Time.
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/NICHOLAS B. MICHAUD/
EXAMINER
Art Unit 2818
/Mounir S Amer/Primary Examiner, Art Unit 2818