DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/28/2026 has been entered.
Status of the Application
Claims 1-5, 7-10, 12-14, 16-19, and 22-25 remain pending in this application. Acknowledgement is made of the amendment received 04/28/2026. Claims 6 and 15 are canceled, claims 1, 9, and 16 are amended, and claims 24 and 25 are added for consideration.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-5, and 22-24 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al (US 20230207553 A1, hereafter Xie) in view of Liaw (US 20200105761 A1), Endo et al (US 20100202208 A1, hereafter Endo), and Peng et al (US 20170110405 A1, hereafter Peng).
Regarding claim 1, Xie teaches: A semiconductor device (Xie 100, fig 1A, 1B), comprising:
a logic cell (Xie C1, ¶0051) in a device region (Xie fig 1A, region between 170 and 190, best shown as 140), comprising:
a first P-type gate-all-around (GAA) nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116, “PFET”, ¶0039, 0044, 0045, a singular PFET formed by 124, G2 within 120-3, fig 1B, “plurality of PFET devices” ¶0044);
a second P-type GAA nanosheet transistor (Xie G1, 120-3, 124, 112, 114, 116, “PFET”, ¶0039, 0044, 0045); and
an N-type GAA nanosheet transistor (Xie G2, 120-2, 122, 112, 114, 116, “NFET”, ¶0039, 0044, a singular NFET formed by 122, G1 within 120-2, fig 1B, “plurality of NFET devices” ¶0044, 0045);
wherein each of the first P-type GAA nanosheet transistor, the second P-type GAA nanosheet transistor and the N-type GAA nanosheet transistor has two channel members (Xie 112, 114, 116, ¶0046, at least two) vertically stacked in the device region (Xie fig 1A);
a back-side interconnect structure (Xie 105, 181-184, 190, ¶0049) on a back-side of the device region (Xie fig 1A, ¶0049, 105, 190 are formed below 140), comprising:
a first back-side contact (Xie 184, ¶0049), a second back-side contact (Xie 183, ¶0049);
a VDD line (Xie 196, ¶0050, “VDD”) formed in a back-side metal layer (layer best shown as Xie 192 in fig 1A, in at least one embodiment 194 containing metal, ¶0099), coupled to a source feature (Xie 124 right of G2 with respect to fig 1B, ¶0044, 0050) of the first P-type GAA nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116) through the first back-side contact (Xie 184)(Xie fig 1B, ¶0050, similar to 182 fig 1A), wherein the first P-type GAA nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116) and the second P-type GAA nanosheet transistor (Xie G1, 120-3, 124, 112, 114, 116) share a common drain feature (Xie 124 between G1 and G2 in C1 with respect to fig 1B, ¶0044, 0050), wherein a longest dimension of the VDD line extends in a first direction (Xie Y dir, fig 1B)(Xie fig 1B); and
a VSS line (Xie 194, ¶0050, “VSS”) formed in the back-side metal layer (layer best shown as Xie 192 in fig 1A) and coupled to a source feature (Xie 122 right of G2 with respect to fig 1B, ¶0044) of the N-type GAA nanosheet transistor (Xie G2, 120-2, 122, 112, 114, 116) through the second back-side contact (Xie 183)(Xie fig 1B, ¶0050, the examiner interprets “the backside source/drain contacts 181 and 184 (which are connected to the backside power rail 194)” to be a typo based on fig 1B and the context of the paragraph, and that it should read “backside source/drain contacts 181 and 183”, similar to 181 fig 1A); and
a back-side metal line (Xie 198) disposed below the VSS line and coupled to the VSS line (Xie ¶0049-0050, fig 1A), wherein the back-side metal line has a first width in the first direction (Xie fig 1A);
a front-side interconnect structure (Xie 160-163, 170, ¶0047) on a front-side of the device region (Xie fig 1A, ¶0047, 170 is formed above 140), comprising:
a first front-side contact (Xie 161, ¶0048) and a second front-side contact (Xie 160, ¶0048); and
at least one metal line (Xie T6 or T3, ¶0048) coupled to the common drain feature (Xie 124 between G1 and G2 in C1 with respect to fig 1B) of the first P-type GAA nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116) and the second P-type GAA nanosheet transistor (Xie G1, 120-3, 124, 112, 114, 116) through the first front-side contact (Xie 161)(Xie fig 1A, T6 is coupled to 161 at least via 175, ¶0048, 0054) or coupled to a drain feature (Xie 122 between G1 and G2 in C1 with respect to fig 1B) of the N-type GAA nanosheet transistor (Xie G2, 120-2, 122, 112, 114, 116) through the second front-side contact (Xie 160)(Xie fig 1A, T3 is coupled to 160 at least via 174, ¶0048, 0054);
an inter-layer dielectric (Xie 140, 142, 171) over the source feature (Xie 124 right of G2 with respect to fig 1B) of the first P-type GAA nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116)(Xie fig 1A).
Xie does not explicitly teach: a third back-side contact;
a VDD line coupled to a source feature of the second P-type GAA nanosheet transistor through the third back-side contact.
Liaw, in the same field of endeavor of semiconductor device manufacturing, teaches: A semiconductor device (Liaw 500, 510SP, fig 5A), comprising:
a first P-type GAA nanosheet transistor (Liaw left 510SP with respect to fig 5A, fig 5D, ¶0039-0044, 535SP, 530S, 545S);
a second P-type GAA nanosheet transistor (Liaw right 510SP with respect to fig 5A, fig 5D); and an N-type GAA nanosheet transistor (Liaw 510SN);
a first contact (Liaw left most 550 within 510SP with respect to fig 5A, fig 5D), a second contact (Liaw center 550 within 510SP with respect to fig 5A, fig 5D), and a third contact (Liaw right most 550 within 510SP with respect to fig 5A, fig 5D).
Xie further teaches: a plurality of P-type GAA nanosheet transistors (Xie 120-3, 124, 112, 114, 116, “PFET”) within a channel (Xie C1), the channel comprising a standard logic cell (Xie ¶0051), wherein;
a VDD line (Xie 196, ¶0050, “VDD”) coupled to a source feature (Xie 124 ¶0044, 0050) of a P-type GAA nanosheet transistor through a back-side contact (Xie 184, ¶0049)(Xie fig 1A, 1B); and
adjusting the configuration of source drain contacts and adjusting a layout of contacts of standard logic cell to form logic gates (Xie ¶0051).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to duplicate the first back-side contact of Xie (Xie 184) such that it is coupled to the source feature of the second P-type GAA nanosheet transistor (Xie G1, 120-3, 124, 112, 114, 116), in order to provide functionality to the second P-type GAA nanosheet transistor, and/or in order to form a half a NAND gate of a CMOS device (Liaw ¶0037, Xie ¶0005, 0051).
Further, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to duplicate first back-side contact of Xie, in order to form a transistor, since mere duplication of the essential working parts of a device involves only routine skill in the art (see MPEP 2144.04 VI).
Xie in view of Liaw does not teach: a first back-side via disposed between the VDD line and the first back-side contact and coupling the VDD line to the first back-side contact, wherein a longest dimension of the first back-side via extends in a second direction different than the first direction.
Xie further teaches: using a via (Xie 174) to couple a contact (Xie 160) and a metal line (Xie T3) within an interconnect structure (Xie 170)(Xie fig 1A).
Endo, in the same field of endeavor of semiconductor device manufacturing, and in at least one embodiment, teaches: a first via (CP10, BRI of “via”, ¶0083), wherein a longest dimension of the via (Endo dp_rect) extends in a second direction (Endo Gate width direction, fig 4, 11B, similar to Xie X-dir)(Endo fig 11B) different than a first direction (Endo Gate length direction, fig 4, 11B, ¶0079, similar to Xie Y-dir)(Endo fig 11B).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the first via of Endo, between the VDD line and first back-side contact of Xie in view of Liaw, such that “a first back-side via disposed between the VDD line and the first back-side contact and coupling the VDD line to the first back-side contact, wherein a longest dimension of the first back-side via extends in a second direction different than the first direction”, in order to increase an alignment margin in the second direction (Endo ¶0099), thereby ensuring sufficient contact and/or suppressing an increase in contact resistance (Endo ¶0156) between the VDD line and the first back-side contact of Xie in view of Liaw due to misalignment.
Xie in view of Liaw and Endo does not teach: wherein the at least one metal line has a second width in the first direction, and the second width is less than the first width.
Peng, in the same field of endeavor of semiconductor device manufacturing, teaches: a first metal line (Peng 206, ¶0033) has a first width (Peng wa, ¶0034) in a first direction (Peng 112, ¶0032)(Peng fig 3A), wherein a second metal line (Peng 304) has a second width (Peng fig 3A) in the first direction (Peng fig 3A), and the second width is less than a first width (Peng fig 3A).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the first width of the metal line of Xie in view of Liaw and Endo, such that “wherein the at least one metal line has a second width in the first direction, and the second width is less than the first width”, as taught by Peng, in order to reduce current density in the back side power distribution network, thereby improving electromigration and IR specs (Peng ¶0083), while maintaining front side routing space (Xie ¶0003).
Regarding claim 2, Xie in view of Liaw, Endo, and Peng teaches: The semiconductor device as claimed in claim 1, wherein the VSS line (Xie 194, ¶0050, “VSS”) is coupled to the second back-side contact (Xie 183, ¶0049); and
wherein the first back-side via (Endo CP10) has a rectangular shape or an elliptical shape (Endo fig 4, 11B).
Xie in view of Liaw, Endo, and Peng does not explicitly teach: wherein the back-side interconnect structure further comprises: a second back-side via formed between the back-side metal layer and the back-side of the device region, wherein the VSS line is coupled to the second back-side contact through the second back-side via;
wherein the second back-side via have a rectangular shape or an elliptical shape.
Endo further teaches: a plurality of vias (Endo CP-10, BRI of “via”, ¶0083).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to duplicate the first via of Xie in view of Liaw, Endo, and Peng, such that “the back-side interconnect structure further comprises: a second back-side via formed between the back-side metal layer and the back-side of the device region, wherein the VSS line is coupled to the second back-side contact through the second back-side via; wherein the second back-side via have a rectangular shape or an elliptical shape”, in order to increase an alignment margin in the second direction (Endo ¶0099), thereby ensuring sufficient contact and/or suppressing an increase in contact resistance (Endo ¶0156) between the VSS line and the second back-side contact of Xie in view of Liaw and Endo due to misalignment.
Further, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to duplicate the first via of Xie in view of Liaw, Endo, and Peng, since mere duplication of the essential working parts of a device involves only routine skill in the art (see MPEP 2144.04 VI).
Regarding claim 3, Xie in view of Liaw, Endo, and Peng teaches: The semiconductor device as claimed in claim 2, wherein the first back-side via and second back-side via (Xie 181-184, 190, as modified to include Endo CP10) have a dimension ratio of long side (Endo dp_rect, ¶0154, 0079, similar to c1, ¶0083) to short side (Endo dp_min, ¶0154, 0079, similar to a3, ¶0083) that is within a range of 1.2 to 5 (¶0080-0083, dp_rect=2*dp_min+Sp_min=(2*70nm)+(200nm)=340nm → ratio dp_rect:dp_min=340nm:70nm=4.85:1, similar to ratio c1:a3=290nm:60nm=4.83:1, fig 10).
Regarding claim 4, Xie in view of Liaw, Endo, and Peng teaches: The semiconductor device as claimed in claim 1, wherein the VSS line (Xie 194, ¶0050, “VSS”) extends in the first direction (Xie Y dir, fig 1B), and a gate electrode (Xie 150, G1-G3) wrapping around the two channel members (Xie 112, 114, 116, ¶0046, at least two)(Xie fig 5B) of the first P-type GAA nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116) or the N-type GAA nanosheet transistor (Xie G2, 120-2, 122, 112, 114, 116)(Xie fig 5B) extends in the second direction (Xie X dir, ¶0045, fig 1B), wherein the first direction is perpendicular to the second direction (Xie fig 1B, 5B).
Regarding claim 5, Xie in view of Liaw, Endo, and Peng teaches: The semiconductor device as claimed in claim 4, wherein the first P-type GAA nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116) and the N-type GAA nanosheet transistor (Xie G2, 120-2, 122, 112, 114, 116) share the gate electrode (Xie 150, G1-G3).
Regarding claim 22, Xie in view of Liaw, Endo, and Peng teaches: The semiconductor device as claimed in claim 1, wherein the inter-layer dielectric (Xie 140, 142, 171) overlies the first front-side contact (Xie 161)(Xie fig 7).
Regarding claim 23, Xie in view of Liaw, Endo, and Peng teaches: The semiconductor device as claimed in claim 1, wherein the inter-layer dielectric (Xie 140, 142, 171) is in contact with the first front-side contact (Xie 161)(Xie fig 7).
Regarding claim 24, Xie in view of Liaw, Endo, and Peng teaches: The semiconductor device as claimed in claim 1, wherein a sidewall of the inter-layer dielectric (Xie 140, 142, 171) interfaces with a sidewall of at least one of the first front-side contact (Xie 161) or the second front-side contact (Xie 160)(Xie fig 7).
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al (US 20230207553 A1, hereafter Xie) in view Liaw (US 20200105761 A1), Endo et al (US 20100202208 A1, hereafter Endo), and Peng et al (US 20170110405 A1, hereafter Peng), as applied to claim 1 above, and further in view of Gomes et al (US 20210134802 A1, hereafter Gomes).
Regarding claim 7, Xie in view of Liaw, Endo, and Peng teaches: The semiconductor device as claimed in claim 1, including the front-side interconnect structure (Xie 160-163, 170, ¶0047), the back-side interconnect structure (Xie 105, 181-184, 190 as modified to include Endo CP10), the VDD line (Xie 196, ¶0050, “VDD”), and the VSS line (Xie 194, ¶0050, “VSS”),
wherein the VDD or VSS line is coupled to a power source (Xie ¶0002, 0050, “positive power supply voltage … and negative power supply voltage”).
Xie in view of Liaw, Endo, and Peng does not teach: a power tap structure, comprising:
a tap via formed in an isolation layer between the front-side interconnect structure and the back-side interconnect structure,
wherein the VDD line or the VSS line is coupled to a power source of the front-side interconnect structure through the tap via.
Gomes, in the same field of endeavor of semiconductor device manufacturing, and in at least one embodiment, teaches: a power tap structure (Gomes 658, ¶0072, “power through electrically conductive vias extending in the z-direction”), comprising:
a tap via (Gomes 658, ¶0072, 0100, and/or BRI of “via”) formed in an isolation layer (Gomes 630 within 634, 636, 638, 656, ¶0090, at least electrically isolating) between a front-side interconnect structure (Gomes 656, similar to 634, ¶0088, 0023) and a back-side interconnect structure (Gomes 624, ¶0100, “interconnect structure 624”, 634, ¶0088, 0023)(Gomes ¶0100, fig 6E).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of Xie in view of Liaw, Endo, and Peng to include the power tap structure of Gomes connected to the VDD or VSS line of Xie, and such that “wherein the VDD or VSS line is coupled to a power source of the front-side interconnect structure through the tap via”, in order to distribute power across to other vertically stacked cells (Gomes ¶0074), and/or to allow power to be distributed via front-side contacts via the front-side interconnect structure, and/or improving flexibility of electrical connections to transistors (Gomes ¶0027).
Regarding claim 8, Xie in view of Liaw, Endo, Peng, and Gomes teaches: The semiconductor device as claimed in claim 7, wherein a depth (Xie Z dir, fig 1A) of the tap via (Xie as modified to include Gomes 658) is greater than depths of the first back-side contact (Xie 184), the second back-side contact (Xie 183), the first front-side contact (Xie 161), and the second front-side contact (Xie 160)(a depth of the tap via must be greater than a depth from a top surface of Xie 190 to a bottom surface Xie 170, fig 1A, therefore the tap has a depth greater than the back-side and the front side contacts by at least the depth of Xie 124).
Claims 16, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al (US 20230207553 A1, hereafter Xie) in view of Liaw (US 20200105761 A1) and Block et al (US 20200035560 A1, hereafter Block).
Regarding claim 16, Xie teaches: A semiconductor device (Xie 100, fig 1A, 1B), comprising:
a logic cell (Xie C1, ¶0051) in a device region (Xie fig 1A, region between 170 and 190, best shown as 140), comprising:
a first gate-all-around (GAA) nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116, “PFET”, ¶0039, 0044, 0045, a singular PFET formed by 124, G2 within 120-3, fig 1B, “plurality of PFET devices” ¶0044); and
a second GAA nanosheet transistor (Xie G1, 120-3, 124, 112, 114, 116, “PFET”, ¶0039, 0044, 0045); and
wherein each of the first GAA nanosheet transistor and the second GAA nanosheet transistor has two channel members (Xie 112, 114, 116, ¶0046, at least two) vertically stacked in the device region (Xie fig 1A);
a dielectric layer (Xie 105, ¶0044, “insulating substrate layer 105 (e.g., buried oxide (BOX) layer 105)”) underlying the two channel members (Xie 112, 114, 116) of the first GAA nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116)(Xie fig 1A);
a back-side interconnect structure (Xie 105, 181-184, 190, ¶0049) on a back-side of the device region (Xie fig 1A, ¶0049, 105, 190 are formed below 140), comprising:
a first back-side contact (Xie 184, ¶0049) extending through the dielectric layer (Xie fig 1A); and
a power line (Xie 196, 198, ¶0050, “backside power rails”, similar to 194) formed in a back-side metal layer (layer best shown as Xie 192 in fig 1A, in at least one embodiment 194 containing metal, ¶0099), coupled to a source feature (Xie 124 right of G2 with respect to fig 1B, ¶0044, 0050) of the first GAA nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116) through the first back-side contact (Xie 184)(Xie fig 1B, ¶0050, similar to 182 fig 1A), a source feature of the second GAA nanosheet transistor (Xie 124 left of G1 with respect to fig 1B),wherein the first GAA nanosheet transistor and the second GAA nanosheet transistor share a common drain feature (Xie 124 between G1 and G2 in C1 with respect to fig 1B, ¶0044, 0050) disposed between the source feature of the first GAA nanosheet transistor (Xie 124 right of G2 with respect to fig 1B) and the source feature of the second GAA nanosheet transistor in a first direction (Xie Y-direction, fig 1B, 4A, 6A); and
a front-side interconnect structure (Xie 160-163, 170, ¶0047) on a front-side of the device region (Xie fig 1A, ¶0047, 170 is formed above 140), comprising:
a first front-side contact (Xie 161, ¶0048) coupled to the common drain feature (Xie 124 between G1 and G2 in C1 with respect to fig 1B) of the first GAA nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116) and the second GAA nanosheet transistor (Xie G1, 120-3, 124, 112, 114, 116)(Xie fig 1A, 1B, ¶0048, 0054, 124 is coupled to 161);
a first gate via (Xie 152, ¶0047) coupled to a gate (Xie G2, 150) of the first GAA nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116)(Xie fig 1B, 6A); and
a second gate via (Xie 151, ¶0047) coupled to a gate (Xie G1, 150) of the second GAA nanosheet transistor (Xie G1, 120-3, 124, 112, 114, 116)(Xie fig 1B, 6A, 6C); and
an inner spacer (Xie 136, ¶0074) disposed between the gate (Xie G2, 150) of the first GAA nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116) and the source feature (Xie 124 left of G1 with respect to fig 1B) of the first GAA nanosheet transistor (Xie fig 4B, ¶0074), wherein the inner spacer is in contact with the dielectric layer (Xie fig 4B, at least the bottom most 136 is in direct contact with 105),
wherein the common drain feature (Xie 124 between G1 and G2 in C1 with respect to fig 1B) of the first GAA nanosheet transistor and the second GAA nanosheet transistor comprises epitaxially- grown materials (Xie ¶0075, “epitaxial growth of the source/drain elements 124”), and the source feature of the first GAA nanosheet transistor (Xie 124 right of G2 with respect to fig 1B, ¶0044, 0050) comprises the epitaxially- grown materials (Xie ¶0075, “epitaxial growth of the source/drain elements 124”) and an additional implant (Xie ¶0078).
Xie does not explicitly teach: a second back-side contact;
a power line coupled to the source feature of the second GAA nanosheet transistor through the second back-side contact.
Liaw, in the same field of endeavor of semiconductor device manufacturing, teaches: A semiconductor device (Liaw 500, 510SP, fig 5A), comprising:
a first GAA nanosheet transistor (Liaw left 510SP with respect to fig 5A, fig 5D, ¶0039-0044, 535SP, 530S, 545S);
a second GAA nanosheet transistor (Liaw right 510SP with respect to fig 5A, fig 5D);
a first contact (Liaw left most 550 within 510SP with respect to fig 5A, fig 5D) and a second contact (Liaw right most 550 within 510SP with respect to fig 5A, fig 5D).
Xie further teaches: a plurality of GAA nanosheet transistors (Xie 120-3, 124, 112, 114, 116, “PFET”) within a channel (Xie C1), the channel comprising a standard logic cell (Xie ¶0051), wherein;
a power line (Xie 196, 198, ¶0050, “backside power rails”, similar to 194) coupled to a source feature (Xie 124 ¶0044, 0050) of a P-type GAA nanosheet transistor through a back-side contact (Xie 184, ¶0049)(Xie fig 1A, 1B); and
adjusting the configuration of source drain contacts and adjusting a layout contacts of standard logic cell to form logic gates (Xie ¶0051).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to duplicate first back-side contact of Xie (Xie 184) such that it is coupled to the source feature of the second GAA nanosheet transistor (Xie G1, 120-3, 124, 112, 114, 116), in order to provide functionality to the second GAA nanosheet transistor, and/or in order to form a half a NAND gate of a CMOS device (Liaw ¶0037, Xie ¶0005, 0051).
Further, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to duplicate the first back-side contact of Xie, in order to form a transistor, since mere duplication of the essential working parts of a device involves only routine skill in the art (see MPEP 2144.04 VI).
Xie in view of Liaw does not explicitly teach: wherein the front-side contact is disposed between the first gate via and the second gate via in a second direction different than the first direction.
Xie further teaches: a first gate via (Xie 152, ¶0047) coupled to a gate (Xie G2, 150) of the first GAA nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116)(Xie fig 1B, 6A); and
a second gate via (Xie 151, ¶0047) coupled to a gate (Xie G1, 150) of the second GAA nanosheet transistor (Xie G1, 120-3, 124, 112, 114, 116)(Xie fig 1B, 6A, 6C), wherein a front-side contact (Xie 160, ¶0048) is disposed between the first gate via and the second gate via in a second direction (Xie X-direction, fig 1B, 4A, 6A) different than a first direction (Xie Y-direction, fig 1B, 4A, 6A)(Xie fig 6A, at least a portion of 160 is between 151 and 152).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the relative position of the first gate via of Xie in view of Liaw, such that “the front-side contact is disposed between the first gate via and the second gate via in a second direction different than the first direction”, in order to connect the gate via to a different metal track, thereby allowing flexibility of connection and/or function of the gate (Xie ¶0048, 0093).
Xie in view of Liaw does not teach: a composition of the common drain feature of the first GAA nanosheet transistor and the second GAA nanosheet transistor is different than a composition of the source feature of the first GAA nanosheet transistor.
Block, in the same field of endeavor of semiconductor device manufacturing, teaches: adjusting a composition of a common source/drain feature (Block 640, ¶0181, 0300, raising a dopant concentration of a backside source/drain).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to adjust the composition of the source feature of the first GAA nanosheet transistor of Xie in view of Liaw, such that “a composition of the common drain feature of the first GAA nanosheet transistor and the second GAA nanosheet transistor is different than a composition of the source feature of the first GAA nanosheet transistor”, as taught by Block, in order to form asymmetric source and drain compositions, thereby reducing the contact resistance of a backside contact (Block ¶0162, 0174, 0181).
Regarding claim 18, Xie in view of Liaw and Block teaches: The semiconductor device as claimed in claim 16, wherein when the first GAA nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116) is a P-type transistor (Xie “PFET”, ¶0039, 0044, 0045), the additional implant comprises Boron, BF2, Ge, or a combination thereof (Xie ¶0078, “Ge-containing source gas … boron (B) …for P-type FETs”).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Xie et al (US 20230207553 A1, hereafter Xie) in view of Liaw (US 20200105761 A1) and Block et al (US 20200035560 A1, hereafter Block), as applied to claim 16 above, and further in view of Gomes et al (US 20210134802 A1, hereafter Gomes).
Regarding claim 19, Xie in view of Liaw and Block teaches: The semiconductor device as claimed in claim 16, including the front-side interconnect structure (Xie 160-163, 170, ¶0047), the back-side interconnect structure (Xie 105, 181-184, 190, as modified to include duplicated Xie 184), and the power line (Xie 196, 198, ¶0050, “backside power rails”, similar to 194).
wherein the power line is coupled to a power source (Xie ¶0002, 0050, “positive power supply voltage … and negative power supply voltage”).
Xie in view of Liaw and Block does not teach: a power tap structure, comprising:
a tap via formed in an isolation layer between the front-side interconnect structure and the back-side interconnect structure, wherein a power line is coupled to a power source of the front-side interconnect structure through the tap via.
Gomes, in the same field of endeavor of semiconductor device manufacturing, and in at least one embodiment, teaches: a power tap structure (Gomes 658, ¶0072, “power through electrically conductive vias extending in the z-direction”), comprising:
a tap via (Gomes 658, ¶0072, 0100, and/or BRI of “via”) formed in an isolation layer (Gomes 630 within 634, 636, 638, 656, ¶0090, at least electrically isolating) between a front-side interconnect structure (Gomes 656, similar to 634, ¶0088, 0023) and a back-side interconnect structure (Gomes 624, ¶0100, “interconnect structure 624”, 634, ¶0088, 0023)(Gomes ¶0100, fig 6E).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of Xie in view of Liaw and Block to include the power tap structure of Gomes connected to the power line of Xie in view of Liaw and Block, and such that “wherein the power line is coupled to a power source of the front-side interconnect structure through the tap via”, in order to distribute power across to other vertically stacked cells (Gomes ¶0074), and/or to allow power to be distributed via front-side contacts via the front-side interconnect structure, and/or improving flexibility of electrical connections to transistors (Gomes ¶0027).
SECOND INTERPRETATION
Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al (US 20230207553 A1, hereafter Xie) in view of Liaw (US 20200105761 A1) and Block et al (US 20200035560 A1, hereafter Block).
Regarding claim 16, Xie teaches: A semiconductor device (Xie 100, fig 1A, 1B), comprising:
a logic cell (Xie C1, ¶0051) in a device region (Xie fig 1A, region between 170 and 190, best shown as 140), comprising:
a first gate-all-around (GAA) nanosheet transistor (Xie G2, 120-2, 122, 112, 114, 116, “NFET”, ¶0039, 0044, 0045, a singular NFET formed by 122, G2 within 120-2, fig 1B, “plurality of NFET devices” ¶0044); and
a second GAA nanosheet transistor (Xie G1, 120-2, 122, 112, 114, 116, “NFET”, ¶0039, 0044, 0045); and
wherein each of the first GAA nanosheet transistor and the second GAA nanosheet transistor has two channel members (Xie 112, 114, 116, ¶0046, at least two) vertically stacked in the device region (Xie fig 1A);
a dielectric layer (Xie 105, ¶0044, “insulating substrate layer 105 (e.g., buried oxide (BOX) layer 105)”) underlying the two channel members (Xie 112, 114, 116) of the first GAA nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116)(Xie fig 1A);
a back-side interconnect structure (Xie 105, 181-184, 190, ¶0049) on a back-side of the device region (Xie fig 1A, ¶0049, 105, 190 are formed below 140), comprising:
a first back-side contact (Xie 183, ¶0049) extending through the dielectric layer (Xie fig 1A); and
a power line (Xie 194, 198, ¶0050, “backside power rails”, similar to 196) formed in a back-side metal layer (layer best shown as Xie 192 in fig 1A, in at least one embodiment 194 containing metal, ¶0099), coupled to a source feature (Xie 122 right of G2 with respect to fig 1B, ¶0044, 0050) of the first GAA nanosheet transistor (Xie G2, 120-2, 122, 112, 114, 116) through the first back-side contact (Xie 183)(Xie fig 1B, ¶0050, similar to 181 fig 1A), a source feature of the second GAA nanosheet transistor (Xie 122 left of G1 with respect to fig 1B), wherein the first GAA nanosheet transistor and the second GAA nanosheet transistor share a common drain feature (Xie 122 between G1 and G2 in C1 with respect to fig 1B, ¶0044, 0050) disposed between the source feature of the first GAA nanosheet transistor (Xie 122 right of G2 with respect to fig 1B) and the source feature of the second GAA nanosheet transistor in a first direction (Xie Y-direction, fig 1B, 4A, 6A); and
a front-side interconnect structure (Xie 160-163, 170, ¶0047) on a front-side of the device region (Xie fig 1A, ¶0047, 170 is formed above 140), comprising:
a first front-side contact (Xie 160, ¶0048) coupled to the common drain feature (Xie 122 between G1 and G2 in C1 with respect to fig 1B) of the first GAA nanosheet transistor (Xie G2, 120-2, 122, 112, 114, 116) and the second GAA nanosheet transistor (Xie G1, 120-2, 122, 112, 114, 116)(Xie fig 1A, 1B, ¶0048, 0054, 122 is coupled to 160),
a first gate via (Xie 152, ¶0047) coupled to a gate (Xie G2, 150) of the first GAA nanosheet transistor (Xie G2, 120-2, 122, 112, 114, 116)(Xie fig 1B, 6A); and
a second gate via (Xie 151, ¶0047) coupled to a gate (Xie G1, 150) of the second GAA nanosheet transistor (Xie G1, 120-2, 122, 112, 114, 116)(Xie fig 1B, 6A, 6C), wherein the front-side contact (Xie 160, ¶0048) is disposed between the first gate via and the second gate via in a second direction (Xie X-direction, fig 1B, 4A, 6A) different than the first direction (Xie Y-direction, fig 1B, 4A, 6A)(Xie fig 6A, at least a portion of 160 is between 151 and 152); and
an inner spacer (Xie 136, ¶0074) disposed between the gate (Xie G2, 150) of the first GAA nanosheet transistor (Xie G2, 120-3, 124, 112, 114, 116) and the source feature (Xie 122 left of G1 with respect to fig 1B) of the first GAA nanosheet transistor (Xie fig 4B, ¶0074), wherein the inner spacer is in contact with the dielectric layer (Xie fig 4B, at least the bottom most 136 is in direct contact with 105),
wherein the common drain feature (Xie 122 between G1 and G2 in C1 with respect to fig 1B) of the first GAA nanosheet transistor and the second GAA nanosheet transistor comprises epitaxially- grown materials (Xie ¶0075, “epitaxial growth of the source/drain elements 122”), and the source feature of the first GAA nanosheet transistor (Xie 122 right of G2 with respect to fig 1B, ¶0044, 0050) comprises the epitaxially- grown materials (Xie ¶0075, “epitaxial growth of the source/drain elements 122”) and an additional implant (Xie ¶0078).
Xie does not explicitly teach: a second back-side contact;
a power line coupled to a source feature of the second GAA nanosheet transistor through the second back-side contact.
Liaw, in the same field of endeavor of semiconductor device manufacturing, teaches: A semiconductor device (Liaw 500, 510SN, fig 5A), comprising:
a first GAA nanosheet transistor (Liaw left 510SN with respect to fig 5A, fig 5D, ¶0039-0044, 535SN, 530S, 545S);
a second GAA nanosheet transistor (Liaw right 510SN with respect to fig 5A, fig 5D);
a first contact (Liaw left most 550 within 510SN with respect to fig 5A, fig 5D) and a second contact (Liaw right most 550 within 510SN with respect to fig 5A, fig 5D).
Xie further teaches: a plurality of GAA nanosheet transistors (Xie 120-2, 122, 112, 114, 116, “NFET”) within a channel (Xie C1), the channel comprising a standard logic cell (Xie ¶0051), wherein;
a power line (Xie 194, 198, ¶0050, “backside power rails”, similar to 196) coupled to a source feature (Xie 122 ¶0044, 0050) of a N-type GAA nanosheet transistor through a back-side contact (Xie 183, ¶0049)(Xie fig 1A, 1B); and
adjusting the configuration of source drain contacts and adjusting a layout contacts of standard logic cell to form logic gates (Xie ¶0051).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to duplicate the first back-side contact of Xie (Xie 183) such that it is coupled to the source feature of the second GAA nanosheet transistor (Xie G1, 120-2, 122, 112, 114, 116), in order to provide functionality to the second GAA nanosheet transistor, and/or in order to form a half a NAND gate of a CMOS device (Liaw ¶0037, Xie ¶0005, 0051).
Further, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to duplicate the first back-side contact of Xie, in order to form a transistor, since mere duplication of the essential working parts of a device involves only routine skill in the art (see MPEP 2144.04 VI).
Xie in view of Liaw does not teach: a composition of the common drain feature of the first GAA nanosheet transistor and the second GAA nanosheet transistor is different than a composition of the source feature of the first GAA nanosheet transistor.
Block, in the same field of endeavor of semiconductor device manufacturing, teaches: adjusting a composition of a common source/drain feature (Block 640, ¶0181, 0300, raising a dopant concentration of a backside source/drain).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to adjust the composition of the source feature of the first GAA nanosheet transistor of Xie in view of Liaw, such that “a composition of the common drain feature of the first GAA nanosheet transistor and the second GAA nanosheet transistor is different than a composition of the source feature of the first GAA nanosheet transistor”, as taught by Block, in order to form asymmetric source and drain compositions, thereby reducing the contact resistance of a backside contact (Block ¶0163, 0174, 0181).
Regarding claim 17, Xie in view of Liaw and Block teaches: The semiconductor device as claimed in claim 16, wherein when the first GAA nanosheet transistor (Xie G2, 120-2, 122, 112, 114, 116) is an N-type transistor (Xie “NFET”, ¶0039, 0044, 0045), the additional implant comprises phosphorus, Arsenic, Ge, or a combination thereof (Xie ¶0078, “Ge-containing source gas … phosphorus (P) or arsenic (As) … for N-type FETs”).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Claims 9, 10, 12-14, and 25 allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 9, it is allowable primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combination with all other limitations:
the first contact feature is disposed above the tap via and extends through a second dielectric layer through which the plurality of front-side contacts also extend, or
the first contact feature is disposed below the tap via and disposed in the first dielectric layer. (Applicant fig 6B, 7A, ¶0087).
Xie et al (US 20230207553 A1, hereafter Xie) in view of Liaw (US 20200105761 A1) as applied to claim 9 in the previous office action dated 01/28/2026, teach some of the limitations of claim 9.
Gomes et al (US 20210134802 A1, hereafter Gomes) teaches: a power tap structure (Gomes 658, ¶0072, “power through electrically conductive vias extending in the z-direction”), comprising:
a tap via (Gomes 658, ¶0072, 0100, and/or BRI of “via”) extending through an isolation layer (Gomes 630 within 656, ¶0084, 0090, at least electrically isolating) over a first dielectric layer (Gomes 630 within 638, ¶0084, 0090, “dielectric material”).
Liebmann et al (US 20220181258 A1, hereafter Liebman) teaches: a power tap structure (Liebmann 110, ¶0053-0056), comprising:
a tap via (Liebmann 112, 113, ¶0053-0054) extending through a device layer (Liebmann fig 1); and
a first contact feature (Liebmann 111) interfacing with the tap via (Liebmann fig 1), wherein at least one of:
the first contact feature is disposed above the tap via (Liebmann fig 1).
Neither Xie, Liaw, Gomes, nor Liebmann, either alone or in combination, teaches: the first contact feature is disposed above the tap via and extends through a second dielectric layer through which the plurality of front-side contacts also extend, or the first contact feature is disposed below the tap via and disposed in the first dielectric layer; as required by claim 9.
Therefore, Xie in view of Liaw, Gomes, and Liebmann in combination disclose some of the features of the claimed invention, but there is no motivation/teaching and do not render obvious to combine and/or modify Xie, Liaw, Gomes, Liebmann, or any other prior arts of record so that all of limitations of claim 9 as a whole can be met.
Regarding claims 10, 12-14, and 25, the dependent claims are allowed for their dependency to claim 9.
Conclusion
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/NICHOLAS B. MICHAUD/
EXAMINER
Art Unit 2818
/Mounir S Amer/Primary Examiner, Art Unit 2818
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