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Last updated: April 16, 2026
Application No. 17/747,757

Memory Device Including Bottom Electrode Bridges and Method of Manufacture

Final Rejection §103
Filed
May 18, 2022
Examiner
CRAWFORD EASON, LATANYA N
Art Unit
2813
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Co., LTD.
OA Round
4 (Final)
78%
Grant Probability
Favorable
5-6
OA Rounds
2y 8m
To Grant
79%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allow Rate
719 granted / 917 resolved
+10.4% vs TC avg
Minimal +0% lift
Without
With
+0.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
42 currently pending
Career history
959
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
51.1%
+11.1% vs TC avg
§102
34.7%
-5.3% vs TC avg
§112
10.6%
-29.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 917 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 5, & 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kan (US Pub no. 2018/0061467 A1) in view of Sasaki (US Pub no. 2022/0190234 A1) Regarding claim 1, Kan et al discloses a memory comprising: a first electrode (M4) on a first via(V3)[0083-0084], wherein first via(V3) side surfaces for the first via (V3)are disposed laterally within first electrode(M4) side surfaces for the first electrode(M4) fig. 8; a second electrode(V3) on a second via(M4), wherein second via side surfaces for the second via(M4) are disposed laterally within second electrode(V3) side surfaces for the second electrode(V3); a spin-orbit torque (SOT) structure (840)physically and electrically coupled to the first electrode(M4) and the second electrode(M4) [0085] fig. 8, wherein the SOT structure (840)overlaps the first electrode(M4) and the second electrode(M4) fig. 8, and outer SOT(840) side surfaces for the SOT structure (840)are laterally disposed within a perimeter defined by the first electrode(M4) side surfaces for the first electrode(M4) and the second electrode side surfaces for the second electrode(M4); and a magnetic tunnel junction (MTJ) (830)on the SOT structure(840)[0085] fig. 8. Kan et al fails to teach wherein the first electrode is spaced apart from the second electrode along a first direction in a top-down view; wherein along a second direction, the first electrode extends laterally past edges of the SOT structure in the top-down view, wherein along the second direction, the second electrode extends laterally past edges of the SOT structure in the top-down view, and wherein the second direction is perpendicular to the first direction; wherein a width of a bottom surface of the SOT structure measured along the first direction is greater than a width of a top surface of the SOT structure measured along the first direction, and wherein the width of the top surface of the SOT structure is greater than the first distance However, Sasaki et al discloses wherein the first electrode (31)is spaced apart from the second electrode(32) along a first direction in a top-down view fig. 4[0058-0059]; wherein along a second direction, the first electrode(31) extends laterally past edges of the SOT structure(20) in the top-down view fig . 4, wherein along the second direction, the second electrode (32)extends laterally past edges of the SOT structure (20)in the top-down view fig. 4, and wherein the second direction is perpendicular to the first direction(fig. 3 /fig. 4); wherein a width of a bottom surface of the SOT structure(20) measured along the first direction is greater than a width of a top surface of the SOT structure (20)measured along the first direction, and wherein the width of the top surface of the SOT structure is greater than the first distance(fig. 3). . It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kan et al with the teachings of Sasaki to enhance spin efficiency. Regarding claim 5, Sasaki et al discloses wherein the SOT structure(20) has a rectangular shape in the top-down view, and wherein the MTJ (10)has a rounded shape in the top-down view(fig. 4). Regarding claim 6, Kan et al discloses wherein a first portion of a top surface of the first electrode(M4) is physically coupled to the SOT structure(840), and wherein a second portion of the top surface of the first electrode(M4) is free from contact with the SOT structure(840) fig. 8. Claim(s) 2-4,& 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kan (US Pub no. 2018/0061467 A1) in view of Sasaki (US Pub no. 2022/0190234 A1) as applied to claim 1 and further in view of Sato (US Pub no. 2020/0006631 A1). Regarding claim 2, Kan et al as modified by Sasaki et al discloses all the claim limitations of claim 1 but fails to teach wherein the SOT structure has a stepped structure. However, Sato et al discloses wherein the SOT structure (106)has a stepped structure[0072]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kan et al & Sasaki et al with the teachings of Sato et al to diminish the effect of spin diffusion current. Regarding claim 3, Sato et al discloses wherein the outer SOT side surfaces for the SOT structure(106) comprises first side surfaces having a rectangular shape in the top-down view, and wherein the SOT structure (106)comprises second side surfaces having a rounded shape in the top-down view[0072][0048][0051] fig. 1b /fig. 2(since a recess is formed in 106 as shown in fig. 2 it will partially have the same circular structure as the MTJ). Regarding claim 4, Sato et al discloses wherein the MTJ (104)and the SOT structure (106)have rounded shapes in the top-down view fig. 1b /fig. 2(since a recess is formed in 106 as shown in fig. 2 it will partially have the same circular structure as the MTJ). Regarding claim 9, Kan et al as modified by Sasaki et al discloses all the claim limitations of claim 1 but fails to teach wherein the SOT structure comprises a multi-layer stack comprising alternating layers of a heavy metal material and a first material different from the heavy metal material. However, Sato et al teaches wherein the SOT structure (114/106)comprises a multi-layer stack comprising alternating layers of a heavy metal material and a first material different from the heavy metal material[0049-0050]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kan et al & Sasaki et al with the teachings of Sato to provide high spin efficiency Regarding claim 10, Sato et al discloses wherein the heavy metal material comprises tungsten, platinum, or tantalum, and wherein the first material comprises tantalum[0049-0050] Claim(s) 7 & 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kan (US Pub no. 2018/0061467 A1) in view of Sasaki (US Pub no. 2022/0190234 A1) as applied to claim 1 and further in view of Martin (US Pub no. 2021/0295887 A1). Regarding claims 7, Kan et al as modified by Sasaki et al discloses all the claim limitations of claim 1 but fails to teach wherein the first electrode is separated from the second electrode by a first distance in the first direction, and wherein the MTJ has a first width in the first direction greater than the first distance. However, Martin et al discloses wherein the first electrode is separated from the second electrode by a first distance (Wg)in the first direction[0038], and wherein the MTJ(20) has a first width in the first direction greater than the first distance(fig. 3/ fig. 4. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kan et al & Sasaki et al with the teachings of Martin et al reduce the writing current. Regarding claim 8, Martin et al discloses the first distance (Wg) wherein the MTJ (20)has a first width(D30) in the second direction(y) [0038]but fails to teach the first distance greater than or equal to 20 nm and the MTJ first width less than or equal to 30 nm. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to achieve first distance greater than or equal to 20 nm and first width is less than or equal to 30 nm through routine experimentation to optimize the writing current since In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. /n re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990) Claim(s) 15 , 16 & 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US Pub no. 2021/0082998 A1) in view of Sasaki (US Pub no. 2022/0190234 A1) Regarding claim 15, Lee et al discloses A memory device comprising: a first dielectric layer (111) on a semiconductor substrate (100) [0028], the first dielectric layer (111)over a first via (120a)and a second via(120b ) [0029]; a first bottom electrode(191) in the first dielectric layer(111) [0031], the first bottom electrode(191) on the first via(120a) , wherein first via(120a) side surfaces for the first via (120a)are disposed laterally within first electrode (191)side surfaces for the first bottom electrode(191); a second bottom electrode(192) in the first dielectric layer(111) [0031], the second bottom via (192)(examiner interprets “the second bottom via” as the second bottom electrode) on the second via(120b) fig. 2, wherein second via (120a) side surfaces for the second via (120a) are disposed laterally within second electrode side surfaces for the second bottom electrode(192) ; a spin-orbit torque (SOT) structure(152) on the first bottom electrode(191) and the second bottom electrode(192) , wherein outer SOT side surfaces for the SOT structure(152) are laterally disposed within a perimeter defined by outer side surfaces for the first electrode side surfaces for the first bottom electrode(191) and the second electrode(192) side surfaces of the second bottom electrode(192b); and a magnetic tunnel junction (MTJ) on the SOT structure(150), wherein the MTJ(MTJ) overlaps the first bottom electrode (191)and the second bottom electrode(192) in a first direction perpendicular to a major surface of the semiconductor substrate(100) fig. 2/fig. 24. Lee et al fails to teach wherein the first bottom electrode is spaced apart from the second bottom electrode along a first direction in a top-down view; wherein along a second direction, the first bottom electrode extends laterally past edges of the SOT structure, wherein along the second direction, the second bottom electrode extends laterally past edges of the SOT structure, wherein the second direction is perpendicular to the first direction, and wherein the first direction and the second direction are parallel to a major surface of the semiconductor substrate, wherein a bottom surface of the SOT structure is wider than a top surface of the SOT structure along the first direction, and wherein the top surface of the SOT structure overlaps the first bottom electrode and the second bottom electrode in a cross-sectional view. However, Sasaki et al discloses wherein the first bottom electrode (31)is spaced apart from the second bottom electrode(32) along a first direction in a top-down view fig. 4; wherein along a second direction, the first bottom electrode (31)extends laterally past edges of the SOT structure(20) fig. 3/fig. 4, wherein along the second direction, the second bottom electrode extends laterally past edges of the SOT structure(20), wherein the second direction is perpendicular to the first direction(fig. 3/ fig. 4), and wherein the first direction and the second direction are parallel to a major surface of the semiconductor substrate(sub), wherein a bottom surface of the SOT structure(20) is wider than a top surface of the SOT structure(20) along the first direction fig. 4, and wherein the top surface of the SOT structure (20)overlaps the first bottom electrode (31)and the second bottom electrode(32) in a cross-sectional view(fig. 3). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Lee et al with the teachings of Sasaki et al to enhance spin efficiency. Regarding claim 16, Lee et al discloses wherein the first bottom electrode and the second bottom electrode(191/192) comprise platinum[0051]. Regarding claim 19, Lee et al discloses wherein the SOT structure(152) is physically and electrically coupled to the first bottom electrode(191) and the second bottom electrode(192) fig. 24. Claim(s) 17 & 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US Pub no. 2021/0082998 A1) in view of Sasaki (US Pub no. 2022/0190234 A1) as applied to claim 15 and further in view of Liu (US Pub no.2020/0075670 A1). Regarding claim 17, Lee et al as modified by Sasaki et al discloses all the claim limitations of claim 15 but fails to teach wherein the SOT structure comprises a multi-layer stack comprising alternating layers of a heavy metal material and a first material different from the heavy metal material, and wherein a ratio of a total thickness of the layers comprising the first material to a total thickness of the layers comprising the heavy metal material is in a range from 1:19 to 1:4. However, Liu et al discloses a multi-layer stack comprising alternating layers of a heavy metal material (230HM)and a first material (230MI)different from the heavy metal material, and a ratio of a total thickness of the layers comprising the first material to a total thickness of the layers comprising the heavy metal material is in a range[0030][0035][0062] but fails to teach from 1:19 to 1:4. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to adjust the ratio in a range from 1:19 to 1:4 through routine experimentation "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation .”In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Lee et al & Sasaki et al with the teachings of Liu et al to impact switching capability. Regarding claim 18, Liu et al discloses the SOT channel layer includes one or more magnetic insertion layers and one or more heavy metal layers stacked in an alternating manner [0014]but fails to teach comprises four layers of the heavy metal material and three layers of the first material. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Liu et al to include four layers of the heavy metal material and three layers of the first material, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art (St. Regis Paper Co. v. Bemis Co., 193 USPQ 8). Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Lee et al & Sasaki et al with the teachings of Liu et al to impact switching capability. Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US Pub no. 2021/0082998 A1) in view of Sasaki (US Pub no. 2022/0190234 A1) as applied to claim 15 and further in view of Martin (US Pub no. 2021/0295887 A1) Regarding claim 20, Lee et al as modified by Sasaki et al discloses all the claim limitations of claim 15 but fails to teach wherein the first bottom electrode is separated from the second bottom electrode by a first distance greater than 20 nm in the first direction, and wherein the MTJ has a first width in the second direction less than 30 nm. However, Martin et al teaches wherein the first bottom electrode (51)is separated from the second bottom electrode (51)by a first distance (Wg) in the first direction(x), and wherein the MTJ (20)has a first width(D30) in the second direction(y) [0038]but fails to teach the first distance greater than 20 nm and the MTJ first width less than 30 nm. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to achieve first distance greater than 20 nm and first width is less than or equal to 30 nm through routine experimentation to optimize the writing current since In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. /n re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990) Allowable Subject Matter Claims 11, 12, & 14 are allowed. The following is a statement of reasons for the indication of allowable subject matter: wherein a first lateral distance between the first upper sidewall and the second upper sidewall is less than a second lateral distance between the first lower sidewall and the second lower sidewall, and wherein the second etching process ends on the first bottom electrode bridge and the second bottom electrode bridge. Response to Arguments Applicant’s arguments with respect to claim(s) 1-12 & 14-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LATANYA N CRAWFORD EASON whose telephone number is (571)270-3208. The examiner can normally be reached Monday-Friday 8:30 AM-4:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LATANYA N CRAWFORD EASON/Primary Examiner, Art Unit 2813
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Prosecution Timeline

May 18, 2022
Application Filed
Sep 28, 2024
Non-Final Rejection — §103
Jan 31, 2025
Response Filed
Apr 28, 2025
Final Rejection — §103
Jul 02, 2025
Response after Non-Final Action
Jul 21, 2025
Request for Continued Examination
Jul 23, 2025
Response after Non-Final Action
Jul 24, 2025
Non-Final Rejection — §103
Nov 26, 2025
Response Filed
Feb 07, 2026
Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
78%
Grant Probability
79%
With Interview (+0.2%)
2y 8m
Median Time to Grant
High
PTA Risk
Based on 917 resolved cases by this examiner. Grant probability derived from career allow rate.

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