DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on February 23, 2026. Claims 1, 14-15 and 20 have been amended. New claims 21-24 have been added. Claims 2, 16-17 and 19 have been canceled. Claims 3-13 have been withdrawn. Currently, claims 1, 14-15, 18 and 20-24 are pending.
Applicant’s amendment to claim 20 successfully overcomes the 112(b) rejection of claim 20 set forth in the previous Office Action.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 14 have been considered but are moot as applied to the newly added claim limitations because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Regarding claim 14, the Applicant argues that, “Zhao is not directed to a method of preventing aluminum diffusion, as alleged by the Office. Rather, Zhao is directed to a method that includes forming a diffusion layer that allows a material of the diffusion layer to diffuse into a first work function layer and a cap layer to form a doped work function layer and a doped cap layer, respectively. Zhao at Abstract.
A person of ordinary skill in the art seeking to prevent aluminum diffusion (as in the present application and claimed invention) would not seek to form a diffusion layer that allows a material of the diffusion layer to diffuse into a first work function layer and a cap layer to form a doped work function layer and a doped cap layer, respectively, as in Zhao. In fact, a diffusion layer that would allow diffusion, as in Zhao, is precisely the type of layer that the present application and claimed invention seeks to avoid. This disclosure in Zhao cannot be merely ignored.
Accordingly, citing to Zhao, solely for allegedly teaching "exposing the substrate surface to a thermal treatment at a temperature of at least 700 °C," is impermissible picking and choosing among isolated disclosures in the prior art only so much of it as will support a given position, to the exclusion of other parts necessary to the full appreciation of what such reference fairly suggests to one of ordinary skill in the art. Since Zhao has nothing to do with the claimed invention, citing to Zhao solely for allegedly teaching "exposing the substrate surface to a thermal treatment at a temperature of at least 700 °C," is impermissible according to section 103 and federal case law.”
The Examiner respectfully disagrees with the Applicant’s assertion.
The claimed feature of, “exposing the substrate surface to a thermal treatment at a temperature of at least 700 °C to drive atoms of the interfacial silicon oxide layer into the high- K metal oxide layer;” is inherent in the prior art structure described by Zhao. Specifically, this inherency argument applies to openings 211 and 212, which include a barrier layer. The different structure of other openings in Zhao, such as the fifth and sixth openings 215 and 216 which lack a barrier layer 206, where materials from the diffusion layer 207 diffuse into the cap layer 203 to form a doped capped layer 231 is not relevant to this specific analysis and is therefore explicitly excluded form consideration.
Zhao discloses a gate stack structure substantially identical to that of the Appellant and the annealing process necessarily produces the same outcome.
Zhao teaches a gate stack within openings 211 and 212 comprises
1) A silicon oxide interlayer 204, which is the functional equivalent of the Appellant’s interfacial silicon oxide layer [0052, 0053, Figures 1-5].
2) A high-k gate dielectric layer 202 and a capping layer 203, which correspond directly to the Appellant’s high-k metal oxide layer [0055, 0056, Figures 1-5].
3) A barrier layer 206, comprised of TaN, which is a material explicitly listed by the Appellant in paragraph [0055] for their own barrier layer [0063, 0065, Figures 1-5].
4) An aluminum-containing work function layer, referenced as first work function layer 221 and diffusion layer 207, which is the equivalent of the Appellant 's aluminum-containing layer.
Zhao’s process includes a thermal treatment to cause migration of aluminum from diffusion layer 207 to the first work function layer 221, forming an aluminum doped layer 230 within openings 211 and 212.
While Zhao is silent regarding aluminum migrating specifically into the barrier layer 206, this is consistent with the understanding that a barrier layer, especially one composed of TaN, is intended to block such diffusion. Zhao’s disclosure of aluminum migration into the capping layer in openings 215 and 216 where no barrier layer 206 is present serves as further evidence.
Since Zhao’s structure in these specific openings is substantially identical to the Applicant’s, the annealing step with inherently cause the same physical phenomenon in both structures. Specifically, atoms from the interfacial silicon oxide layer will be driven into high-k metal oxide layer. This is not a newly discovered feature but an inevitable result of applying the disclosed thermal treatment to the disclosed structure in openings 211 and 212.
Regarding product and apparatus claims, when the structure recited in the reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. The Courts have held that it is well settled that where there is a reason to believe that a functional characteristic would be inherent in the prior art, the burden of proof then shifts to the applicant to provide objective evidence to the contrary. In Schreiber, 128 F.3d 1473, 1478, 44 USPQ2d 1429, 1432 (Fed.Cir.1997) See MPEP 2112.01.
Regarding claim 18, the Applicant argues that, “Since Besser has nothing to do with the claimed invention, citing to Besser solely for allegedly teaching "in situ deposited titanium nitride (TiN)" as a capping layer is impermissible according to section 103 and federal case law…. Since Bao has nothing to do with the claimed invention, citing to Bao solely for allegedly teaching "silicon (Si)" as a capping layer is impermissible according to section 103 and federal case law…… The Office has impermissibly picked and chosen the materials from Bao and Besser, used the claimed invention as a template, and attempted to fit the materials into the claimed invention. The materials in Bao and Besser have absolutely nothing to do with the claimed invention.”
The Examiner respectfully disagrees with the Applicant’s assertion regarding the combination of references. The Applicant’s arguments that the Office has “impermissibly picked and chosen the materials from Bao and Besser” is a misunderstanding of the legal standard for obviousness under U.S.C. 103.
Choi teaches a TiN capping layer formed by ALD or CVD process which maybe in-situ methods of deposition. Besser discloses a known, conventional method for depositing TiN that is, in-situ for the predictable purpose of preventing oxidation and moisture absorption. Bao establishes that the use of composite capping layer comprising TiN and silicon is a known combination. The claimed invention is therefore a predictable outcome of known elements and techniques from the prior art.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2015/0126023 A1; hereafter Choi) in view of Cabral, JR. et al. (US 2012/0038056 A1; hereafter Cabral, JK.).
Regarding claim 1, Choi teaches a method of preventing aluminum diffusion in a metal gate stack (see e.g., Figures 1A-1M), the method comprising:
forming a barrier layer (see e.g., second metal layer 32 made of TiN, TaN, TiSiN, TaSiN, WN, or WSiN, Para [0044], Figure 1L) directly on an underlying metal layer (see e.g., the second metal layer 32 is formed directly on the lanthanide-containing high-k insulating layer 22A for example, transistor 10N1, on the high-k insulation layer 22 for example, transistor 10N2, and on the first metal layer 28A for example, transistors 10P2 and 10P1, Para [0044], Figure 1L), the barrier layer having a thickness in the range of 5 A to 30 A (see e.g., the second metal layer 32 has a thickness of about 0.5-2 nm., Para [0044]); and
depositing an aluminum-containing layer directly on the barrier layer (see e.g., a third metal layer 34 formed directly on the second metal layer 32. The third metal layer 34 is comprised of a metal that will function as the work function adjusting metal for the NMOS devices. In one example, the third metal layer 34 may be a layer of titanium aluminum carbon (TiAlC), TiAl, TiAlN, TaAl, TaAlC, HfAlC, HfAl, WSi, TiSi, HfSi or any other N-type work function metal, Para [0045], Figure 1M),
wherein substantially no aluminum from the aluminum-containing layer migrates through the barrier layer into the underlying metal layer (see e.g., the second metal layer 32 is comprised of a metal that will serve as a barrier layer to prevent diffusion of the N-work function metal into the underlying gate insulation layers. The barrier layer 32 is typically needed when the N-work function metal contains aluminum that is, the barrier layer prevents the diffusion of aluminum from the aluminum containing layer to the underlying high-k gate insulation layer 22, Paras [0044] - [0045]).
Choi does not explicitly teach
“barrier layer comprising titanium tantalum nitride (TiTaN)”,
However, Choi’s TaN barrier layer is functionally equivalent to TiTaN as taught by Cabral, JR. (see e.g., the barrier metal layer 20 is composed of a material that serves as a diffusion barrier between the device layer 10 and the interconnect metal layer 25. The barrier metal layer 20 includes titanium tantalum nitride (TiTaN), Para [0046], Figure 1)
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Cabral, JR.’s teachings of barrier layer comprising titanium tantalum nitride (TiTaN) in the method of Choi in order to use any of the alternatively usable materials and arrive at the claimed invention.
Claims 14, 15, 20 and 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2015/0126023 A1; hereafter Choi) in view of Cabral, JR. et al. (US 2012/0038056 A1; hereafter Cabral, JK.) and Zhao (US 2015/0214112 A1).
Regarding claim 14, Choi teaches a method of forming a metal gate stack (see e.g., Figures 1A-1R), the method comprising:
depositing an interfacial silicon oxide layer on a substrate surface (see e.g., a thin native oxide layer formed on the substrate 12, Para [0034], Figure 2);
forming a high-K metal oxide layer on the interfacial silicon oxide layer (see e.g., high-k gate insulation layer 22, for transistor 10N2, and lanthanide containing high-k insulating layer 22A, for transistor 10N1, deposited on the native oxide layer, Para [0035], Figure 1C);
depositing a barrier layer directly on the high-K metal oxide layer (see e.g., the second metal layer 32 may be a layer of TiN, TaN, TiSiN, TaSiN, WN, or WSiN having a thickness of about 0.5-2 nm. The second metal layer 32 is formed directly on the lanthanide-containing high-k insulating layer 22A for transistor 10N1 and on the high-k insulation layer 22 for transistor 10N2, Para [0044], Figure 1L);
depositing an aluminum-containing layer directly on the barrier layer (see e.g., a third metal layer 34 formed directly on the second metal layer 32. The third metal layer 34 is comprised of a metal that will function as the work function adjusting metal for the NMOS devices. In one example, the third metal layer 34 may be a layer of titanium aluminum carbon (TiAlC), TiAl, TiAlN, TaAl, TaAlC, HfAlC, HfAl, WSi, TiSi, HfSi or any other N-type work function metal, Para [0045], Figure 1M);
and substantially no aluminum from the aluminum-containing layer migrates through the barrier layer into the high-k metal oxide layer (see e.g., the second metal layer 32 is comprised of a metal that will serve as a barrier layer to prevent diffusion of the N-work function metal into the underlying gate insulation layers. The barrier layer 32 is typically needed when the N-work function metal contains aluminum that is, the barrier layer prevents the diffusion of aluminum from the aluminum containing layer to the underlying high-k gate insulation layer 22, Paras [0044] - [0045], Figure 1L)
depositing at least one capping layer on the aluminum-containing layer (see e.g., a fourth metal layer 36 formed on the third metal layer 34. The fourth metal layer 36 may be a layer of TiN, TaN etc., Para [0046], Figure 1N);
removing the at least one capping layer and the barrier layer (see e.g., portion of the second metal layer 32 and fourth metal layer 36 are removed by a timed etching process, Para [0050], Figure 1R).
Choi does not explicitly teach
“wherein the barrier layer comprising titanium tantalum nitride (TiTaN)”
However, Choi’s TaN barrier layer is functionally equivalent to TiTaN as taught by Cabral, JR. (see e.g., the barrier metal layer 20 is composed of a material that serves as a diffusion barrier between the device layer 10 and the interconnect metal layer 25. The barrier metal layer 20 includes titanium tantalum nitride (TiTaN), Para [0046], Figure 1)
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Cabral, JR.’s teachings of barrier layer comprising titanium tantalum nitride (TiTaN) in the method of Choi in order to use any of the alternatively usable materials and arrive at the claimed invention.
Choi does not explicitly teach
“exposing the substrate surface to a thermal treatment at a temperature of at least 700 °C to drive atoms of the interfacial silicon oxide layer into the high- K metal oxide layer”;
In a similar field of endeavor Zhao teaches exposing the substrate surface to a thermal treatment at a temperature of at least 700 °C (see e.g., an annealing process is performed at a temperature range from 500.degree.C to about 800.degree.C once the bonding layer 204, gate dielectric layer 202, barrier layer 206, first metal work function layer 221 and diffusion layer 207 are formed, Para [0076], Figure 4).
Zhao’s process includes a thermal treatment to cause migration of aluminum from diffusion layer 207 to the first work function layer 221, forming an aluminum doped layer 230 within openings 211 and 212.
While Zhao is silent regarding aluminum migrating specifically into the barrier layer 206, this is consistent with the understanding that a barrier layer, especially one composed of TaN, is intended to block such diffusion. Zhao’s disclosure of aluminum migration into the capping layer in openings 215 and 216 where no barrier layer 206 is present serves as further evidence.
Since Zhao’s structure in these specific openings is substantially identical to the Applicant’s, the annealing step with inherently cause the same physical phenomenon in both structures. Specifically, atoms from the interfacial silicon oxide layer will be driven into high-k metal oxide layer. This is not a newly discovered feature but an inevitable result of applying the disclosed thermal treatment to the disclosed structure in openings 211 and 212.
Regarding product and apparatus claims, when the structure recited in the reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. The Courts have held that it is well settled that where there is a reason to believe that a functional characteristic would be inherent in the prior art, the burden of proof then shifts to the applicant to provide objective evidence to the contrary. In Schreiber, 128 F.3d 1473, 1478, 44 USPQ2d 1429, 1432 (Fed.Cir.1997) See MPEP 2112.01.
Therefore, it would be obvious to one skilled in the art at the time the invention was effectively filed to implement Zhao’s teachings of exposing the substrate surface to a thermal treatment at a temperature of at least 700 °C to drive atoms of the interfacial silicon oxide layer into the high- K metal oxide layer in the method of Choi in order to activate the atoms.
Regarding claim 15, Choi, as modified by Cabral, JR. and Zhao, teaches the limitations of claim 14 as mentioned above. Choi further teaches
wherein the barrier layer has a thickness in the range of 5A to 30A (see e.g., the second metal layer 32 has a thickness of about 0.5-2 nm., Para [0044]).
Regarding claim 20, Choi, as modified by Cabral, JR. and Zhao, teaches the limitations of claim 14 as mentioned above. Choi further teaches
wherein the barrier layer is deposited by atomic layer deposition (ALD) or chemical vapor deposition (CVD) (see e.g., the second metal layer 32 maybe formed by ALD process, Para [0044]).
Regarding claim 23, Choi, as modified by Cabral, JR. and Zhao, teaches the limitations of claim 15 as mentioned above. Choi further teaches
wherein the thickness of the barrier layer is in the range of 5 A to 20 A (see e.g., the second metal layer 32 has a thickness of about 0.5-2 nm., Para [0044]).
Regarding claim 24, Choi, as modified by Cabral, JR. and Zhao, teaches the limitations of claim 14 as mentioned above. Choi further teaches
wherein the high-K metal oxide layer comprises hafnium oxide (HfO2) (see e.g., the high-k gate insulation layer 22 includes hafnium oxide, Para [0035], Figure 1C).
Claims 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 2015/0126023 A1; hereafter Choi) in view of Cabral, JR. et al. (US 2012/0038056 A1; hereafter Cabral, JK.) and Zhao (US 2015/0214112 A1) and further in view of Marcadal et al. (US 2008/0032041 A1; hereafter Marcadal).
Regarding claim 21, Choi, as modified by Cabral, JR. and Zhao, teaches the limitations of claim 14 as mentioned above. Choi does not explicitly teach
“wherein the barrier layer is deposited at a temperature in the range of 350 °C to 500 °C”.
Choi discloses a TaN film functionally equivalent to the Tantalum-based barrier layer described by Cabral, JR.’s.
In a similar field of endeavor Marcadal provides a generic teaching of forming a tantalum-containing barrier layer 20 using Atomic Layer Deposition (ALD). Marcadal teaches such layers are ideally formed within a temperature of about 200.degree. C. to about 500.degree. C., preferably from about 250.degree. C. to about 400.degree. C., and more preferably from about 330.degree. C. to about 360.degree. C. (see g., Para [0025]).
Therefore, it would have been obvious to one skilled int he art at the time the invention was effectively filed to implement Marcadal’s teachings of depositing a barrier layer at a temperature range of 350 °C to 500 °C in the method of Choi in order to operate within a known optimal ALD temperature window for tantalum-based films.
Regarding claim 22, Choi, as modified by Cabral, JR. and Zhao, teaches the limitations of claim 14 as mentioned above. Choi does not explicitly teach
“wherein the barrier layer is deposited at a pressure in the range of 2 Torr to 50 Torr”.
Choi discloses a TaN film functionally equivalent to the Tantalum-based barrier layer described by Cabral, JR.’s.
In a similar field of endeavor Marcadal provides a generic teaching of forming a tantalum-containing barrier layer 20 using Atomic Layer Deposition (ALD). Marcadal teaches that such layers are ideally formed within a pressurized environment ranging from about 1 mTorr to about 100 Torr, preferably from about 1 Torr to about 10 Torr, and more preferably from about 2 Torr to about 5 Torr (see g., Para [0025]).
Therefore, it would have been obvious to one skilled int he art at the time the invention was effectively filed to implement Marcadal’s teachings of depositing a barrier layer at a pressure in the range of 2 Torr to 50 Torr in the method of Choi to ensure the process operates within the established optimal ALD window for tantalum-based film.
Claims 18 is rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Cabral, JR. et al. (US 2012/0038056 A1; hereafter Cabral, JK.), Zhao (US 2015/0214112 A1) and further in view of Bao et al. (US 2023/0075740 A1; hereafter Bao) and Besser et al. (US 2013/0049200 A1; hereafter Besser).
Regarding claim 18, Choi, as modified by Cabral, JR. and Zhao, teaches the limitations of claim 14 as mentioned above. Choi further teaches
wherein the at least one capping layer includes a first capping layer comprised of titanium nitride (TiN) (see e.g., fourth metal layer 36 may be a layer of TiN, Para [0046]).
Choi does not explicitly teach
“in-situ deposited titanium nitride (TiN)”.
In a similar field of endeavor Besser teaches
in-situ deposited titanium nitride (TiN) (see e.g., capping layer TiN is formed by depositing in-situ to prevent oxidation and water absorption of underlying metal layer, Para [0031]).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed implement Besser’s teachings of in-situ deposited titanium nitride (TiN) in the method of Choi in order to prevent oxidation and water absorption of underlying layers.
Choi does not explicitly teach
“a second capping layer comprised of silicon”.
In a similar field of endeavor Bao teaches
a second capping layer comprised of silicon (see e.g., the annealing stack 235 includes a layer of amorphous silicon over a cap film of TiN deposited on the high-k dielectric layer (HK2) 150, Para [0047]).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Bao’s teachings of a second capping layer comprised of silicon in the method of Choi in order to form a stacked capped layer for annealing purposes.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/FAKEHA SEHAR/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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