DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/19/2025 has been entered.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2011/0304042 A1, newly cited), and further in view of Chou et al. (US 2007/0205520 A1, of record).
Re Claim 13, Cheng teaches a semiconductor structure comprising a first semiconductor die and an interconnect-containing structure (Fig. 1 and Fig. 10B), wherein the first semiconductor die comprises:
first metal interconnect structure located within first interconnect-level dielectric material layer (30a+30b+12, Fig. 1, “30a” and “30b” are bottom two layers of composite passivation layer 30, where 30 is made of multiple dielectric layers, para [0013], and are marked in annotated Fig. 1 below, while layer 12 is an interconnect structure comprising metal lines, vias and inter-layer dielectric, para [0012]);
first bonding pad (28, Fig. 1, para [0013]) located on a topmost first interconnect-level dielectric material layer (top surface of layer “30b”, see annotated Fig. 1 below) and electrically connected to a respective one of the first metal interconnect structures (28 is electrically connected to the device 14 via the interconnect structure 12, para [0013]), wherein at least one of the first bonding pad (28) comprises a pad plate portion (marked “pad plate portion of 28”) having a bottom surface in direct contact with a horizontal surface segment of a top surface of the topmost interconnect-level dielectric layer (top surface of layer “30b”, see annotated Fig. 1 below) within a first horizontal plane (top surface of layer “30b”) and further comprises a via portion (marked “via portion of 28”) that vertically extends from the first horizontal plane (top surface of layer “30b”) downward through the topmost interconnect-level dielectric layer (layer “30b”) and contacts a respective sidewall of the topmost interconnect-level dielectric layer (layer “30b”, see Fig. 1) and contacts a top surface of the respective one of the metal interconnect structures (12, see Fig. 1);
a dielectric passivation layer (marked “30c” in annotated Fig. 1 below which is part of the composite passivation layer 30, where 30 is made of multiple dielectric layers, para [0013]) located directly on the topmost first interconnect-level dielectric material layer (layer “30b”) and the first bonding pad (28), wherein the dielectric passivation layer (layer “30c”) comprises a dielectric passivation material which is selected from silicon nitride and silicon carbide nitride (dielectric layers 30 can be made of silicon nitride, para [0013]), conformally covers, and directly contacts, all sidewall surfaces of the first bonding pad (28, see Fig. 1), peripheral surface segments of top surfaces of the first bonding pad (28, see Fig. 1), and the top surface of the topmost interconnect-level dielectric layer (layer “30b”, see Fig. 1) in a vertical cross-sectional view (see Fig. 1), and has a uniform material composition throughout (see Fig. 1); and
first metal bump structure (32+34+36, Fig. 1, paras [0014] – [0015]) extending through the dielectric passivation layer (layer “30c”) and located on the first bonding pad (28), wherein:
each of the first metal bump structure (32+34+36) comprises a contoured bottom surface (marked “contoured bottom surface” in annotated Fig. 1 below) including a bottommost surface segment (bottommost surface of 32+34+36) in contact with a top surface of the at least one of the first bonding pad (top surface of 28), and an annular surface segment (marked “annular surface” in annotated Fig. 1 below) that overlies the dielectric passivation layer (layer “30c”) and having an inner periphery (marked “IN” in annotated Fig. 1 below) that is laterally offset inward from an outer periphery (marked “OUT” in annotated Fig. 1 below) by a lateral offset distance (marked “LOD1” and “LOD2” in annotated Fig. 1 below);
the annular surface segment (marked “annular surface”) is located above, and is vertically spaced from, a second horizontal plane including topmost surface segments of the dielectric passivation layer (topmost surface of layer “30c”, see Fig. 1) and is in direct contact with a dielectric surface (marked “30d” in annotated Fig. 1 below which is part of the composite passivation layer 30, which is made of multiple dielectric layers, para [0013]);
the interconnect-containing structure (Fig. 10B) comprises second metal bump structure (202+204, Fig. 10B, para [0023]) and is selected from a second semiconductor die, an interposer, or a packaging substrate (200 can be a package substrate, Fig. 10B, para [0023]); and
the first metal bump structures (32+34+36) are bonded (see Fig. 10B) to the second metal bump structures (202+204) through solder material portions (206, Fig. 10B, para [0023]).
Lin does not explicitly state that the lateral offset distance (LOD1 + LOD2) is at least 8 % of a width of a respective underlying one of the bonding pad (28). However, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to deduce from annotated Fig. 1 below, that the lateral offset distance (LOD1 + LOD2) is at least 10% of the width of 28 and is within the metes and bounds of the claimed range (see annotated Fig. 1 below).
It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the width of the lateral offset distance and arrive at the claimed range. With respect to the limitations of claimed range, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the width of the lateral offset distance would have been obvious to one of ordinary skill in the art.
Additionally, Lin does not disclose a plurality of a plurality of bonding pads and corresponding plurality of metal bump structures. One of ordinary skill in the semiconductor art would also realize that there can be several bonding pads with corresponding metal bump structures to not only provide electrical connection to other dies, external circuits or PCBs (printed circuit boards) but the plurality of bonding pads and metal bump structures also provide mechanical and structural support while stacking multiple dies. For example, Chou discloses a plurality of bonding pads (16a, Fig. 2G, para [0048]) and corresponding plurality of metal bump structures (26, Fig. 2G, para [0054]), to perform the above said functions. Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the semiconductor device of Lin to have a plurality of bonding pads and corresponding plurality of metal bump structures, as disclosed by Chou, for the reasons above.
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Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2011/0304042 A1, newly cited), and Chou et al. (US 2007/0205520 A1, of record), and further in view of Yang et al. (US 2012/0018877 A1, of record).
Re Claim 14, Lin modified by Chou teaches the semiconductor structure of Claim 13, further comprising a capping dielectric material layer (marked “30d” in annotated Fig. 1 below which is part of the composite passivation layer 30, where 30 is made of multiple dielectric layers, para [0013], Lin) contacting the dielectric passivation layer (layer “30c”, see Fig. 1, Lin) and the contoured bottom surfaces of the first metal bump structures (“contour bottom surface” of 32+34+36, Lin), wherein each of the first metal bump structures (32+34+36, Lin) comprises an additional tapered surface segment (tapered surface segment of 32+34, see Fig. 1, Lin) in contact with a tapered sidewall of a respective opening through the capping dielectric material layer (tapered sidewall of “layer 30d”, Lin).
Lin does not disclose an underfill material portion in Fig. 10B between the device 100 and the package substrate 200, and hence does not teach that an underfill material portion contacts the capping dielectric material layer.
However, in a related art, Yang teaches an interconnection between two package substrates 10 and 50 (Fig. 8A), where an underfill layer 47 is disposed between the substrates, which protects the interconnecting components from external damage and also provide mechanical support.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to use the teachings as disclosed Yang and dispose an underfill between the device 100 and the package substrate 200 of Lin, as the underfill will protect the interconnecting components from external damage and will also provide mechanical support. The underfill will be in direct contact with the capping layer (layer “30d”) in Fig. 10B of Lin.
Allowable Subject Matter
Claims 1-5, 7-8, 10-12, 21-24, 26 and 28 are allowed.
Claim 27 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowable subject matter:
Claim 1 is allowable for at least the following reasons. The limitation, “A semiconductor structure comprising a semiconductor die, wherein the semiconductor die comprises: metal interconnect structures located within interconnect-level dielectric material layers; bonding pads located on a topmost interconnect-level dielectric material layer and electrically connected to a respective one of the metal interconnect structures, wherein at least one of the bonding pads comprises a pad plate portion having a bottom surface in direct contact with a horizontal surface segment of a top surface of the topmost interconnect-level dielectric layer within a first horizontal plane; a dielectric passivation layer located directly on the top surface of the topmost interconnect-level dielectric material layer, wherein the dielectric passivation layer comprises a dielectric passivation material which is selected from silicon nitride and silicon carbide nitride, conformally covers, and directly contacts, all sidewall surfaces of the bonding pads, peripheral surface segments of top surfaces of the bonding pads, and the top surface of the topmost interconnect-level dielectric layer in a vertical cross-sectional view, and has a uniform material composition throughout; and metal bump structures extending through the dielectric passivation layer and located on the bonding pads, wherein each of the metal bump structures comprises a contoured bottom surface including a bottommost surface segment in contact with a top surface of the at least one of the bonding pads, a tapered surface segment in contact with a tapered sidewall of a respective-opening through the dielectric passivation layer, and an annular surface segment that overlies the dielectric passivation layer and having an inner periphery that is laterally offset inward from an outer periphery by a lateral offset distance that is at least 8 % of a width of an underlying one of the bonding pads, wherein the annular surface segment is located above, and is vertically spaced from, a second horizontal plane including topmost surface segments of the dielectric passivation layer and is in direct contact with a dielectric surface,” is taught by Minda et al. (US 2005/0258539 A1), and further in view of Chou et al. (US 2007/0205520 A1) and Deng et al. (US 2016/0300807 A1), as explained in the Final Office Action mailed 6/10/2025. The newly added limitation, which “further comprises a via portion that vertically extends from the first horizontal plane downward through the topmost interconnect-level dielectric layer and contacts a sidewall of the topmost interconnect-level dielectric layer and contacts a top surface of the one of the metal interconnect structures” is also taught separately by Lin et al. (US 2011/0304042 A1, newly cited). However, it would not have been obvious to a person of ordinary skill in the art to combine the above teachings to reach the combined limitation recited in claim 1. Claims 2-5, 7-8, 10-12, 21-24 and 26 depend from claim 1 and is allowable for at least these reasons.
Claim 21 is allowable for at least the following reasons. The limitation, “A semiconductor structure comprising a semiconductor die, wherein the semiconductor die comprises: metal interconnect structures located within interconnect-level dielectric material layers; bonding pads located on a topmost interconnect-level dielectric material layer and electrically connected to a respective one of the metal interconnect structures, wherein at least one of the bonding pads comprises a pad plate portion having a respective bottom surface in direct contact with a horizontal surface segment of a top surface of the topmost interconnect-level dielectric layer within a first horizontal plane; a dielectric passivation layer located on the topmost interconnect-level dielectric material layer, wherein the dielectric passivation layer comprises a dielectric passivation material which is selected from silicon nitride and silicon carbide nitride, conformally covers, and directly contacts, all sidewall surfaces of the bonding pads, peripheral surface segments of top surfaces of the bonding pads, and the top surface of the topmost interconnect-level dielectric layer in a vertical cross-sectional view, and has a uniform material composition throughout; a capping dielectric material layer overlying the dielectric passivation layer; and metal bump structures extending through the dielectric passivation layer and the capping dielectric material layer and located on the bonding pads, wherein each of the metal bump structures comprises a contoured bottom surface including a bottommost surface segment in contact with a top surface of a respective one of the bonding pads, a tapered surface segment in contact with a tapered sidewall of a respective opening through the dielectric passivation layer, and a first annular surface segment that contacts a second annular surface segment of the capping dielectric material layer,” is taught by Minda et al. (US 2005/0258539 A1), and further in view of Chou et al. (US 2007/0205520 A1) and Deng et al. (US 2016/0300807 A1), as explained in the Final Office Action mailed 6/10/2025. The newly added limitation, which “further comprises a via portion that vertically extends from the first horizontal plane downward through the topmost interconnect-level dielectric layer and contacts a respective sidewall of the topmost interconnect-level dielectric layer and contacts a top surface of the respective one of the metal interconnect structures” is also taught separately by Lin et al. (US 2011/0304042 A1, newly cited). However, it would not have been obvious to a person of ordinary skill in the art to combine the above teachings to reach the combined limitation recited in claim 21. Claims 22-24 and 28 depend from claim 21 and is allowable for at least these reasons
Claim 27 is allowable for at least the reasons of, “wherein each of the metal bump structures comprises an additional annular surface segment located within the second horizontal plane and in contact with a respective annular surface segment of a top surface of a capping segment of the dielectric passivation layer that overlies a respective one of the bonding pads”. This limitation is neither anticipated nor made obvious by the prior art of record.
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Conclusion
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898