DETAILED ACTION
This action is responsive to the amendment and request for continued examination received on 12/19/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/19/2025 has been entered.
Claim Interpretation
Applicant has utilized the phrase “electrically Isolated” in claims 1, 9, and 21 to describe the relationship between the “(first) contact” and the “second S/D”. Applicant also elected Figure 10A (species B) for examination in the response to restriction received on 02/10/2025. [0063] of the specification states that “the transistor 110A and the transistor 120A share the conductive segment 210b as a shared S/D. In some embodiments, the isolation layer 920b covers the conductive segment 210b (or the shared S/D), and the conductive segment 210b (or the shared S/D) is electrically isolated from an external connector” and [0060] states that “the contact 320A is electrically connected to the conductive segment (or the S/D) 210c of the transistor 120A through the conductive via 712A”.
Based on these lines and Figure 10B, it appears that there is an electrical connection between the contact (#320A) and at least the right S/D of #120A (#210c). Furthermore, it is clear that #210b/#210c represent the opposing source and drain of the transistor #120A. For this reason, it is interpreted that there is an electrical connection between the contact (#320A) and the S/D (#210b) through the transistor (#120A) even though the contact is electrically isolated from #210b by the isolation layer (#920b). Therefore, it is interpreted by the examiner, based on the disclosure, that two elements may be “electrically isolated” if there is no direct electrical contact between them, even if an alternative indirect electrical connection is made through another component.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3-7, 9-15, and 28 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 10192819 B1; Chanemougame et al.; 01/2019; (“Chanemougame”).
Regarding Claim 1. Chanemougame discloses A semiconductor device (Figures 1A-1E), comprising:
a first transistor (#120, Figure 1A, FET) comprising a first source/drain (S/D) (#122a, Figure 1A, source/drain region), a second S/D (#122b, Figure 1A, source/drain region), and a first gate (#151(u), Figure 1A, upper shared gate) between the first S/D and the second S/D (Figure 1A, #151(u) is between #122a and #122b);
a second transistor (#140, Figure 1A, FET);
a third transistor (#110, Figure 1A, FET), wherein the first transistor and the second transistor are stacked over the third transistor (Figure 1A, #120 and #140 are stacked over #110);
a first contact (#163 + #193, Figure 1C, embedded contact and insulated contact) covering the second S/D of the first transistor (Figure 1C, #163 + #193 at least partially covers a sidewall of #122b), wherein the first contact is electrically connected to the second transistor (Figures 1C, 1D, and 1E, #163 is electrically connected to #142b of #140 through conductive trace #183) and electrically isolated from the second S/D (Figure 1C, #163 + #193 is electrically isolated from #122b by dielectric sidewall spacer #195); and
an isolation layer (#195 + #105 + #104, Figure 1C, dielectric sidewall spacer and thin dielectric layer and thin conformal dielectric layer) entirely covering a circumferential surface of the second S/D of the first transistor (Figure 1C, #195, #104, and #105 in combination cover an entire circumferential surface of #122b) and electrically isolating the first contact from the second S/D (Figure 1C, #195, #104, and #105 electrically isolate #163 and #193 from #122b),
wherein the second S/D (#122b) is a shared S/D between the first transistor (#120) and the second transistor (#140) (column 7, lines 15-18, “a shared second source/drain region 122b/142a extends between the second channel region(s) 121 of the second FET 120 and second channel region(s) 141 of the second FET 140”, i.e. #122b is a shared S/D between #120 and #140).
Regarding Claim 3. Chanemougame discloses The semiconductor device according to Claim 1, wherein the third transistor (#110, Figure 1A, FET) comprises a third S/D (#112b, Figure 1A, source/drain region) stacked directly under the second S/D (Figure 1A, #112b is stacked directly under #122b), and the first contact electrically connects the third S/D of the third transistor to a fourth S/D of the second transistor (Figures 1C, 1D, and 1E, #163 + #193 electrically connects #112b of #110 to #142b of #140 through #183).
Regarding Claim 4. Chanemougame discloses The semiconductor device according to Claim 3, wherein the first contact directly contacts a portion of the third S/D of the third transistor (Figure 1C, #163 + #193 directly contacts a portion of #112b of #110).
Regarding Claim 5. Chanemougame discloses The semiconductor device according to Claim 1, wherein the first contact directly contacts a circumferential surface of the isolation layer (Figure 1C, #193 directly contacts a circumferential surface of #195).
Regarding Claim 6. Chanemougame discloses The semiconductor device according to Claim 1, wherein the first transistor and the second transistor have the same conductivity type (column 6, lines 18-20, “The second FET 120, 140 can be a second-type FET that is different from the first-type conductivity (e.g., an N-type FET)”, i.e. they are both n-type), and the first transistor and the third transistor have opposite conductive types (column 5, lines 54-55, “The first FET 110, 130 can be a first-type FET (e.g., a P-type FET)”, i.e. #120 is n-type while #110 is p-type).
Regarding Claim 7. Chanemougame discloses The semiconductor device according to Claim 1, wherein the second transistor comprises a second gate (#156(u), Figure 1A, upper shared gate of #140) electrically connected to the first contact (Figures 1A, 1C, and 1D, #163 and #193 are electrically connected to #142b, the source drain region of #140, such that it is electrically connected to the gate #156(u) of #140 as both #142b and #156(u) are parts of the transistor #140).
Regarding Claim 9. Chanemougame discloses A semiconductor device (Figures 1A-1E), comprising:
a first transistor (#120, Figure 1A, FET) comprising a first S/D (#122a, Figure 1A, source/drain region), a second S/D (#122b, Figure 1A, source/drain region), and a first gate (#151(u), Figure 1A, upper shared gate) between the first S/D and the second S/D (Figure 1A, #151(u) is between #122a and #122b);
a second transistor (#110, Figure 1A, FET) stacked directly under the first transistor (Figure 1A, #110 is directly under #120) and comprising a third S/D directly under the second S/D of the first transistor (#112b, Figure 1A, source/drain region directly under #122b);
a third transistor (#140, Figure 1A, FET) stacked over the second transistor (Figure 1A, #140 is stacked over #110);
a conductive trace (#194, Figure 1D, MOL contact) over the first transistor (Figure 1C, #194 is over #120 in that it is at a higher vertical level); and
a contact (#163 + #193, Figure 1C, embedded contact and insulated contact) covering the second S/D of the first transistor (Figure 1C, #163 and #193 combined at least partially covers a sidewall of #122b of #120), wherein the contact is electrically connected to the conductive trace (Figure 1C, #163 and #193 are electrically connected to #194 through #199 and #183, middle of the line (MOL) contact) and electrically isolated from the second S/D (Figure 1C, #163 and #193 are electrically isolated from #122b by dielectric sidewall spacer #195), and the contact comprises a first extension (Figure 1C, #163 functions as an extension between #122b and #112b) between a bottom surface of the second S/D and a top surface of the third S/D (Figure 1C, #163 is between a bottom surface of #122b and a top surface of #112b),
wherein the second S/D (#122b) is a shared S/D between the first transistor (#120) and the third transistor (#140) (column 7, lines 15-18, “a shared second source/drain region 122b/142a extends between the second channel region(s) 121 of the second FET 120 and second channel region(s) 141 of the second FET 140”, i.e. #122b is a shared S/D between #120 and #140).
Regarding Claim 10. Chanemougame discloses The semiconductor device according to Claim 9, wherein the contact further comprises a second extension (#183, Figures 1C and 1E, metal level wire) covering a top surface and two lateral surfaces of the second S/D (Figures 1C and 1E, #183, shown to be over #122b in a vertical direction, at least partially covers the top surface of #122b and partially covers two side surfaces of #122b, the side surface facing #193 and the side surface facing #156 in Figure 1E).
Regarding Claim 11. Chanemougame discloses The semiconductor device according to Claim 9, wherein the second transistor (#110, Figure 1A, FET) further comprises a fourth S/D directly under the first S/D (#112a, Figure 1A, source/drain region directly under #122a), and a second gate (151(l), Figure 1A, lower shared gate) between the third S/D and the fourth S/D (Figure 1A, #151(l) is between #112a and #112b), wherein the contact is electrically connected to the third S/D of the second transistor (Figure 1C, #163 and #193 are electrically connected to #112b).
Regarding Claim 12. Chanemougame discloses The semiconductor device according to Claim 11, wherein the third transistor comprises a fifth S/D (#142b, Figure 1A, source/drain region) electrically connected to the third S/D of the second transistor through the conductive trace and the contact (Figures 1C and 1D, #142b is electrically connected to #112b through #194, #183, #199, and #193/#163).
Regarding Claim 13. Chanemougame discloses The semiconductor device according to Claim 12, wherein the third transistor is offset from the second transistor from a top view perspective (Figures 1A and 1E, #140 is offset from #110 in the top view perspective of Figure 1E).
Regarding Claim 14. Chanemougame discloses The semiconductor device according to Claim 11, wherein the contact is conformally formed on the third S/D of the second transistor (Figure 1C, #163 is conformally formed on a top surface of #112b).
Regarding Claim 15. Chanemougame discloses The semiconductor device according to Claim 9, further comprising an isolation layer (#195 + #105, Figure 1C, dielectric sidewall spacer and thin dielectric layer) between and directly contacting the contact and the second S/D of the first transistor (Figure 1C, #195 is between and directly contacting #193 and #122b).
Regarding Claim 28. Chanemougame discloses The semiconductor device according to Claim 1, further comprising a conductive trace (#183, Figures 1C, 1D, and 1E, metal level wire) over the first transistor (Figures 1C, 1D, and 1E, #183 is over #120 in that it is at a higher vertical level),
a first via (#199, Figure 1C, middle of the line (MOL) contact) directly over the first contact (Figure 1C, #199 is directly over the combination of #193 and #163),
a second contact (#164, Figure 1B, embedded contact), and
a second via (#194, Figure 1D, MOL contact) between the conductive trace and the second contact (Figures 1B-1E, #194 is electrically between #183 and #164 by following the electrical pathway from #183 to #194 and through the first and second transistors (#120 and #140) and their respective S/D regions (#122a, #133b/#142a, and #142b) to #164),
wherein the first contact is electrically connected to the second contact through the first via, the conductive trace, and the second via (Figures 1B-1E, the combination of #193 and #163 is electrically connected to #164 by following the electrical pathway from #199 to #183 to #194 and through the first and second transistors (#120 and #140) and their respective S/D regions (#122a, #133b/#142a, and #142b) to #164).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 21, 23, and 25-27 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 10192819 B1; Chanemougame et al.; 01/2019; (“Chanemougame”) in view of US 2023/0197815 A1; Huang et al.; 06/2023; (“Huang”).
Regarding Claim 21. Chanemougame discloses A semiconductor device (Figures 1A-1E), comprising:
a first transistor (#120, Figure 1A, FET) comprising a first S/D (#122a, Figure 1A, source/drain region), a second S/D (#122b, Figure 1A, source/drain region), and a first gate (#151(u), Figure 1A, upper shared gate) between the first S/D and the second S/D (Figure 1A, #151(u) is between #122a and #122b);
a second transistor (#110, Figure 1A, FET) stacked directly under the first transistor (Figure 1A, #110 is directly under #120);
a third transistor (#140, Figure 1A, FET) stacked over the second transistor (Figure 1A, #140 is stacked over #110) and comprising a third S/D (#142b, Figure 1A, source/drain region);
a conductive trace (#183, Figures 1C, 1D, and 1E, metal level wire) over the first transistor (Figures 1C, 1D, and 1E, #183 is over #120 in that it is at a higher vertical level); and
a first contact (#163 + #193, Figure 1C, embedded contact and insulated contact) covering the second S/D of the first transistor (Figure 1C, #163 and #193 combined at least partially covers a sidewall of #122b of #120), wherein the first contact is electrically connected to third S/D of the third transistor through the conductive trace (Figures 1C and 1D, #163 and #193 are electrically connected to #142b through #183),
wherein the second transistor (#110) comprises a fourth S/D directly under the second S/D (#112b, Figure 1A, source/drain region directly under #122b), the fourth S/D comprises a conductive layer (#112b, Figure 1A, column 5 line 66 through column 6 line 2, #112b is heavily doped to have a high conductivity) and a spacer layer (#103, Figure 1C, conformal dielectric layer which may be interpreted as part of the S/D region) covering the conductive layer (Figure 1A, #103 covers a portion of #112b), the spacer layer has an opening exposing a portion of the conductive layer (Figure 1C, #103 has an opening which exposes a portion of #112b where the contact extends through to contact #112b); and
wherein the second S/D (#122b) is a shared S/D between the first transistor (#120) and the third transistor (#140) (column 7, lines 15-18, “a shared second source/drain region 122b/142a extends between the second channel region(s) 121 of the second FET 120 and second channel region(s) 141 of the second FET 140”, i.e. #122b is a shared S/D between #120 and #140).
Chanemougame does not disclose that the portion of the conductive layer is protruding out of the opening of the spacer layer and extending into a recess of the first contact.
However, Huang teaches a stacked transistor structure (Figure 1a, [0029]) comprising stacked combinations of upper transistors (upper devices) and lower transistors (lower devices) wherein contacts (#109) are formed to wrap around upper devices in order to make contact with the source/drain regions of lower devices (see Figure 2c) wherein the lower transistor comprises a source or drain region including a conductive layer (#103, Figure 2c) and a spacer layer (#105, dielectric) covering the conductive layer (Figure 2c, #105 at least partially covers the sidewalls of #103) and the spacer layer has an opening exposing a portion of the conductive layer (Figure 2c, #105 has an opening exposing the top portion of #103) and the portion of the conductive layer is protruding out of the opening of the spacer layer and extending into a recess of the first contact (Figure 2c, the top portion of #103 protrudes out of #105 and into a recess into #109).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the source/drain region of the lower transistor to protrude into the contact structure in Chanemougame as was done in Huang in order to maximize the contact area between the contact and the source/drain region and reduce contact resistance in stacked transistor structures (see [0015] of Huang).
Regarding Claim 23. Chanemougame in view of Huang discloses The semiconductor device according to Claim 21, further comprising
a first via (Chanemougame, #199, Figure 1C, middle of the line (MOL) contact) directly over the first contact (Chanemougame, Figure 1C, #199 is directly over the combination of #193 and #163),
a second contact (Chanemougame, #164, Figure 1B, embedded contact), and
a second via (#194, Figure 1D, MOL contact) between the conductive trace and the second contact (Chanemougame, Figures 1B-1E, #194 is electrically between #183 and #164 by following the electrical pathway from #183 to #194 and through the first and second transistors (#120 and #140) and their respective S/D regions (#122a, #133b/#142a, and #142b) to #164), and
the first contact is electrically connected to the second contact through the first via, the conductive trace, and the second via (Chanemougame, Figures 1B-1E, the combination of #193 and #163 is electrically connected to #164 by following the electrical pathway from #199 to #183 to #194 and through the first and second transistors (#120 and #140) and their respective S/D regions (#122a, #133b/#142a, and #142b) to #164).
Regarding Claim 25. Chanemougame in view of Huang discloses The semiconductor device according to Claim 21, further comprising an isolation layer (Chanemougame, #195 + #105, Figure 1C, dielectric sidewall spacer and thin dielectric layer) covering a circumferential surface of the second S/D (Chanemougame, Figure 1C, #195 and #105 in combination at least partially cover a circumferential surface of #122b) and contacting the first contact (Chanemougame, Figure 1C, #195 is contacting the combination of #163 and #193).
Regarding Claim 26. Chanemougame in view of Huang discloses The semiconductor device according to Claim 21, wherein the first contact directly contacts the portion of the conductive layer (Chanemougame, Figure 1C, #163 directly contacts the exposed portion of #112b; Huang, Figure 2c, #109 directly contacts the exposed portion of #103).
Regarding Claim 27. Chanemougame in view of Huang discloses The semiconductor device according to Claim 26, wherein the first contact is conformally formed on the portion of the conductive layer of the fourth S/D (Chanemougame, Figure 1C, #163 is conformally formed on an exposed top surface of #112b; Huang, Figure 2c, #109 is conformally formed on the exposed portion of #103).
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 10192819 B1; Chanemougame et al.; 01/2019; (“Chanemougame”) in view of US 2023/0197815 A1; Huang et al.; 06/2023; (“Huang”), as applied to claim 23 above, and further in view of US 20200203382 A1; Jung et al.; 06/2020; (“Jung”).
Regarding Claim 24. Chanemougame in view of Huang discloses The semiconductor device according to Claim 23, a thickness of the first contact (Chanemougame, combination of #163 and #193) is greater than a thickness of the second contact (Chanemougame, #164) (Chanemougame, Figures 1B and 1C, a vertical thickness of the combination of #163 and #193 is greater than a vertical thickness of #164 since #164 has a vertical thickness less than that of the source/drain region #122a while the combination of #163 and #193 extends fully through the source/drain region #122b and the source drain regions are shown to have the same vertical thickness in Figure 1A), and a thickness of the first via (Chanemougame, #199) is substantially the same as a thickness of the second via (Chanemougame, #194) (Chanemougame, Figure 1E, the horizontal thicknesses of #194 and #199 are substantially the same).
Chanemougame in view of Huang do not disclose that the first contact tapers in a direction away from the first via.
However, Jung teaches a structure comprising a plurality of stacked overlapping transistors (Figure 9) wherein all of the contacts to source/drain regions, in a direction away from their overlying vias, have a tapered shape with a narrower bottom (Figure 9, all of the source/drain electrodes #S1-2/#D1-2 have a shape which tapers in a direction away from their overlying vias).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider having contacts with a tapered structure in Chanemougame in view of Huang similar to the contacts of Jung as an obvious change of shape (see MPEP 2144.04.IV.B) absent persuasive evidence that the shape of the claimed contact as being tapered was significant. The formation of tapered vias is a known consequence of etching processes in semiconductor devices in which results in narrower openings as greater depths are etched into the underlying materials.
Response to Arguments/Amendments
Applicant’s amendments to claim 1, 9, and 21 and corresponding arguments, see pages 7-8 of the remarks, filed 12/19/2025, with respect to the rejections of claim 1, 9, and 21, and their respective dependent claims, have been fully considered but are not found persuasive. Applicant argues that the cited prior art do not disclose “the second S/D is a shared S/D between the first transistor and the third transistor” as recited in amended claim 21, along with the similar amendments which were made to claims 1 and 9. Examiner respectfully disagrees. Regrettably, upon further search and consideration of the cited prior art, in view of the amendments to claims 1, 9, and 21, it was determined that the amendments are disclosed by the cited prior art.
With regard to US 20200203382 A1; Jung et al.; 06/2020; (“Jung”), all 35 U.S.C. 102 rejections have been withdrawn as the Jung reference does not disclose the amended limitations.
With regard to US 10192819 B1; Chanemougame et al.; 01/2019; (“Chanemougame”), the reference does disclose that “the second S/D is a shared S/D between the first transistor and the third transistor”. Specifically, Figure 1A and column 7, lines 15-18, of the Chanemougame reference disclose that the second S/D (#122b/#142a) is a shared S/D between the first transistor (#120) and the neighboring third transistor (#140) (column 7, lines 15-18, “a shared second source/drain region 122b/142a extends between the second channel region(s) 121 of the second FET 120 and second channel region(s) 141 of the second FET 140”, i.e. #122b is a shared S/D between #120 and #140). For this reason, the amendments to claims 1, 9, and 21 have not been found allowable. Furthermore, all arguments that their respective dependent claims (3-7, 10-15, and 23-28) are allowable for their dependencies have been rendered moot as the independent claims have not been found allowable.
Claims 1, 3-7, 9-15, and 28 stand rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 10192819 B1; Chanemougame et al.; 01/2019; (“Chanemougame”).
Claims 21, 23, and 25-27 stand rejected under 35 U.S.C. 103 as being unpatentable over US 10192819 B1; Chanemougame et al.; 01/2019; (“Chanemougame”) in view of US 2023/0197815 A1; Huang et al.; 06/2023; (“Huang”).
Claim 24 stands rejected under 35 U.S.C. 103 as being unpatentable over US 10192819 B1; Chanemougame et al.; 01/2019; (“Chanemougame”) in view of US 2023/0197815 A1; Huang et al.; 06/2023; (“Huang”), as applied to claim 23 above, and further in view of US 20200203382 A1; Jung et al.; 06/2020; (“Jung”).
Conclusion
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/TYLER J WIEGAND/Examiner, Art Unit 2812