DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/09/2026 has been entered.
Response to Amendment
The Amendment filed on 02/09/2026 has been entered. Claims 10-11, 14 and 21 are canceled by Applicant. Claims 23-24 are new. Claims 1-9,12-13,15-20 and 22-24 are pending.
Response to Arguments
Applicant's arguments "Applicant Arguments/Remarks Made in an Amendment" with the
"Amendment/Req. Reconsideration-After Final Reject" filed on 02/09/2026, have been fully considered, the arguments are not persuasives and some of them are moot because do not apply to new ground of rejections with new references, US 20150108635 A1 to Liang and US 20170005074 A1 to Chen, being used in the current rejection, see detail below.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 15-17 and 20 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2016/0322330 A1, hereinafter Lin, of the record) in view of Liang (US 20150108635 A1, hereinafter Liang).
Re: Independent Claim 1, Lin discloses a method of forming a semiconductor package, comprising:
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Lin’s Figure 4-Annotated.
forming a redistribution layer structure (108A RDLs in [0021, 0022], Fig. 4) over a first die (102 a die in [0013], Fig. 4) and a dummy die (106 a dummy die in [0016], Fig. 4), wherein the redistribution layer structure (108A) is directly electrically connected to the first die (102);
forming an insulating layer (124-2 molding compound in 101B-2 in [0013], wherein 124-2 is formed over 108C, in [0022], Fig. 4-Annotated), wherein the insulating layer (124-2) and the redistribution layer structure (108A) are disposed on opposite sides of the first die (102);
forming at least one thermal through via (TIVs-2 in 101B-2, wherein additional fan-out tiers and/or interconnect features are formed over RDLs 108C in [0022], Fig. 4-Annotated), wherein the at least one thermal through via extends from a topmost surface of the insulating layer to a bottommost surface of the insulating layer.
Lin does not expressly disclose forming at least one opening in the insulating layer and after forming the redistribution layer structure and the insulating layer, forming at least one thermal through via in the at least one opening of the insulating layer.
However, in the same semiconductor device field of endeavor, Liang discloses forming at least one opening (opening several openings formed in the dielectric layer 152 in [0044], Figs. 6G-6H-Annotated) in the insulating layer (152 dielectric layer in [0044], Figs. 6G-6H-Annotated) and after forming (Figs. 6G-6H-Annotated) the redistribution layer structure (RDL a bottom RDL formed by 114,112,108,106 layers in [0044], Figs. 6E,6G-6H-Annotated) and the insulating layer (152), forming at least one thermal through via (158-159 metal structures filled into the openings in [0045], Figs. 6G-6H-Annotated) in the at least one opening (opening) of the insulating layer (152).
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Liang’s Figure 6H-Annotated.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to include the method of forming at least one opening in the insulating layer and after forming the redistribution layer structure and the insulating layer, forming at least one thermal through via in the at least one opening of the insulating layer since the selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results to simplify and improve the accuracy of the manufacture of the thermal vias. In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946); In re Gibson, 39 F.2d 975, 5 USPQ 230 (CCPA 1930). See MPEP § 2144.04.
Regarding claim 2, Lin modified by Liang discloses the method as claimed in claim 1, wherein the dummy die (106, Lin) is electrically connected (106 connected to 102 through 108A, Fig. 4, Lin) to the first die (102, Lin) through the redistribution layer structure (108A, Lin).
Regarding claim 3, Lin modified by Liang discloses the method as claimed in claim 1, further comprising forming at least one through via (126 a TIVs via extending through molding compound 124 in 101A in [0017], Fig. 4, Lin) aside the first die (102, Lin) between (126 between 108A and TIVs, Fig. 4, Lin) the redistribution layer structure (108A, Lin) and the at least one thermal through via (TIVs-2 in 101B-2, Lin).
Regarding claim 4, Lin modified by Liang discloses the method as claimed in claim 1, further comprising forming connectors (120 external connectors in [0020], Fig. 4, Lin) over the redistribution layer structure (108A, Lin).
Regarding claim 5, Lin modified by Liang discloses the method as claimed in claim 4,
Lin does not disclose wherein the first die is disposed in a first region, the dummy die is disposed in a second region, a density of the connectors in the first region is equal to the number of the connectors in the first region divided by an area of the first region, a density of the connectors in the second region is equal to the number of the connectors in the second region divided by an area of the second region, and the density of the connectors in the second region is larger than the density of the connectors in the first region.
However, the Applicant has not presented persuasive evidence that the claimed
“density of the connectors in the second region larger than the density of the connectors in the first region” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed density of the connectors in the second region larger than the density of the connectors in the first region). Also, the applicant has not shown that the claimed “difference of density of the connectors in the second region respect to the density of the connectors in the first region” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. At meantime, Lin discloses “a density of the connectors in the second region similar to the density of the connectors in the first region”, Fig. 4, therefore, the density is a result effective variable. It has been held that is not inventive to discover the optimum density of the connectors in the second region respect to the density of the connectors in the first region by routine experimentation (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), MPEP 2144.05 II). Thus, it would have been obvious to add the density of the connectors in the second region is larger than the density of the connectors in the first region to include more electronic devices.
Regarding claim 6, Lin modified by Liang discloses the method as claimed in claim 1, further comprising forming other redistribution layer structure (108B RDLs in [0021], Fig. 4, Lin) comprising a conductive pattern (RDLs including conductive features in [0029], Lin) disposed between and interfacing with the insulating layer (124-2, Lin) and the first die (102, Lin) and the dummy die (102, Lin), wherein the at least one thermal through via (TIVs in 101B, Lin) is electrically connected to the redistribution layer structure (108A, Lin) through the other redistribution layer structure (108B, Lin).
Regarding claim 7, Lin modified by Liang discloses the method as claimed in claim 4,
Lin does not disclose wherein the first die is disposed in a first region, the dummy die is disposed in a second region, a density of the at least one thermal through via in the first region is equal to the number of the at least one thermal through via in the first region divided by an area of the first region, a density of the at least one thermal through via in the second region is equal to the number of the at least one thermal through via in the second region divided by an area of the second region, and the density of the at least one thermal through via in the first region is larger than the density of the at least one thermal through via in the second region.
However, the Applicant has not presented persuasive evidence that the claimed
“density of the at least one thermal through via in the first region larger than the density of the at least one thermal through via in the second region” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed density of the at least one thermal through via in the first region larger than the density of the at least one thermal through via in the second region). Also, the applicant has not shown that the claimed “difference of density of the at least one thermal through via in the first region respect to the density of the at least one thermal through via in the second region” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. At meantime, Lin discloses “a density of thermal through via in 101B”, Fig. 4-Annotated, therefore, the density is a result effective variable. It has been held that is not inventive to discover the optimum density of the at least one thermal through via in the first region respect to the density of the at least one thermal through via in the second region by routine experimentation (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), MPEP 2144.05 II). Thus, it would have been obvious to add density of the at least one thermal through via in the first region larger than the density of the at least one thermal through via in the second region to include more electronic devices.
Regarding independent claim 15, Lin teaches a method of forming a semiconductor package, comprising:
forming a redistribution layer structure (108B, C RDLs in [0021, 0022], Fig. 4) over a carrier (carrier a carrier over 108C in [0029]);
after forming the redistribution layer structure (108B, C), forming at least one first through via (126 a TIVs via extending through molding compound 124 in 101A in [0017], Fig. 4) on the redistribution layer structure (108B, C) over the carrier (carrier);
encapsulating (124 TIVs via extending through molding compound 124 in [0017], Fig. 3F) the at least one first through via (126) with an encapsulant (124-101A Fig. 4) over the carrier (carrier);
after forming the at least one first through via (126), forming an insulating layer (124-2 molding compound in 101B-2 in [0013], wherein 124-2 is formed over 108C, in [0022], Fig. 4-Annotated) over the redistribution layer structure (108B, C);
Lin does not expressly disclose forming at least one opening in the insulating layer; and after forming the insulating layer, forming at least one thermal through via in the at least one opening, wherein the redistribution layer structure is electrically connected to the at least one first through via and the at least one thermal through via.
However, in the same semiconductor device field of endeavor, Liang discloses forming at least one opening (opening several openings formed in the dielectric layer 152 in [0044], Figs. 6G-6H-Annotated) in the insulating layer (152 dielectric layer in [0044], Figs. 6G-6H-Annotated); and after forming (Figs. 6G-6H-Annotated) the insulating layer (152), forming at least one thermal through via (158-159 metal structures filled into the openings in [0045], Figs. 6G-6H-Annotated) in the at least one opening (opening).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to include the method of forming at least one opening in the insulating layer; and after forming the insulating layer, forming at least one thermal through via in the at least one opening since the selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results to simplify and improve the accuracy of the manufacture of the thermal vias. In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946); In re Gibson, 39 F.2d 975, 5 USPQ 230 (CCPA 1930). See MPEP § 2144.04.
The combination of Lin and Liang results in forming at least one opening in the insulating layer; and after forming the insulating layer, forming at least one thermal through via in the at least one opening, wherein the redistribution layer structure is electrically connected to the at least one first through via and the at least one thermal through via.
Regarding claim 16, Lin modified by Liang discloses the method as claimed in claim 15, further comprising forming a die (102 a die in [0017], Fig. 4, Lin) aside the at least one first through via (126, Lin) in the encapsulant (124-101A, Lin), wherein the at least one thermal through via (TIVs-2, Lin) is electrically connected (TIVs-2 is connected to 102 through 108B, 108A and 126, Fig. 4-Annotated, Lin) to the die (102, Lin) through the at least one first through via (126, Lin).
Regarding claim 17, Lin modified by Liang discloses the method as claimed in claim 16, further comprising forming a die attach film (118 a die attach film in [0021], Fig. 4, Lin) between the die (102, Lin) and the at least one thermal through via (TIVs-2, Lin).
Regarding claim 20, Lin modified by Liang discloses the method as claimed in claim 15, wherein surfaces of the at least one first through via (126, Lin) and the encapsulant (124-101A, Lin) are substantially coplanar (as showed in Fig. 4, Lin).
Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Lin, in view of Liang and further in view of Eid et al. (US 20190214328 A1, hereinafter Eid, of the record).
Regarding claim 18, Lin modified by Liang discloses the method as claimed in claim 16, further comprising forming a paste (118 adhesive layer over 102 in [0030], Fig. 4, Lin) between (as showed in Fig. 4, Lin) the die (102, Lin) and the redistribution layer structure (108B, C, Lin), wherein the redistribution layer structure (108B, C, Lin) exposed by the at least one opening (Liang applied to Lin, vias TIVs-2 formed in 124-2 as vias 126 exposing 108C, Lin) interfaces with the paste (118, Lin) and the at least one thermal through via (TIVs-2, Lin).
Lin does not disclose that the adhesive layer (118) is a conductive paste.
However, in the same semiconductor device field of endeavor, Eid discloses a conductive paste (416 a thermal interface material layer in [0033], Fig. 6).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the current invention to make the Lin’s paste layer a conductive paste layer, according to Eid’s method to obtain wherein the redistribution layer structure exposed by the at least one opening interfaces with the conductive paste and the at least one thermal through via to improve the conveyance of heat from the electrical components ([0034], Eid).
Regarding claim 19, Lin modified by Liang and Eid discloses the method as claimed in claim 18, wherein the conductive paste (118’s Lin after applied Eid) is in direct contact (118 in direct contact with 108B and 102 as showed in Fig. 4, Lin) with the die (102) and the redistribution layer structure (108B, C, Fig. 4).
Claims 8-9 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Lin, in view of Eid et al. (US 20190214328 A1, hereinafter Eid, of the record) and further in view of Liang.
Regarding Independent Claim 8, Lin discloses a method of forming a semiconductor package, comprising:
providing a first die (102 a die in [0013], Fig. 4) and a dummy die (106 a dummy die in [0016], Fig. 4) with a paste (118 glue layer in [0021], Fig. 4-Annotated) thereon;
forming a redistribution layer structure (108A RDLs in [0021, 0022], Fig. 4) over the first die (102) and the conductive paste (118) and electrically connected (Fig. 4) to the first die (102);
after forming the redistribution layer structure (108A, Fig. 4), forming an insulating layer (124-2 molding compound in 101B-2 in [0013], wherein 124-2 is formed over 108C, in [0022], Fig. 4-Annotated) over the redistribution layer structure (108A).
Lin does not expressly disclose wherein the paste (118) is a conductive paste and after forming the insulating layer, forming at least one thermal through via (TIVs-2 in 101B-2, wherein additional fan-out tiers 101B and interconnect features are formed over RDLs 108C in [0022], Fig. 4-Annotated) in the insulating layer over the first die and the conductive paste, wherein the conductive paste is disposed between the first die and the at least one thermal through via, and the at least one thermal through via is electrically connected to the first die through the conductive paste.
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Eid’s Figure 6-Annotated.
However, in the same semiconductor device field of endeavor, Eid discloses a conductive paste (416 a thermal interface material layer in [0033], Fig. 6).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the current invention to make the Lin’s paste layer a conductive paste layer, wherein the conductive paste extends from a sidewall of the first die to a sidewall of the dummy die according to Eid’s method to improve the conveyance of heat from the electrical components ([0034], Eid).
Lin modified by Eid does not expressly disclose after forming the insulating layer, forming at least one thermal through via in the insulating layer over the first die and the conductive paste, wherein the conductive paste is disposed between the first die and the at least one thermal through via, and the at least one thermal through via is electrically connected to the first die through the conductive paste.
However, in the same semiconductor device field of endeavor, Liang discloses after forming (after the dielectric layer 152, 158-159 are formed in [0044], Figs. 6G-6H-Annotated)) the insulating layer (152 dielectric layer in [0044], Figs. 6G-6H-Annotated), forming at least one thermal through via (158-159 metal structures filled into the openings of 152 in [0045], Figs. 6G-6H-Annotated) in the insulating layer (152).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to include the method of after forming the insulating layer, forming at least one thermal through via in the insulating layer since the selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results to simplify and improve the accuracy of the manufacture of the thermal vias. In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946); In re Gibson, 39 F.2d 975, 5 USPQ 230 (CCPA 1930). See MPEP § 2144.04.
The combination of Lin, Eid and Liang results in after forming the insulating layer, forming at least one thermal through via in the insulating layer over the first die and the conductive paste, wherein the conductive paste is disposed between the first die and the at least one thermal through via, and the at least one thermal through via is electrically connected to the first die through the conductive paste.
Regarding claim 9, Lin modified by Eid and Liang discloses the method as claimed in claim 8, wherein the conductive paste (118’s Lin after applied Eid) is in direct contact (as showed in Fig. 4, Lin) with the first die (102, Lin).
Regarding claim 12, Lin modified by Eid and Liang discloses the method as claimed in claim 8, wherein the redistribution layer structure (108A, Lin) and the at least one thermal through via (TIVs-2, Lin) are disposed at opposite sides (as showed in Fig. 4-Annotated, Lin) of the first die (102, Lin).
Regarding claim 13, Lin modified by Eid and Liang discloses the method as claimed in claim 12, before forming the insulating layer (124-2, Fig. 4-Annotated, Lin), further comprising forming a plurality of connectors (120 external connectors in [0020], Fig. 4, Lin) on an outermost surface of the redistribution layer structure (108A, Lin), wherein the connectors (120, Lin) and the first die (102, Lin) are disposed on opposite sides of the redistribution layer structure (108A, Lin), and the redistribution layer structure (108A, Lin) is disposed between the connectors (120, Lin) and the first die (102, Lin).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Lin, in view of Eid, in view of Liang and further in view of Franz et al. (US 20190164892 A1, hereinafter Franz, of the record).
Regarding claim 22, Lin modified by Eid and Liang discloses the method as claimed in claim 8,
Lin modified by Eid and Liang does not disclose further comprising forming a patch antenna on the at least one thermal through via.
However, in the same semiconductor device field of endeavor, Franz discloses further comprising forming a patch antenna (22 metallization 22 forms an antenna structure in [0079], Fig. 4) on the at least one thermal through via (25 thermal via in [0079], Fig. 4).
It would have been obvious to one of ordinary skill in the art, at the time the invention was filed to include the Frank’s method of forming a patch antenna on the at least one thermal through via layer in the method of Lin combined with Eid and Liang to include a variety of purpose simultaneously ([0034] Franz).
Claim 23-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin, in view of Liang and further in view of Chen et al. (US 20170005074 A1, hereinafter Chen).
Regarding claim 23, Lin modified by Liang discloses the method as claimed in claim 15,
Lin modified by Liang does not expressly disclose further comprising: forming a dielectric layer between the carrier and the redistribution layer structure; forming a de-bonding layer interfacing with the carrier and the dielectric layer; and debonding the redistribution layer structure from the carrier before forming the insulating layer, wherein the dielectric layer interfaces with the insulating layer and the redistribution layer structure, and the at least one opening is further formed in the dielectric layer to expose the redistribution layer structure.
However, in the same semiconductor device field of endeavor, Chen discloses forming a dielectric layer (34 adhesive layer in [0011], Fig. 13) between the carrier (30 carrier substrate in [0014], Fig. 13) and the redistribution layer structure (68,70 conductive patterns 68 in dielectric layer 70 in [0032], Fig. 13); forming a de-bonding layer (32 adhesive layer in [0011], Fig. 13) interfacing with the carrier (30) and the dielectric layer (34); and debonding (Figs. 14-16) the redistribution layer structure (68,70) from the carrier (30).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the current invention to include the Chen’s method wherein forming a dielectric layer between the carrier and the redistribution layer structure; forming a de-bonding layer interfacing with the carrier and the dielectric layer; and debonding the redistribution layer structure from the carrier to the combination of Lin and Liang to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area ([0002], Chen).
The combination of Lin, Liang and Chen results in debonding (Chen applied to Lin) the redistribution layer structure (108C RDLs in [0021, 0022], Fig. 4, Lin) from the carrier (30 removed, Fig. 16 from Chen applied to Lin) before (120 formed before 124-2, Fig. 4-Annotated, Lin) forming the insulating layer (124-2, Fig. 4-Annotated, Lin), wherein the dielectric layer (Chen’s 34 applied to Lin) interfaces with the insulating layer (124-2, Fig. 4-Annotated, Lin) and the redistribution layer structure (108C RDLs in [0021, 0022], Fig. 4, Lin), and the at least one opening (Liang applied to Lin) is further formed in the dielectric layer (Chen’s 34 applied to Lin) to expose (Liang applied to Lin, vias Lin’s TIVs-2 formed in 124-2 as vias 126 exposing 108C, then the addition dielectric 34 from Chen, results in the exposed 108C’s Lin) the redistribution layer structure (108C RDLs in [0021, 0022], Fig. 4, Lin).
Regarding claim 24, Lin modified by Liang discloses the method as claimed in claim 15, further comprising: forming another redistribution layer structure (108A RDLs in [0021, 0022], Fig. 4, Lin) over the encapsulant (124-101A, Fig. 4, Lin); forming a plurality of connectors (120 external connectors in [0020], Fig. 4, Lin) on an outermost surface of the another redistribution layer structure (108A, Fig. 4, Lin).
Lin modified by Liang does not expressly disclose forming another redistribution layer structure (108A, Fig. 4, Lin) over the carrier and after forming the connectors and before forming the insulating layer, removing the carrier.
However, in the same semiconductor device field of endeavor, Chen discloses forming another redistribution layer structure (68,70 conductive patterns 68 in dielectric layer 70 in [0032], Fig. 13) over the carrier (30 carrier substrate in [0014], Fig. 13) and after (Figs. 14-16) forming the connectors (30 a set of conductive connectors in [0035], Fig. 14), removing (Fig. 16) the carrier (30, Fig. 13).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the current invention to include the Chen’s method wherein forming another redistribution layer structure over the carrier and after forming the connectors, removing the carrier to the combination of Lin and Liang to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area ([0002], Chen).
The combination of Lin, Liang and Chen results in after (Chen applied to Lin) forming the connectors (120 Fig. 4, Lin) and before (120 formed before 124-2, Fig. 4-Annotated, Lin) forming the insulating layer (124-2, Fig. 4-Annotated, Lin), removing the carrier (30 removed, Fig. 16 from Chen applied to Lin).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kim (US 20160172291 A1) teaches “SEMICONDUCTOR PACKAGE”. This document is related to a semiconductor package including a package substrate with a top surface and a bottom surface opposite to the top surface, the top surface of the package substrate configured to have a semiconductor chip mounted thereon, a power block and a ground block in the package substrate, the power block configured as a power pathway penetrating the package substrate, and the ground block configured as a ground pathway penetrating the package substrate, first vias extended from the power block and the ground block, and the first vias electrically connected to the semiconductor chip, second vias extended from the power block and the ground block toward the bottom surface of the package substrate, and block vias to penetrate the power block and the ground block, the block vias electrically connected to the semiconductor chip and electrically separated from the power block and the ground block.
Choi (US 20190287873 A1) teaches “METHOD OF PACKAGING THIN DIE AND SEMICONDUCTOR DEVICE INCLUDING THIN DIE”. This document is related to a semiconductor device having a carrier and a semiconductor die disposed over the carrier. A dummy die is disposed over the carrier as well. A first encapsulant is deposited over the semiconductor die and dummy die. The dummy die and a first portion of the first encapsulant is backgrinded while a second portion of the first encapsulant remains covering the semiconductor die. Backgrinding the dummy die fully removes the dummy die while the second portion of the first encapsulant remains covering the semiconductor die. A second encapsulant is optionally deposited over the dummy die prior to disposing the dummy die over the carrier. A conductive pillar is optionally formed over the dummy die prior to depositing the second encapsulant. The carrier is removed to expose an active surface of the semiconductor die. A build-up interconnect structure is formed over the active surface after removing the carrier.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA M RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898