Prosecution Insights
Last updated: April 19, 2026
Application No. 17/750,570

Display Apparatus and Manufacturing Method of Display Apparatus

Final Rejection §103§112
Filed
May 23, 2022
Examiner
RODRIGUEZ VILLANU, SANDRA MILENA
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Semiconductor Energy Laboratory Co. Ltd.
OA Round
4 (Final)
89%
Grant Probability
Favorable
5-6
OA Rounds
2y 11m
To Grant
99%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allow Rate
98 granted / 110 resolved
+21.1% vs TC avg
Moderate +10% lift
Without
With
+10.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
36 currently pending
Career history
146
Total Applications
across all art units

Statute-Specific Performance

§103
49.7%
+9.7% vs TC avg
§102
27.4%
-12.6% vs TC avg
§112
21.4%
-18.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 110 resolved cases

Office Action

§103 §112
DETAILED ACTION General Remarks The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment The Amendment filed on 02/06/2026 has been entered. Claims 5-8 are canceled. Claim 16 is new. Claims 1-4, 9-16 are pending Response to Arguments Applicant’s arguments "Applicant Arguments/Remarks Made in an Amendment" with the "Amendment/Req. Reconsideration-After Non-Final Reject" filed on 02/06/2026, have been fully considered, the Applicant’s arguments related to the Jongman’s device (US 20210407974 A1), describes: "…The rejection, however, does not identify this alleged "boundary" in Jongman. In the rejection, the Office provides an annotated copy of Jongman's Figure 10. In the annotated figure, the Office appears to be contending that the claimed boundary between the first element layer and the second element layer is by via 23. Thereby, the Office divided the set of backplane 13 and substrate 11 into two layers by using via 23 which appears to be what the Office is contending corresponds to the claimed boundary…". However, the Applicant’s arguments are not persuasive because the Jongman’s describes a “depth boundary surface” adjacent to via 23, as showed in Jongman’s Figure 10-Annotated in the previous non-final action (11/06/2025), the “boundary” does not correspond to via 23. In addition, the term “boundary” means a line which marks the limits of an area, as the “depth boundary surface” showed in Jongman and is consistent with the specification of the application, a new annotated Jongman’s Figure 10 (enlarged) is added to clarify, see the rejection below. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. Claim 16 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention (Figure 1, 23A). Regarding claim 16, it recites the limitation “a scan line driver circuit at an end of the light-emitting element layer, and wherein the scan line driver circuit is electrically connected to the plurality of pixels”. It is not clear where is the “a scan line driver circuit” in the light-emitting element layer. The scan line driver circuit is described in paragraph [0411] and included in Figure 23A, as element 464, however, 464 is not included in the light-emitting element layer. For the examination purpose and according to Figure 1, the limitation “a scan line driver circuit at an end of the light-emitting element layer, and wherein the scan line driver circuit is electrically connected to the plurality of pixels” is interpreted as “a driver circuit at an end of the first element layer, and wherein the driver circuit is electrically connected to the plurality of pixels”. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document. Claims 9, 11-13 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Jongman et al. (US 20160014882 A1, hereinafter Jongman, of the record) in view of Jiang (US 20210407974 A1, hereinafter Jiang, of the record). Regarding independent Claim 9, Jongman discloses a display apparatus comprising: PNG media_image1.png 601 975 media_image1.png Greyscale Jongman’s Figure 10-Annotated. PNG media_image2.png 236 416 media_image2.png Greyscale Jongman’s enlarged-Figure 10-Annotated. a plurality of pixels (4a-p, 4b-p and 4c-p a plurality of pixels formed by displays units 4a, 4b, backplane layer 13 and substrate 11, driver chip 5a-5b and interconnections 25 in [0022,0095,0100,0101,0106], Fig. 10-Annotated) each comprising a light-emitting element (LED an emissive included in the plurality of display units 4a,4b in [0120], Fig. 10-Annotated) and a transistor (the backplane 13 comprises a plurality of transistors in [0022]) electrically connected (transistor are connected to LED to drive a region of the display in [0022], Fig. 10-Annotated) to the light-emitting element (LED), an element layer (9, 5a, 25-9, 5b, 25 including a controller 9 (including 13 and 11), driver circuits 5a-5b and interconnections 25 in [0096], [0099], [0105], Fig. 10-Annotated), a light-emitting element layer (4a-4b-4c including a plurality of display units in [0095], Fig. 10-Annotated) over the element layer (9, 5a, 25-9, 5b, 25), wherein the element layer (9, 5a, 25-9, 5b, 25) includes a first element layer (9, 5a, 25 including a controller 9, a driver circuit 5a and interconnection 25 in [0096], [0099], [0105], Fig. 10-Annotated) and a second element layer (9, 5b, 25 including a controller 9, a driver circuit 5b and interconnection 25 in [0096], [0099], [0105], Fig. 10, Annotated), and a boundary therebetween (a depth boundary surface in Section-Fig. 10-Annotated by clarification), wherein the light-emitting element layer (4a-4b-4c) includes a first light-emitting element layer (4a a first display unit in [0095], Fig. 10) and a second light-emitting element layer (4b a second display unit in [0095], Fig. 10), and a boundary therebetween, wherein the plurality of pixels (4a-p, 4b-p and 4c-p) includes (in Fig. 10-Annotated) a first pixel (4a-p), a second pixel (4b-p) and a third pixel (4c-p), wherein the first pixel (4a-p) comprises a first light-emitting element (an LED in 4a in [0120]) in the first light-emitting element layer (4a), and a first transistor (T1 a transistor included in the backplane 13, transistors are connected to LED to drive a region of the display in [0022], Fig. 10-Annotated) in the first element layer (9, 5a, 25), wherein the first transistor (T1) is configured to drive the first light-emitting element (transistors, in the backplane 13 are connected to LED to drive a region of the display in [0022], Fig. 10-Annotated), wherein the second pixel (4b-p) comprises a second light-emitting element (an LED in 4b in [0120]) in the second light-emitting element layer (4b), and a second transistor (T2 a transistor included in the backplane 13 in [0022], Fig. 10-Annotated) in the first element layer (9, 5a, 25, Fig. 10-Annotated), wherein the second transistor (T2) is configured to drive the second light-emitting element (transistors, in the backplane 13 are connected to LED to drive a region of the display in [0022], Fig. 10-Annotated), wherein the third pixel (4c-p) comprises a third light-emitting element (a second LED in 4b in [0120], Fig. 10-Annotated) in the second light-emitting element layer (4b), and a third transistor (T3 a transistor included in the backplane 13 in [0022], Fig. 10-Annotated) in the second element layer (9, 5b, 25, Fig. 10-Annotated), and wherein the third transistor (T3) is configured to drive the third light-emitting element (transistors, in the backplane 13 are connected to LED to drive a region of the display in [0022], Fig. 10-Annotated), Jongman does not expressly disclose wherein the display apparatus comprises a first film an element layer (9, 5a, 25-9, 5b, 25) over the first film, a light-emitting element layer (4a-4b-4c) over the element layer (9, 5a, 25-9, 5b, 25), and a second film over the element layer. However, in the same semiconductor device field of endeavor, Jiang discloses a wherein the display apparatus comprises a first film (100 a substrate layer in [0033], Fig. 3) an element layer (300 an array substrate in [0033], Fig. 3) over the first film (100), a light-emitting element layer (400 a display layer in [0033], Fig. 3) over the element layer (300), and a second film (600 an encapsulation layer in [0033], Fig. 3) over the element layer (300), It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to the Jiang’s feature wherein the display apparatus comprises a first film, an element layer over the first film, a light-emitting element layer over the element layer, and a second film over the element layer to Jongman’s device to protect the display panel ([0040], Jiang). Regarding Claim 11, Jongman modified by Jiang discloses the display apparatus according to claim 9, Jongman modified by Jiang does not expressly disclose wherein each of the first film and the second film is transparent. However, in the same semiconductor device field of endeavor, Jiang discloses wherein each of the first film (100) and the second film (600) is transparent (600 made of a transparent material to allow the light transmission in [0044] and 100 made of glass in [0040]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to the Jiang’s feature wherein each of the first film and the second film is transparent to Jongman’s device to protect the display panel ([0040], Jiang). Regarding Claim 12, Jongman modified by Jiang discloses the display apparatus according to claim 9, wherein said each light-emitting element (4a-4b-4c, Jongman) in the plurality of pixels is any one of an organic EL element and a micro LED (an LED in 4a-4b-4c in [0120], Jongman). Regarding Claim 13, Jongman modified by Jiang discloses an electronic device (a reflective display apparatus in [0001], Jongman) comprising the display apparatus according to claim 9. Regarding Claim 15, Jongman modified by Jiang discloses the display apparatus according to claim 9, wherein the second light-emitting element (LED in 4b in [0120], Jongman) and the second transistor (T2, Jongman) overlap each other (Fig. 10-Annotated, Jongman). Regarding Claim 16, Jongman modified by Jiang discloses the display apparatus according to claim 9, wherein the display apparatus further comprises a driver circuit (5a, 25 a driver circuit 5a and interconnection 25, wherein driver circuits includes scan line driver circuits in [0096], [0105], Fig. 10, Jongman) at an end of the first element layer (9, 5a, 25, Jongman), and wherein the driver circuit (5a, 25, Jongman) is electrically connected to the plurality of pixels (4a-p, 4b-p and 4c-p in [0022,0095,0100,0101,0106], Fig. 10-Annotated, Jongman). Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Jongman et al. in view of Jiang and further in view of Tsukamoto et al. (US 20200043381 A1, hereinafter Tsukamoto, of the record). Regarding Claim 10, Jongman modified by Jiang discloses the display apparatus according to claim 9, Jongman modified by Jiang does not expressly disclose further comprising a polarizing film over the second film. However, in the same semiconductor device field of endeavor, Tsukamoto discloses a polarizing film (166 a circularly polarizing plate in [0074], Fig. 1C). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Tsukamoto’s feature of a polarizing film to the combination of the device of Jongman and Jiang to prevent for seeing an overlapping area because of the reflection of light at surfaces and the inside of the display panels ([0074], Tsukamoto). Allowable subject matter Claims 1-4 and 14 are allowed. The following is an examiner’s statement of reasons for allowance: The closest prior art to the present invention is (US 2016/0014882 A1 to Jongman) discloses a display apparatus having a flexible display panel and driver electronics to drive the flexible display panel and methods of forming a flexible display unit for a reflective display apparatus having a flexible display panel and driver electronics to drive the flexible display panel, and more particularly to tiled displays comprising reflective, e.g., electrophoretic, display medium. Re: Independent Claim 1, there is no teaching or suggestion in the prior art of record to provide: “a first driver circuit portion in the first element layer… …and a second driver circuit portion in an end portion of the first element layer… … the second light-emitting element and the second driver circuit portion overlap each other” recited in claim 1. Missing elements in the closest art gives rise to the innovation in the current invention. Therefore, the claim 1 is allowed. Regarding claims 2-4 and 14, they are allowed due their dependencies of claim 1. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA M RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898 /JESSICA S MANNO/SPE, Art Unit 2898
Read full office action

Prosecution Timeline

May 23, 2022
Application Filed
Feb 24, 2025
Non-Final Rejection — §103, §112
May 28, 2025
Response Filed
Jul 10, 2025
Final Rejection — §103, §112
Oct 17, 2025
Request for Continued Examination
Oct 17, 2025
Response after Non-Final Action
Oct 29, 2025
Response after Non-Final Action
Nov 03, 2025
Non-Final Rejection — §103, §112
Feb 06, 2026
Response Filed
Mar 19, 2026
Final Rejection — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
89%
Grant Probability
99%
With Interview (+10.3%)
2y 11m
Median Time to Grant
High
PTA Risk
Based on 110 resolved cases by this examiner. Grant probability derived from career allow rate.

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