DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/14/2026 has been entered.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on 5/14/2026. Claims 17, 25, 30, 32-33, and 39 have been amended. Claims 40-42 have been added. Claims 19, 29, and 31 have been canceled. Currently, claims 17, 20-22, 25-28, 30, and 32-42 are pending.
Response to Arguments
Regarding independent claim 17, Applicant argues neither Cheng nor Sawada teach or suggest the following claim amendments added into claim 1: “wherein a first length of a top surface of the first conductive bond pad is substantially equal to a second length of a bottom surface of the first conductive bond pad in a first cross-sectional view, wherein a third length of a top surface of the second conductive bond pad is substantially equal to a fourth length of a bottom surface of the second conductive bond pad in a second cross-sectional view substantially orthogonal to the first cross-sectional view” and “wherein the lateral routing structure has a fifth length in the second cross-sectional view less than the third length and greater than a width of the second conductive bond pad in the first cross-sectional view, and wherein a width of the lateral routing structure in the first cross-sectional view is less than the fifth length.” Examiner agrees.
However, the new limitations necessitated further search and consideration, and new prior art Cheng et al. (US 20200328180), Yamagishi et al. (US 20210351219), and Furuhashi et al. (US 20190386052) have been found or considered. Therefore, Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable under Cheng in view of Yamagishi and Furuhashi, as described below. As a result, the rejection of claim 17 and its dependent claims is maintained.
Regarding independent claim 25, Applicant argues neither Cheng nor Okina teach or suggest the claim amendments added into claim 25, e.g. forming a redistribution structure on the second interconnect structure. Examiner agrees.
However, the new limitations necessitated further search and consideration, and new prior art Wu et al. (US 20200058617), Cheng et al. (US 20200328180), Choi et al. (US 20220399316), Chen et al. (US 20210098423), and Park et al. (US 20210020544) have been found or considered. Therefore, Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable under Wu in view of Cheng, Choi, Chen, and Park, as described below. As a result, the rejection of claim 25 and its dependent claims is maintained.
Regarding claim 32, Applicant argues neither Cheng nor Sawada teach or suggest the claim amendments added into claim 32, e.g. wherein a second bond via in the second plurality of conductive bond structures overlies and contacts the second conductive structure, wherein the second bond via is laterally offset from the first conductive structure in the first direction, and wherein the first bond via is laterally offset from the second conductive structure in a second direction substantially orthogonal to the first direction. Examiner agrees.
However, the new limitations necessitated further search and consideration, and new prior art Wu et al. (US 20200058617) and Yamagishi et al. (US 20210351219) have been found or considered. Therefore, Claim 32 is rejected under 35 U.S.C. 103 as being unpatentable under Wu in view of Yamagishi, as described below. As a result, the rejection of claim 32 and its dependent claims is maintained.
All other arguments have been fully addressed in prior Office Actions or in the rejections set forth below.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the newly added limitation “wherein the first length is greater than the third length” in the fifth to last line of the claim 1 (see also the 35 USC § 112(a) rejection below) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 17, 20-22, 33, 35, and 37-40 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor at the time the application was filed, had possession of the claimed invention.
Claim 17 recites “wherein the first length is greater than the third length” in the fifth to last line of the claim. As described in claim 1 and shown in present application Figs. 11-12, the first length is “of a top surface of the first conductive bond pad [126a] in a first cross-sectional view [y-z plane]” (see lines 21-23 of claim 1), and the third length is “of a top surface of the second conductive bond pad [126b] in a second cross-sectional view [x-z plane] substantially orthogonal to the first cross-sectional view” (see lines 24-26 of claim 1).
However, none of the present application’s figures or specification show that the first length of the first conductive bond pad 126a extending in the y-direction is greater than the third length of the second conductive bond pad 126b extending in the x-direction. Fig. 12 only shows that the first conductive bond pad extends in the y-direction and that the second conductive bond pad 126b extends in the x-direction, and not the relationship between the two lengths. Also, para. [0058] of the specification only explains that along the y-axis, the “width” of 126a is greater than the “width” of 126b; and that along the x-axis, the length of 126b is greater than the “length” of 126a. No part of the specification, including para. [0058], explains that the “width” of 126a along the y-axis is greater than the length of 126b along the x-axis.
Therefore, because of the newly amended language of claim 17, the claim language of claim 17 has been determined to be new matter. This is because this concept is not present in the original disclosure of the specification or claims, as explained above.
Claims 20-22, 37-40, because they are dependent on claim 17, inherit the deficiency of claim 17.
Claim 33 recites “wherein a length of the lateral surface of the first conductive structure in the second direction is greater than the length of the lateral surface of the second conductive structure in the first direction” in lines 3-5 of the claim. Similar to the 112(a) rejection of claim 17 above, none of the present application’s figures or specification show that the length of the first conductive structure 126a extending in the y-direction is greater than the length of the second conductive structure 126b extending in the x-direction.
Therefore, because of the newly amended language of claim 33, the claim language of claim 33 has been determined to be new matter. This is because this concept is not present in the original disclosure of the specification or claims, as explained above.
Claim 35, because it is dependent on claim 33, inherit the deficiency of claim 33.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17, 22, and 38-40 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 20200328180, hereinafter “Cheng”) in view of Yamagishi et al. (US 20210351219) and Furuhashi et al. (US 20190386052, cited by Applicant in the Information Disclosure Statement filed on 3/13/2026).
Regarding claim 17, Cheng teaches, in Figs. 8A-9B and 11A-11B, a method for forming an integrated circuit (IC) ([0024]-[0025], [0027]), the method comprising:
forming, in Fig. 9A, a plurality of first semiconductor devices (904, [0117]) on a first substrate (902, [0117]), wherein the first semiconductor devices (904) predominately comprise a first type of IC device (memory stack) and are formed by a first fabrication process ([0117], “a memory stack 904 can be formed by a gate replacement process, e.g., replacing the sacrificial layers with conductor layers 906 using wet/dry etch of the sacrificial layers selective to dielectric layers 908 and filling the resulting recesses with conductor layers 906”) (see Fig. 9A);
forming, in Fig. 9B, a first hybrid bond structure (922, [0120]) on the first substrate (902) (see Fig. 9B);
forming, in Fig. 8A, a plurality of second semiconductor devices (808, [0131]) on a second substrate (802, [0131]), wherein the second semiconductor devices (808) predominately comprise a second type of IC device (processor) different from the first type of IC device (memory stack), wherein the second semiconductor devices (808) are formed by a second fabrication process different than the first fabrication process ([0131], “a plurality of transistors 804 are formed on a silicon substrate 802 … by a plurality of processes including, but not limited to, photolithography, dry/wet etch, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes”) (see Fig. 8A);
forming, in Fig. 8B, a second hybrid bond structure (816 and top horizontal wire of layer 814, [0133]) on the second substrate (802), wherein the second hybrid bond structure comprises a lateral routing structure (top wire of layer 814) (see Fig. 8B); and
bonding, in Figs. 11A-11B, the first hybrid bond structure (922) to the second hybrid bond structure (816 and top wire of layer 814) such that the second semiconductor devices (808) are laterally offset from at least one of the first semiconductor devices (904) by a non-zero distance (see Fig. 11B), wherein the lateral routing structure (top wire of layer 814) continuously extends along the non-zero distance and electrically couples the at least one of the first semiconductor devices (904) to the second semiconductor devices (808), wherein bonding the first hybrid bond structure (922) to the second hybrid bond structure (816 and top wire of layer 814) forms a bonded metal structure ([0086], labelled as 730/726/top wire of layer 724 in Fig. 7A) comprising a first conductive bond pad (924, [0138]) of the first hybrid bond structure (922) and a second conductive bond pad (818, [0138]) of the second hybrid bond structure (816) (see Figs. 11A-11B),
wherein the first conductive bond pad (924) contacts the second conductive bond pad (818) (see Fig. 11B).
Cheng does not teach that a first length of a top surface of the first conductive bond pad is substantially equal to a second length of a bottom surface of the first conductive bond pad in a first cross-sectional view, wherein a third length of a top surface of the second conductive bond pad is substantially equal to a fourth length of a bottom surface of the second conductive bond pad in a second cross-sectional view substantially orthogonal to the first cross-sectional view,
that the first length is greater than the third length, and
that the lateral routing structure has a fifth length in the second cross-sectional view less than the third length and greater than a width of the second conductive bond pad in the first cross-sectional view, and wherein a width of the lateral routing structure in the first cross-sectional view is less than the fifth length.
In a similar field of endeavor, Yamagishi teaches, in Fig. 11, that a first length of a top surface of the first conductive bond pad (202, [0111]) is substantially equal to a second length of a bottom surface of the first conductive bond pad (202) in a first cross-sectional view (Fig. 11 view), wherein a third length of a top surface of the second conductive bond pad (302, [0111]) is substantially equal to a fourth length of a bottom surface of the second conductive bond pad (302) in a second cross-sectional view (side view) substantially orthogonal to the first cross-sectional view (see how 202 and 302 have rectangular cross-sections in both cross-sectional views),
that the first length (of 202) is greater than the third length (of 302) (see middle section of Fig. 11, [0113]),
so that “effective use of a region in the proximity of the joining plane of the semiconductor substrate is achieved” ([0020]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method for forming an integrated circuit of Cheng with the bond pad lengths of Yamagishi, so that effective use of bonding region is achieved ([0020]).
Cheng in view of Yamagishi does not teach that that the lateral routing structure has a fifth length in the second cross-sectional view less than the third length and greater than a width of the second conductive bond pad in the first cross-sectional view, and wherein a width of the lateral routing structure in the first cross-sectional view is less than the fifth length.
In a similar field of endeavor, Furuhashi teaches, in Figs. 8-9, that the lateral routing structure (58, [0058]) has a fifth (L1 direction) length in the second cross-sectional view less than the third (L1 direction) length (of 72, [0065]) (see Fig. 9), in order to further downsize the device and reduce the material cost ([0075]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method for forming an integrated circuit of Cheng in view of Yamagishi with the lateral routing structure length of Furuhashi, in order to further downsize the device and reduce the material cost ([0075]).
However, Cheng in view of Yamagishi and Furuhashi does not explicitly teach that the lateral routing structure has a fifth length in the second cross-sectional view greater than a width of the second conductive bond pad in the first cross-sectional view, and that a width of the lateral routing structure in the first cross-sectional view is less than the fifth length. Nonetheless, the skilled artisan would know too that the length of the lateral routing structure would impact device size and material cost (Furuhashi, [0075]).
The specific claimed lengths, absent any criticality, is only considered to be the “optimum” lengths disclosed by Cheng in view of Yamagishi and Furuhashi that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired device size, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long as the lateral routing structure being a fifth length in the second cross-sectional view greater than a width of the second conductive bond pad in the first cross-sectional view, and a width of the lateral routing structure in the first cross-sectional view being less than the fifth length are used, as already suggested by Cheng in view of Yamagishi and Furuhashi.
Since the applicant has not established the criticality (see next paragraph) of the lengths stated and since these lengths are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Cheng in view of Yamagishi and Furuhashi.
Please note that the specification contains no disclosure of either the critical nature of the claimed lengths or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 22, Cheng in view of Yamagishi and Furuhashi teaches the limitations of claim 17. Cheng further teaches forming a first interconnect structure (920, [0119]) between the first substrate (902) and the first hybrid bond structure (922) (see Fig. 9B); and
forming a second interconnect structure (814 excluding top wire, [0132]) between the second substrate (802) and the second hybrid bond structure (816 and top wire of layer 814), wherein the first (922) and second (816 and top wire of layer 814) hybrid bond structures electrically couple the first interconnect structure (920) to the second interconnect structure (814 excluding top wire) (see Fig. 8B).
Regarding claim 38, Cheng in view of Yamagishi and Furuhashi teaches the limitations of claim 17. Furuhashi teaches that in the second cross-sectional view (view shown by Fig. 3) outer sidewalls of the lateral routing structure (58) are spaced between outer sidewalls of the second conductive bond pad (72, [0065]) (see Fig. 3).
Regarding claim 39, Cheng in view of Yamagishi and Furuhashi teaches the limitations of claim 17. However, Cheng in view of Yamagishi and Furuhashi does not explicitly teach that in the first cross-sectional view the width of the lateral routing structure is equal to the width of the second conductive bond pad. Nonetheless, the skilled artisan would know too that the width of the lateral routing structure would impact device size and material cost (Furuhashi, [0075]).
The specific claimed widths, absent any criticality, is only considered to be the “optimum” widths disclosed by Cheng in view of Yamagishi and Furuhashi that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired device size, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long in the first cross-sectional view the width of the lateral routing structure being equal to the width of the second conductive bond pad is used, as already suggested by Cheng in view of Yamagishi and Furuhashi.
Since the applicant has not established the criticality (see next paragraph) of the widths stated and since these widths are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Cheng in view of Yamagishi and Furuhashi.
Please note that the specification contains no disclosure of either the critical nature of the claimed widths or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 40, Cheng in view of Yamagishi and Furuhashi teaches the limitations of claim 17. Furuhashi further teaches, in Figs. 8-9, that the first hybrid bond structure (81/52/53, [0105], [0110], [0066]) comprises a first bond via (52, [0110]) contacting the first conductive bond pad (81, [0105]) and the second hybrid bond structure (72/56/64/58, [0065]-[0066], [0076], [0084]) comprises a second bond via (64, [0076]) contacting the second conductive bond pad (72, [0065]) and the lateral routing structure (58, [0084]).
Yamagishi further teaches, in Figs. 11 (middle section) and 12 (left middle section), that the first bond via (209, [0116]) is laterally offset from the second conductive bond pad (202, [0112]) in a first (horizontal) direction, and that the second bond via (309, Fig. 12, [0116]) is laterally offset from the first conductive bond pad (302, [0112]) in a second direction (that 202 is elongated) substantially orthogonal to the first (horizontal) direction (see Fig 12, left middle section).
Claims 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 20200328180, hereinafter “Cheng”) in view of Yamagishi et al. (US 20210351219) and Furuhashi et al. (US 20190386052, cited by Applicant in the Information Disclosure Statement filed on 3/13/2026), and further in view of Zhang et al. (US 12069854).
Regarding claim 20, Cheng in view of Yamagishi and Furuhashi teaches the limitations of claim 17. Cheng further teaches, in Fig. 8A, forming a plurality of third semiconductor devices (810, [0131]) on the second substrate (802) laterally offset from the second semiconductor devices (808) (see Fig. 8A),
wherein the third semiconductor devices (810) predominately comprise a third type of IC device (SRAM cells, [0131]),
wherein the third type of IC device (SRAM cells) is different from the second type of IC device (808, processor) ([0131]).
Cheng in view of Yamagishi and Furuhashi does not explicitly teach that the third semiconductor devices are formed by a third fabrication process different from the second fabrication process.
In a similar field of endeavor, Zhang teaches, in Fig. 11A, that the third semiconductor devices (1108) are formed by a third fabrication process different from the second fabrication process (of second semiconductor devices 1122, col. 28, lines 10-25) (col. 26; line 55 – col. 27, line 15), in order to “reduce the planar chip size of the peripheral circuits, as well as the total chip size of the memory device” (col. 6, lines 60-65).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method for forming an integrated circuit (IC) of Cheng in view of Yamagishi and Furuhashi with the third fabrication process of Zhang, in order to reduce the planar chip size of the peripheral circuits, as well as the total chip size of the memory device (col. 6, lines 60-65).
Regarding claim 21, Cheng in view of Yamagishi and Furuhashi teaches the limitations of claim 17. Cheng in view of Yamagishi and Furuhashi does not teach depositing a first dielectric layer over the second substrate; forming a through substrate via (TSV) in the first dielectric layer and the second substrate, wherein the TSV is electrically coupled to one or more conductive structures in the second hybrid bond structure; forming a conductive pad in a second dielectric layer over the first dielectric layer, wherein the conductive pad is coupled to the TSV; and forming a conductive bond bump structure on the conductive pad.
In a similar field of endeavor, Zhang teaches, in Fig. 11A, depositing a first dielectric layer (see dielectric layer of 1012, labelled in Fig. 11C; col. 25, lines 15-25) over the second substrate (1004);
forming a through substrate via (TSV) (1124; col. 29, lines 25-40) in the first dielectric layer (in 1012) and the second substrate (1004) (see Fig. 11A), wherein the TSV is electrically coupled to one or more conductive structures (1009 and 1011; col. 29, lines 30-40) in the second hybrid bond structure (1008 and 1010; col. 30, lines 1-15);
forming a conductive pad (see first pad right below 105 under 1124) in a second dielectric layer (dielectric layer of 1112; col. 27, lines 25-35) over the first dielectric layer (in 1012), wherein the conductive pad is coupled to the TSV (1124) (see Fig. 11A); and
forming a conductive bond bump structure (see bump below the conductive pad) on the conductive pad (see Fig. 11A),
in order to “reduce the planar chip size of the peripheral circuits, as well as the total chip size of the memory device” (col. 6, lines 60-65).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method for forming an integrated circuit (IC) of Cheng in view of Yamagishi and Furuhashi with the forming of dielectric layers and connections of Zhang, in order to reduce the planar chip size of the peripheral circuits, as well as the total chip size of the memory device (col. 6, lines 60-65).
Claims 25-26, 28, and 41 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20200058617) in view of Cheng et al. (US 20200328180, hereinafter “Cheng”), Choi et al. (US 20220399316), Chen et al. (US 20210098423), and Park et al. (US 20210020544).
Regarding claim 25, Wu teaches, in Figs. 1, 2, 18, and 4, a method for forming an integrated circuit (IC) ([0003]-[0004]), the method comprising:
forming a plurality of first semiconductor devices (102, [0016]) on a first substrate (100, [0013]), wherein the plurality of first semiconductor devices predominately comprise a first type of IC device ([0016], “may be, for example, MOSFETs, IGFETS, MIM capacitors, flash memory cells, or the like”) (see Fig. 1);
forming a first interconnect structure (204, [0020]) on the first substrate (100), wherein the first interconnect structure comprises a plurality of conductive wires (206, [0020]) vertically stacked with a plurality of conductive vias (208, [0020]) (see Fig. 1);
forming a first hybrid bond structure (see Fig. 18, [0021], structure disposed in and including dielectric layer 220, labelled as bottom half of 332 in Fig. 4) on the first interconnect structure (204), wherein the first hybrid bond structure comprises a first plurality of conductive bond structures (224, [0025]) and a first plurality of conductive bond vias (see Fig. 4, 218/222, [0013], [0017]) in a first bond dielectric structure (220), wherein the first plurality of conductive bond vias (218/222) contact the first plurality of conductive bond structures (224) and a topmost wire level of the plurality of conductive wires (206, [0013]) (see Fig. 18);
forming a plurality of second semiconductor devices (402, [0016]) on a second substrate (400, [0014]) (see Fig. 2);
forming a second interconnect structure (404, [0014]) on the second substrate (400) (see Fig. 2, [0014]);
forming a redistribution structure (232, [0014]) on the second interconnect structure (404), wherein the redistribution structure comprises a plurality of redistribution wires (314/414) vertically stacked with a plurality of redistribution vias (312/412) (see Fig. 2, [0014]);
forming a second hybrid bond structure (labelled in Fig. 4 as 304 and top half of 332) on the redistribution structure (232) ([0015], [0017]), wherein the second hybrid bond structure comprises a second plurality of conductive bond structures (324, [0017]) in a second bond dielectric structure (320, [0017]) and a routing structure (304, [0020]) between the second bond dielectric structure (320) and the redistribution structure (232) (see Fig. 4), wherein the routing structure (304) comprises a plurality of conductive routing structures (306/308, [0020]) in a dielectric structure (310, [0020]) (see Fig. 4); and
bonding the first hybrid bond structure to the second hybrid bond structure (see Fig. 3 for the bonding step, Fig. 4 shows the structure, [0015], [0017]), wherein a bond interface (Fig. 4, middle of 332) is between the first hybrid bond structure and the second hybrid bond structure, and wherein a first subset of the plurality of conductive routing structures (right set of 306/308) electrically couples a first conductive bond structure (right 224) in the first plurality of conductive bond structures (224) to one of the second semiconductor devices (402) (see Fig. 4).
Wu does not teach wherein a height of the first plurality of conductive bond vias is greater than a height of the first plurality of conductive bond structures and a height of the topmost wire level;
wherein the plurality of second semiconductor devices predominately comprise a second type of IC device different from the first type of IC device;
wherein thicknesses of the plurality of redistribution wires are greater than thicknesses of the plurality of conductive wires; and
wherein thicknesses of lateral structures of the plurality of conductive routing structures are less than the thicknesses of the plurality of redistribution wires.
In a similar field of endeavor, Cheng teaches, in Fig. 11B, that the plurality of second semiconductor devices (808) predominately comprise a second type of IC device ([0131, processor transistors) different from the first type of IC device (904, [0137], memory stacks), in order to “improve the processor and memory performance with faster data transfer rate, improve processor core logic efficiency with wider bandwidth, and improve system speed” ([0051]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method for forming an integrated circuit of Wu with the plurality of second semiconductor device type of Cheng, in order to “improve the processor and memory performance with faster data transfer rate, improve processor core logic efficiency with wider bandwidth, and improve system speed” ([0051]).
Wu in view of Cheng does not explicitly teach that thicknesses of the plurality of redistribution wires are greater than thicknesses of the plurality of conductive wires; and
wherein thicknesses of lateral structures of the plurality of conductive routing structures are less than the thicknesses of the plurality of redistribution wires.
In a similar field of endeavor, Choi teaches, in Fig. 10, wherein thicknesses (320T) of the plurality of redistribution wires (320) are greater than thicknesses (132T) of the plurality of conductive wires (132) ([0037]); and
wherein thicknesses (32T) of lateral structures of the plurality of conductive routing structures (32a and 32b) are less than the thicknesses (320T) of the plurality of redistribution wires (320) ([0037]),
in order to provide a semiconductor package with improved thermal radiation properties ([0047]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method for forming an integrated circuit of Wu in view of Cheng with the redistribution wire thicknesses of Choi, in order to provide a semiconductor package with improved thermal radiation properties ([0047]).
Wu in view of Cheng and Choi does not teach that a height of the first plurality of conductive bond vias is greater than a height of the first plurality of conductive bond structures.
In a similar field of endeavor, Chen teaches, in Fig. 3, that a height of the first plurality of conductive bond vias (110b, [0023]) is greater than a height of the first plurality of conductive bond structures (110a, [0023]) ([0021], because “the thickness of the first dielectric layer 108a is larger than the thickness of the second dielectric layer 108b”), in order to “save manufacturing cost and optimize device performance” ([0002]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method for forming an integrated circuit of Wu in view of Cheng and Choi with the bond via heights of Chen, in order to “save manufacturing cost and optimize device performance” ([0002]).
However, Wu in view of Cheng, Choi, and Chen does not explicitly teach that a height of the first plurality of conductive bond vias is greater than a height of the topmost wire level. Nonetheless, the skilled artisan would know too that heights of conductive bond vias would impact planar cross-sectional area and miniaturization (Park, [0003], [0024]).
The specific claimed heights, absent any criticality, is only considered to be the “optimum” heights disclosed by Wu in view of Cheng, Choi, Chen, and Park that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired planar cross-sectional area, device size, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long as a height of the first plurality of conductive bond vias being greater than a height of the topmost wire level is used, as already suggested by Wu in view of Cheng, Choi, Chen, and Park.
Since the applicant has not established the criticality (see next paragraph) of the heights stated and since these heights are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Wu in view of Cheng, Choi, Chen, and Park.
Please note that the specification contains no disclosure of either the critical nature of the claimed heights or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 26, Wu in view of Cheng, Choi, Chen, and Park teaches the limitations of claim 25. Cheng further teaches, in Fig. 8A, forming a plurality of third semiconductor devices (810, [0131]) predominately comprising a third type of IC device (SRAM cells) on the second substrate (802, [0131]); and
forming a plurality of fourth semiconductor devices (812, [0131]) predominately comprising a fourth type of IC device (peripheral circuit transistors) on the second substrate (802), wherein the third type of IC device (810) and the fourth type of IC device (812) are different from each other and the second type of IC device (808, processor transistors), and wherein the plurality of third semiconductor devices (810) are spaced laterally between the plurality of second semiconductor devices (808) and the plurality of fourth semiconductor devices (812) (see Figs. 8A and 11B).
Regarding claim 28, Wu in view of Cheng, Choi, Chen, and Park teaches the limitations of claim 26. Cheng further teaches, in Fig. 11B, that a second subset of the plurality of conductive routing structures (top wire layer of 814 over devices 810, [0132]) electrically couples a second conductive bond structure (third from right 1018) in the first plurality of conductive bond structures (924/1018, [0120], [0127]) to one of the third semiconductor devices (810, [0131]), and
that a third subset of the plurality of conductive routing structures (top wire layer of 814 over devices 812) electrically couples a third conductive bond structure (right 1016) in the first plurality of conductive bond structures (924/1018) to one of the fourth semiconductor devices (812) (see Fig. 11B).
Regarding claim 41, Wu in view of Cheng, Choi, Chen, and Park teaches the limitations of claim 25. However, Wu in view of Cheng, Choi, Chen, and Park does not teach that thicknesses of the second plurality of conductive bond structures are less than the thicknesses of the plurality of redistribution wires. Nonetheless, the skilled artisan would know too that the thicknesses of the plurality of redistribution wires would impact thermal radiation properties of the semiconductor package (Choi, [0047]).
The specific claimed thicknesses, absent any criticality, is only considered to be the “optimum” thicknesses disclosed by Wu in view of Cheng, Choi, Chen, and Park that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired thermal radiation properties, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long that thicknesses of the second plurality of conductive bond structures being less than the thicknesses of the plurality of redistribution wires is used, as already suggested by Wu in view of Cheng, Choi, Chen, and Park.
Since the applicant has not established the criticality (see next paragraph) of the thicknesses stated and since these thicknesses are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Wu in view of Cheng, Choi, Chen, and Park.
Please note that the specification contains no disclosure of either the critical nature of the claimed thicknesses or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20200058617) in view of Cheng et al. (US 20200328180, hereinafter “Cheng”), Choi et al. (US 20220399316), Chen et al. (US 20210098423), and Park et al. (US 20210020544), and further in view of Yokoyama et al. (US 20180240797) and Zhang et al. (US 12069854).
Regarding claim 27, Wu in view of Cheng, Choi, Chen, and Park teaches the limitations of claim 26. Wu in view of Cheng, Choi, Chen, and Park does not teach that the first type of IC device is a logic device, the second type of IC device is a radio frequency device, the third type of IC device is an input/output device, and the fourth type of IC device is a high voltage device.
In a similar field of endeavor, Yokoyama teaches, in Figs. 28A and 29, that the first type of IC device (110) is a logic device ([0067]), the second type of IC device (230A, Fig. 28A) (20, labeled in Fig. 3; Fig. 29) is a radio frequency device ([0072]-[0073], [0103]), and the third type of IC device (210) is an input/output device ([0070]), in order to “provide a stacked body having a configuration suitable for easier manufacturing while reducing a mounting area” ([0008]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method for forming an integrated circuit (IC) of Wu in view of Cheng, Choi, Chen, and Park with the IC device types of Yokoyama, in order to provide a stacked body having a configuration suitable for easier manufacturing while reducing a mounting area ([0008]).
Wu in view of Cheng, Choi, Chen, Park, and Yokoyama do not teach that the fourth type of IC device is a high voltage device.
In a similar field of endeavor, Zhang teaches, in Fig. 11A, that the third type of IC device (1120) is an input/output device (col. 28, lines 10-25), in order to “reduce the planar chip size of the peripheral circuits, as well as the total chip size of the memory device” (col. 6, lines 60-65).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method for forming an integrated circuit (IC) of Wu in view of Cheng, Choi, Chen, Park, and Yokoyama with the third type of IC device of Zhang, in order to reduce the planar chip size of the peripheral circuits, as well as the total chip size of the memory device (col. 6, lines 60-65).
Claim 30 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20200058617) in view of Cheng et al. (US 20200328180, hereinafter “Cheng”), Choi et al. (US 20220399316), Chen et al. (US 20210098423), and Park et al. (US 20210020544), and further in view of Cheng et al. (US 20200350286, hereinafter “Cheng II”).
Regarding claim 30, Wu in view of Cheng, Choi, Chen, and Park teaches the limitations of claim 28. Wu further teaches, in Fig. 4, that the first subset of the plurality of conductive routing structures (right set of 306/308) comprises a lateral routing structure (bottom right 306),
wherein a first portion (bottom portion) of the lateral routing structure (bottom right 306) directly overlies the first conductive bond structure (right 224) (see Fig. 4).
Wu in view of Cheng, Choi, Chen, and Park does not teach that a second portion of the lateral routing structure directly overlies the second conductive bond structure.
In a similar field of endeavor, Cheng II teaches, in Fig. 7B, that a second portion of the lateral routing structure (leftmost portion of top interconnect line of 512, [0082]) directly overlies the second conductive bond structure (third from the right 624, [0087]), in order to achieve “overall faster system speed” ([0038]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method for forming an integrated circuit of Wu in view of Cheng, Choi, Chen, and Park with the lateral routing structure configuration of Cheng II, in order to achieve overall faster system speed ([0038]).
Claims 32-33, 35, and 42 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20200058617) in view of Yamagishi et al. (US 20210351219).
Regarding claim 32, Wu teaches in Figs. 1, 2, 18, and 4, a method for forming an integrated circuit (IC) ([0003]-[0004]), the method comprising:
forming a first IC structure (10/20, Fig. 1, [0013]) comprising a first substrate (100, [0013]), a first plurality of semiconductor devices (102, [0016]) on the first substrate (100), a first interconnect structure (104, [0013]) on the first substrate (100), and a first plurality of conductive bond structures (plurality of 222/224, [0025]) on the first interconnect structure (104) (see Figs. 1 and 18);
forming a second IC structure (30/40, Fig. 2, [0014]) comprising a second substrate (400, [0014]), a second plurality of semiconductor devices (402, [0016]) on the second substrate (400), a second interconnect structure (404, [0014]) on the second substrate (400), and a second plurality of conductive bond structures (plurality of 322/324, [0017], see Fig. 4) on the second interconnect structure (404) ([0015], [0017]) (see Figs. 2 and 4);
bonding the first IC structure (10/20) to the second IC structure (30/40) such that a bond interface (Fig. 4, middle of 332) is between the first plurality of conductive bond structures (plurality of 222/224) and the second plurality of conductive bond structures (plurality of 322/324) ([0015], [0017]), wherein a first conductive structure (left 224) in the first plurality of conductive bond structures contacts a second conductive structure (left 324) in the second plurality of conductive bond structures at the bond interface (middle of 332, see Fig. 4),
wherein a first bond via (left 222, [0017]) in the first plurality of conductive bond structures (plurality of 222/224) underlies and contacts the first conductive structure (left 224), wherein a second bond via (left 332) in the second plurality of conductive bond structures (plurality of 322/324) overlies and contacts the second conductive structure (left 324) (see Fig. 4).
Wu does not teach, in Figs. 1, 2, 18, and 4, that the second conductive structure comprises a lateral surface elongated in a first direction and contacting the first conductive structure, wherein a length of the lateral surface in the first direction is greater than a length of the first conductive structure in the first direction; and
that the second bond via is laterally offset from the first conductive structure in the first direction, and wherein the first bond via is laterally offset from the second conductive structure in a second direction substantially orthogonal to the first direction.
In a similar field of endeavor, Yamagishi teaches, in Figs. 11 (middle section) and 12 (left middle section), that the second conductive structure (302, [0112]) comprises a lateral surface elongated in a first (horizontal) direction and contacting the first conductive structure (202, [0112]), wherein a length of the lateral surface (of 302) in the first (horizontal) direction is greater than a length of the first conductive structure (202) in the first (horizontal) direction (see Fig. 11, middle section, [0113]); and
that the second bond via (309, Fig. 12, [0116]) is laterally offset from the first conductive structure (202) in the first (horizontal) direction, and wherein the first bond via (209, [0116]) is laterally offset from the second conductive structure (302) in a second direction (that 202 is elongated) substantially orthogonal to the first (horizontal) direction (see Fig 12, left middle section),
so that “effective use of a region in the proximity of the joining plane of the semiconductor substrate is achieved” ([0020]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method for forming an integrated circuit of Wu with the bond lengths and bond via locations of Yamagishi, so that effective use of a bonding region is achieved ([0020]).
Regarding claim 33, Wu in view of Yamagishi teaches the limitations of claim 32. Yamagishi further teaches, in Fig. 11 (middle section), that the first conductive structure (202, [0111]) comprises a lateral surface elongated in the second (horizontal) direction, and
that a length of the lateral surface of the first conductive structure in the second direction is greater than the length of the lateral surface of the second conductive structure (302, [0111]) in the first direction (going into page) (see middle section of Fig. 11, [0113]).
Regarding claim 35, Wu in view of Yamagishi teaches the limitations of claim 33. Wu further teaches that a third conductive structure (right 324) in the second plurality of conductive bond structures (plurality of 322/324) is adjacent to the second conductive structure (left 324) and has a length in the first direction substantially equal to the length of the first conductive structure (left 224) in the first direction ([0013], “The redistribution layers … may have rectangular, rounded or other applicable shapes from a top view”).
Regarding claim 42, Wu in view of Yamagishi teaches the limitations of claim 32. Wu further teaches, in Fig. 4, a bond routing structure (336/338, [0017]) between the second plurality of conductive bond structures (plurality of 322/324) and the second interconnect structure (404), wherein the bond routing structure (336/338) comprises a lateral routing structure (left 336) on the second bond via (left 322), wherein a first (left) sidewall of the lateral routing structure (left 336) overlies a conductor-to-conductor bond region of the bond interface (middle of 332), and wherein a second (right) sidewall of the lateral routing structure (left 336) overlies a dielectric-to-conductor bond region of the bond interface (middle of 332) (see Fig. 4).
Claims 34 and 36 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20200058617) in view of Yamagishi et al. (US 20210351219), and further in view of Sawada et al. (US 20220189905).
Regarding claim 34, Wu in view of Yamagishi teaches the limitations of claim 32. Wu further teaches, in Fig. 4, that the first IC structure (10/20) further comprises a first bond dielectric (220, [0017]) around the first plurality of conductive bond structures (plurality of 222/224).
However, Wu in view of Yamagishi does not teach that a first area of the lateral surface of the second conductive structure contacting the first conductive structure is less than a second area of the lateral surface of the second conductive structure contacting the first bond dielectric. Nonetheless, the skilled artisan would know too that the contact area of the lateral surface of the second conductive structure with the first conductive structure would impact contact resistance, and that the second area would impact positioning error (Sawada, [0093]).
The specific claimed areas, absent any criticality, is only considered to be the “optimum” areas disclosed by Wu in view of Yamagishi and Sawada that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired contact resistance, positioning error, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long as the first area being less than the second area is used, as already suggested by Wu in view of Yamagishi and Sawada.
Since the applicant has not established the criticality (see next paragraph) of the areas stated and since these areas are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Wu in view of Yamagishi and Sawada.
Please note that the specification contains no disclosure of either the critical nature of the claimed areas or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 36, Wu in view of Yamagishi and Sawada teaches the limitations of claim 34. Wu further teaches, in Fig. 4, that a third conductive structure (right 224) in the first plurality of conductive bond structures (plurality of 222/224) contacts a fourth conductive structure (right 324) in the second plurality of conductive bond structures (plurality of 322/324) (see Fig. 4), wherein a width of the third conductive structure (right 224) is equal to a width of the fourth conductive structure (right 324).
Yamagishi further teaches, in Fig. 4, that the width of the third conductive structure (left 301, [0093]) is less than the length of the lateral surface of the second conductive structure (202) (see Fig. 4).
Claim 37 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 20200328180, hereinafter “Cheng”) in view of Yamagishi et al. (US 20210351219) and Furuhashi et al. (US 20190386052, cited by Applicant in the Information Disclosure Statement filed on 3/13/2026), and further in view of Wu et al. (US 20200058617).
Regarding claim 37, Cheng in view of Yamagishi and Furuhashi teaches the limitations of claim 22. Cheng further teaches that the second interconnect structure (814 excluding top wire) comprises a conductive wire (bottom wire of 814) electrically coupled to the lateral routing structure (top wire of 814) (see Fig. 8B).
Cheng in view of Yamagishi and Furuhashi does not teach that a thickness of the lateral routing structure is greater than a thickness of the conductive wire.
In a similar field of endeavor, Wu teaches, in Fig. 4, that a thickness of the lateral routing structure (324/412) is greater than a thickness of the conductive wire (406) (see Fig. 4), in order to improve the processing capability and power consumption of the ICs ([0001]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method for forming an integrated circuit of Cheng in view of Yamagishi and Furuhashi with the thicknesses of Wu, in order to improve the processing capability and power consumption of the ICs ([0001]).
Conclusion
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/ERIKA H SON/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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