DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on 12/23/2025. Claims 17, 19, 25, and 31-36 have been amended. Claims 37-39 have been added. Claims 18, 23, and 24 have been canceled. Currently, claims 17, 19-22, and 25-39 are pending.
Response to Arguments
Applicant’s arguments filed 12/23/2025 have been considered but are moot as applied to the newly added claim limitations because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 17, 19, 22, 32, 34, 37, and 38 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 20200350286) in view of Sawada et al. (US 20220189905).
Regarding claim 17, Cheng teaches a method for forming an integrated circuit (IC) ([0016]-[0017] and [0019]), the method comprising:
forming a plurality of first semiconductor devices (604, Fig. 6A, [0084], memory stacks) on a first substrate (602), wherein the first semiconductor devices (604) predominately comprise a first type of IC device and are formed by a first fabrication process ([0084]) (see Fig. 6A);
forming a first hybrid bond structure (622, Fig. 6B, [0087]) on the first substrate (602) (see Fig. 6B);
forming a plurality of second semiconductor devices (504, Fig. 5A, [0081]) on a second substrate (502), wherein the second semiconductor devices (504) predominately comprise a second type of IC device ([0081], logic transistors) different from the first type of IC device, wherein the second semiconductor devices (504) are formed by a second fabrication process different than the first fabrication process ([0081]) (see Fig. 5A);
forming a second hybrid bond structure (514 and top interconnect line of 512; Figs. 5B-5C) on the second substrate (502), wherein the second hybrid bond structure comprises a lateral routing structure (top interconnect line of 512) (see Figs. 5B-5C); and
bonding the first hybrid bond structure to the second hybrid bond structure (see Figs. 7A-7B) such that the second semiconductor devices (504) are laterally offset from at least one of the first semiconductor devices (604) by a non-zero distance (see Fig. 7B), wherein the lateral routing structure (top interconnect line of 512) continuously extends along the non-zero distance and electrically couples the at least one of the first semiconductor devices (604) to the second semiconductor devices (504) (see Fig. 7B), wherein bonding the first hybrid bond structure to the second hybrid bond structure forms a bonded metal structure (first 516/624 to the right) comprising a first conductive bond pad (first 624 to the right) of the first hybrid bond structure and a second conductive bond pad (first 516 to the right) of the second hybrid bond structure, wherein the first conductive bond pad (first 624 to the right) has a first length in a first cross-sectional view (x-y plane) and the second conductive bond pad (first 516 to the right) has a second length in a second cross-sectional view (side view orthogonal to x-y plane), wherein the first conductive bond pad (first 624 to the right) contacts the second conductive bond pad (first 516 to the right).
Cheng does not explicitly teach that the first length is greater than the second length.
In a similar field of endeavor, Sawada teaches, in Fig. 19, that the first length (of first conductive bond pad 38 in x-direction) is greater than the second length (of second conductive bond pad 41 in y-direction) ([0091], both are squares), which “makes it possible to restrain a problem caused by an error in positioning of the metal pad 38 and the metal pad 41” because “the contact area between the metal pad 38 and the metal pad 41 does not vary, and the contact resistance between the metal pad 38 and the metal pad 41 does not vary” ([0093]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the lengths of the conductive bond pads of Cheng with the lengths of the conductive bond pads of Sawada, in order to maintain a constant contact area between these bonds pads even if there is a positioning error ([0093]).
Regarding claim 19, Cheng in view of Sawada teaches the limitations of claim 17. Sawada further teaches, in Fig. 1, that the lateral routing structure (42/43, [0025]) has a third length (of 42) in the second cross-sectional view (side view orthogonal to xz plane) less than the second length (of 41, [0025]) and a width (of 42) in the first cross-sectional view (xz plane) less than the first length (of 38).
Regarding claim 22, Cheng in view of Sawada teaches the limitations of claim 17. Cheng further teaches, in Fig. 6B, forming a first interconnect structure (620) between the first substrate (704) and the first hybrid bond structure (622); and,
in Fig. 5C, forming a second interconnect structure (portion of 512 below top interconnect) between the second substrate (502) and the second hybrid bond structure (514 and top interconnect line of 512), wherein the first (622) and second hybrid bond structures (514 and top interconnect line of 512) electrically couple the first interconnect structure (620) to the second interconnect structure (portion of 512 below top interconnect) (see Fig. 7B).
Regarding claim 32, Cheng teaches a method for forming an integrated circuit (IC) ([0016]-[0017] and [0019]), the method comprising:
forming a first IC structure comprising a first substrate (602), a first plurality of semiconductor devices (604, Fig. 6A, [0084], memory stacks) on the first substrate (602) (see Fig. 6A), a first interconnect structure (620) on the first substrate (602) (see Fig. 6B), and a first plurality of conductive bond structures (624) on the first interconnect structure (620);
forming a second IC structure comprising a second substrate (502) (see Fig. 5A), a second plurality of semiconductor devices (504, Fig. 5A, [0081]) on the second substrate (502) (see Fig. 5A), a second interconnect structure (portion of 512 below top interconnect) on the second substrate (502) (see Fig. 5C), and a second plurality of conductive bond structures (516) on the second interconnect structure (portion of 512 below top interconnect) (see Fig. 5C); and
bonding the first IC structure to the second IC structure (see Figs. 7A-7B) such that a bond interface (702, Fig. 7B) is between the first plurality of conductive bond structures (624) and the second plurality of conductive bond structures (516) (see Fig. 7B),
wherein a first conductive structure (second 624 from the right) in the first plurality of conductive bond structures (624) contacts a second conductive structure (second 516 from the right) in the second plurality of conductive bond structures (516) at the bond interface,
wherein the second conductive structure (516 from the right) comprises a lateral surface (top surface) in a first direction (x-direction) and contacting the first conductive structure (second 624 from the right).
Cheng does not explicitly teach that the lateral surface is elongated in a first direction, and that a length of the lateral surface in the first direction is greater than a length of the first conductive structure in the first direction.
In a similar field of endeavor, Sawada teaches, in Fig. 19, that the lateral surface (top surface of 38, [0091]) is elongated in a first direction (x-direction), and that a length of the lateral surface in the first direction is greater than a length of the first conductive structure (41, [0091]) in the first direction (x-direction), which “makes it possible to restrain a problem caused by an error in positioning of the metal pad 38 and the metal pad 41” because “the contact area between the metal pad 38 and the metal pad 41 does not vary, and the contact resistance between the metal pad 38 and the metal pad 41 does not vary” ([0093]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the lengths of the conductive bond pads of Cheng with the lengths of the conductive bond pads of Sawada, in order to maintain a constant contact area between these bonds pads even if there is a positioning error ([0093]).
Regarding claim 34, Cheng in view of Sawada teaches the limitations of claim 32. Cheng further teaches, in Fig. 7B, that the first IC structure further comprises a first bond dielectric ([0052]) around the first plurality of conductive bond structures (624, labelled as 330 in Fig. 3A).
Sawada further teaches, in Fig. 19, a first area of a lateral surface (top surface) of the second conductive structure (38, [0091]) contacting the first conductive structure (41, [0091]), and a second area (area that left 61 covers) of the lateral surface (top surface) of the second conductive structure (38) contacting the first bond dielectric (13e/14e, [0041]).
However, Cheng in view of Sawada does not explicitly teach that the first area is less than the second area. Nonetheless, the skilled artisan would know too that the contact area of the lateral surface of the second conductive structure with the first conductive structure would impact contact resistance, and that the second area would impact positioning error (Sawada, [0093]).
The specific claimed areas, absent any criticality, is only considered to be the “optimum” areas disclosed by Cheng in view of Sawada that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired contact resistance, positioning error, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long as the first area being less than the second area is used, as already suggested by Cheng in view of Sawada.
Since the applicant has not established the criticality (see next paragraph) of the areas stated and since these areas are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Cheng in view of Sawada.
Please note that the specification contains no disclosure of either the critical nature of the claimed areas or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 37, Cheng in view of Sawada teaches the limitations of claim 22. Sawada further teaches, in Fig. 1, that the second interconnect structure comprises a conductive wire (BL, [0022]) electrically coupled to the lateral routing structure (41/42, [0025]), wherein a thickness of the lateral routing structure (41/42) is greater than a thickness of the conductive wire (BL) (see Fig. 1).
Regarding claim 38, Cheng in view of Sawada teaches the limitations of claim 17. Sawada further teaches that in the second cross-sectional view (side view orthogonal to xz plane) outer sidewalls of the lateral routing structure (of 42) are spaced between outer sidewalls of the second conductive bond pad (41) (see Fig. 1, [0091]).
Claims 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 20200350286) in view of Sawada et al. (US 20220189905), and further in view of Zhang et al. (US 12069854).
Regarding claim 20, Cheng in view of Sawada teaches the limitations of claim 17. Cheng in view of Sawada does not explicitly teach forming a plurality of third semiconductor devices on the second substrate laterally offset from the second semiconductor devices, wherein the third semiconductor devices predominately comprise a third type of IC device and are formed by a third fabrication process different from the second fabrication process, wherein the third type of IC device is different from the second type of IC device.
In a similar field of endeavor, Zhang teaches, in Fig. 11A, forming a plurality of third semiconductor devices (1108) on the second substrate (1004) laterally offset from the second semiconductor devices (1122),
wherein the third semiconductor devices (1108) predominately comprise a third type of IC device and are formed by a third fabrication process different from the second fabrication process (col. 26; line 55 – col. 27, line 15; high voltage), wherein the third type of IC device (high voltage) is different from the second type of IC device (logic),
in order to “reduce the planar chip size of the peripheral circuits, as well as the total chip size of the memory device” (col. 6, lines 60-65).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method for forming an integrated circuit (IC) of Cheng in view of Sawada with the forming of a plurality of third semiconductor devices of Zhang, in order to reduce the planar chip size of the peripheral circuits, as well as the total chip size of the memory device.
Regarding claim 21, Cheng in view of Sawada teaches the limitations of claim 17. Cheng in view of Sawada does not explicitly teach depositing a first dielectric layer over the second substrate; forming a through substrate via (TSV) in the first dielectric layer and the second substrate, wherein the TSV is electrically coupled to one or more conductive structures in the second hybrid bond structure; forming a conductive pad in a second dielectric layer over the first dielectric layer, wherein the conductive pad is coupled to the TSV; and forming a conductive bond bump structure on the conductive pad.
In a similar field of endeavor, Zhang teaches, in Fig. 11A, depositing a first dielectric layer (see dielectric layer of 1012, labelled in Fig. 11C; col. 25, lines 15-25) over the second substrate (1004);
forming a through substrate via (TSV) (1124; col. 29, lines 25-40) in the first dielectric layer (in 1012) and the second substrate (1004) (see Fig. 11A), wherein the TSV is electrically coupled to one or more conductive structures (1009 and 1011; col. 29, lines 30-40) in the second hybrid bond structure (1008 and 1010; col. 30, lines 1-15);
forming a conductive pad (see first pad right below 105 under 1124) in a second dielectric layer (dielectric layer of 1112; col. 27, lines 25-35) over the first dielectric layer (in 1012), wherein the conductive pad is coupled to the TSV (1124) (see Fig. 11A); and
forming a conductive bond bump structure (see bump below the conductive pad) on the conductive pad (see Fig. 11A),
in order to “reduce the planar chip size of the peripheral circuits, as well as the total chip size of the memory device” (col. 6, lines 60-65).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method for forming an integrated circuit (IC) of Cheng with the forming of dielectric layers and connections of Zhang in view of Sawada, in order to reduce the planar chip size of the peripheral circuits, as well as the total chip size of the memory device.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 20200350286) in view of Okina et al. (US 20200258816).
Regarding claim 25, Cheng teaches a method for forming an integrated circuit (IC) ([0016]-[0017] and [0019]), the method comprising:
forming a plurality of first semiconductor devices (604, Fig. 6A, [0084], memory stacks) on a first substrate (602), wherein the plurality of first semiconductor devices (604) predominately comprise a first type of IC device ([0084]) (see Fig. 6A);
forming a first interconnect structure (620) on the first substrate (602) (see Fig. 6B), wherein the first interconnect structure comprises a plurality of conductive wires (bottom layer of 620) vertically stacked with a plurality of conductive vias (vertical vias above the conductive wires) (see Fig. 6B);
forming a first hybrid bond structure (622, Fig. 6B, [0087]) on the first interconnect structure (620), wherein the first hybrid bond structure (622, labelled as 328 in Fig. 3A) comprises a first plurality of conductive bond structures (624, labelled as 330 in Fig. 3A) in a first bond dielectric structure ([0053]) (see Fig. 6B);
forming a plurality of second semiconductor devices (right two 504, Fig. 5A, [0081]) on a second substrate (502) (see Fig. 5A), wherein the plurality of second semiconductor devices (504) predominately comprise a second type of IC device ([0081], logic transistors) different from the first type of IC device;
forming a second interconnect structure (see Fig. 7B below, bottom portion of 512) on the second substrate (502) (see Fig. 5C);
forming a second hybrid bond structure (514 and top portion of 512 to the second interconnect structure, see Fig. 7B below; Figs. 5B-5C) on the second interconnect structure (bottom portion of 512), wherein the second hybrid bond structure comprises a second plurality of conductive bond structures (516) in a second bond dielectric structure (514, [0053]) and a routing structure (top portion of 512 to the second interconnect structure, see Fig. 7B below) between the second bond dielectric structure (514) and the second interconnect structure (bottom portion of 512), wherein the routing structure comprises a plurality of conductive routing structures in a dielectric structure (see Fig. 7B below; [0082]); and
bonding the first hybrid bond structure (622) to the second hybrid bond structure (514 and top portion of 512 to the second interconnect structure) (see Figs. 7A-7B), wherein a bond interface (702) is between the first hybrid bond structure (622) and the second hybrid bond structure, and wherein a first subset of the plurality of conductive routing structures (top interconnect line of 512 and right three vertical lines; see Fig. 7B below) electrically couples a first conductive bond structure (second to right 624) in the first plurality of conductive bond structures (624) to one of the second semiconductor devices (second to right 504) (see Fig. 7B).
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Partial view of Cheng Fig. 7B
Cheng does not teach that the first hybrid bond structure comprises a first plurality of conductive bond vias in a first bond dielectric structure, wherein the first plurality of conductive bond vias contact the first plurality of conductive bond structures and a topmost wire level of the plurality of conductive wires, wherein a height of the first plurality of conductive bond vias is greater than a height of the first plurality of conductive bond structures and a height of the topmost wire level.
In a similar field of endeavor, Okina teaches, in Fig. 16, that the first hybrid bond structure comprises a first plurality of conductive bond vias (784 directly contacting 788, [0113]) in a first bond dielectric structure (760, [0113]), wherein the first plurality of conductive bond vias (784) contact the first plurality of conductive bond structures (788, [0113]) and a topmost wire level of the plurality of conductive wires (layer directly underneath and contacting 784), wherein a height of the first plurality of conductive bond vias (784) is greater than a height of the first plurality of conductive bond structures (788) and a height of the topmost wire level (see Fig. 16), so that “[t]he memory die can be bonded to a logic die containing peripheral circuitry for supporting operations of memory cells within the memory die” (Abstract).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the first hybrid bond structure of Cheng with the conductive bond vias of Okina, so that the memory die can be bonded to a logic die containing peripheral circuitry for supporting operations of memory cells within the memory die (Abstract).
Claims 26 and 28-31 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 20200350286) in view of Okina et al. (US 20200258816), and further in view of Zhang et al. (US 12069854).
Regarding claim 26, Cheng in view of Okina teaches the limitations of claim 25. Cheng in view of Okina does not explicitly teach forming a plurality of third semiconductor devices predominately comprising a third type of IC device on the second substrate; and forming a plurality of fourth semiconductor devices predominately comprising a fourth type of IC device on the second substrate, wherein the third type of IC device and the fourth type of IC device are different from each other and the second type of IC device, and wherein the plurality of third semiconductor devices are spaced laterally between the plurality of second semiconductor devices and the plurality of fourth semiconductor devices.
In a similar field of endeavor, Zhang teaches, in Fig. 11A, forming a plurality of third semiconductor devices (1120) predominately comprising a third type of IC device (col. 28, lines 10-25; input/output) on the second substrate (1004); and
forming a plurality of fourth semiconductor devices (1108) predominately comprising a fourth type of IC device (col. 26; line 55 – col. 27, line 15; high voltage) on the second substrate (1004), wherein the third type of IC device and the fourth type of IC device are different from each other and the second type of IC device (1122; col. 28, lines 10-25; logic), and wherein the plurality of third semiconductor devices (1120) are spaced laterally between the plurality of second semiconductor devices (1122) and the plurality of fourth semiconductor devices (1108) (see Fig. 11A how 1120 are spaced laterally between the right side of 1122 and the top side of 1108),
in order to “reduce the planar chip size of the peripheral circuits, as well as the total chip size of the memory device” (col. 6, lines 60-65).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method for forming an integrated circuit (IC) of Cheng in view of Okina with the forming of a plurality of third semiconductor devices and a plurality of fourth semiconductor devices of Zhang, in order to reduce the planar chip size of the peripheral circuits, as well as the total chip size of the memory device.
Regarding claim 28, Cheng in view of Okina and Zhang teaches the limitations of claim 26. Zhang, in Fig. 11A, further teaches that a second subset (third from the right top interconnection line of 1126) of the plurality of conductive routing structures (top interconnection line of 1126) electrically couples a second conductive bond structure (middle 1009) in the first plurality of conductive bond structures (1009; col. 30, lines 5-10) to one of the third semiconductor devices (1120), and
that a third subset (second from the left vertical interconnection line of 1126) of the plurality of conductive routing structures (1126) electrically couples a third conductive bond structure (left 1009) in the first plurality of conductive bond structures (1009) to one of the fourth semiconductor devices (1108) (see Fig. 11A).
Regarding claim 29, Cheng in view of Okina and Zhang teaches the limitations of claim 28. Zhang further teaches, in Fig. 11A, that the first conductive bond structure (right 1009) is directly adjacent to the second conductive bond structure (middle 1009).
Regarding claim 30, Cheng in view of Okina and Zhang teaches the limitations of claim 29. Cheng further teaches, in Fig. 7B, that the first subset of the plurality of conductive routing structures comprises a lateral routing structure (top interconnect line of 512), and that a first portion of the lateral routing structure (third portion from the right) directly overlies the first conductive bond structure (second from the right 624) and a second portion of the lateral routing structure (leftmost portion of top interconnect line of 512) directly overlies the second conductive bond structure (third from the right 624).
Regarding claim 31, Cheng in view of Okina and Zhang teaches the limitations of claim 30. Cheng further teaches, in Fig. 7B, that the lateral routing structure (top interconnect line of 512) continuously laterally extends along a distance between a device region comprising the plurality of second semiconductor devices (right two 504) and another device region comprising the plurality of third semiconductor devices (left three 504) (see Fig. 7B).
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 20200350286) in view of Okina et al. (US 20200258816) and Zhang et al. (US 12069854), and further in view of Yokoyama et al. (US 20180240797).
Regarding claim 27, Cheng in view of Okina and Zhang teaches the limitations of claim 26. Okina further teaches, in Fig. 16, that the first type of IC device (710) is a logic device ([0111]).
Zhang further teaches, in Fig. 11A separately, that the third type of IC device (1120) is an input/output device (col. 28, lines 10-25), and the fourth type of IC device (1108) is a high voltage device (col. 26; line 55 – col. 27, line 15).
Cheng in view of Okina and Zhang does not explicitly teach that that the second type of IC device is a radio frequency device.
In a similar field of endeavor, Yokoyama teaches, in Figs. 28A and 29, that the second type of IC device (230A, Fig. 28A) (20, labeled in Fig. 3; Fig. 29) is a radio frequency device ([0072]-[0073], [0103]), in order to “provide a stacked body having a configuration suitable for easier manufacturing while reducing a mounting area” ([0008]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method for forming an integrated circuit (IC) of Cheng in view of Okina and Zhang with the second type of IC device, in order to provide a stacked body having a configuration suitable for easier manufacturing while reducing a mounting area.
Claims 33 and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 20200350286) in view of Sawada et al. (US 20220189905), and further in view of Seo et al. (US 20230138813).
Regarding claim 33, Cheng in view of Sawada teaches the limitations of claim 32. Sawada further teaches, in Fig. 19, that the first conductive structure (41, [0091]) comprises a lateral surface (side surface) elongated in a second direction (z-direction) substantially orthogonal to the first direction (x-direction) (see Fig. 19).
Cheng in view of Sawada does not explicitly teach that a length of the lateral surface of the first conductive structure in the second direction is greater than the length of the lateral surface of the second conductive structure in the first direction.
In a similar field of endeavor, Seo teaches, in Fig. 2B, that a length of the lateral surface of the first conductive structure (141) in the second direction (x-direction) is greater than the length of the lateral surface (bottom surface) of the second conductive structure (241) in the first direction (y-direction) ([0031], [0041]; The length of 141 in the x-direction is from about 3 μm to 20 μm, and the length of 241 in the y-direction is from about 2 μm to 3 μm), in order to “provide a semiconductor package having stacked semiconductor chips and increased operation reliability” ([0004]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method for forming an integrated circuit (IC) of Cheng in view of Sawada with the conductive structures of Seo, in order to provide a semiconductor package having stacked semiconductor chips and increased operation reliability.
Regarding claim 35, Cheng in view of Sawada and Seo teaches the limitations of claim 33. Seo further teaches, in Fig. 1, that a third conductive structure (rightmost 241) in the second plurality of conductive bond structures (241) is adjacent to the second conductive structure (241 in part A) and has a length (of the bottom surface) in the first direction (x-direction) substantially equal to the length (of the top surface) of the first conductive structure (141 in part A) in the first direction (see Fig. 1).
Claim 36 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 20200350286) in view of Sawada et al. (US 20220189905), and further in view of Sugisaki et al. (US 20200098776).
Regarding claim 36, Cheng in view of Sawada teaches the limitations of claim 34. Sawada further teaches, in Fig. 1, that a third conductive structure (second from the right 41) in the first plurality of conductive bond structures (41) contacts a fourth conductive structure (second from the right 38) in the second plurality of conductive bond structures (38), wherein a width (of bottom surface) of the third conductive structure (rightmost 41) is equal to a width (of top surface) of the fourth conductive structure (rightmost 38) (see Fig. 1).
Sawada does not explicitly teach that the width of the third conductive structure is less than the length of the lateral surface of the second conductive structure.
In a similar field of endeavor, Sugisaki teaches, in Fig. 18, that the width (of bottom surface) of the third conductive structure (second from the right top 37) is less than the length of the lateral surface (top surface) of the second conductive structure (rightmost bottom 37) [0117], so that multiple chips can be easily stacked by aligning any electrode pad located on the respective sides of the chips and “to increase the storage capacity of the semiconductor memory device” ([0120]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the conductive structure widths of Cheng in view of Sawada with the conductive structure widths of Sugisaki, so that multiple chips can be easily stacked by aligning any electrode pad located on the respective sides of the chips and to increase the storage capacity of the semiconductor memory device ([0120]).
Claim 39 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 20200350286) in view of Sawada et al. (US 20220189905), and further in view of Mizutani et al. (US 20220399358).
Regarding claim 39, Cheng in view of Sawada teaches the limitations of claim 17. Cheng in view of Sawada does not explicitly teach that in the first cross-sectional view a width of the lateral routing structure is equal to a width of the second conductive bond pad.
In a similar field of endeavor, Mizutani teaches, in Fig. 28, that in the first cross-sectional view (Fig. 28) a width (horizontal) of the lateral routing structure (780, [0123]) is equal to a width (horizontal) of the second conductive bond pad (788, [0123]), in order to “maximize the chip area for forming a three-dimensional memory array” ([0202]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the lateral routing structure and second conductive bond pad widths of Cheng in view of Sawada with the widths of Mizutani, in order to maximize the chip area for forming a three-dimensional memory array ([0202]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ERIKA H SON/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893