DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claim 1-25, & 38 in the reply filed on 04/14/25 is acknowledged.
Applicant's election with traverse of Species D (Figs. 6A-6B) in the reply filed on 04/14/25 is acknowledged. This traversal is found persuasive. Thereby claims 1-25 & 38 have been examined below.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 & 3-5 are rejected under 35 U.S.C. 102(a)(1) & (a)(2) as being anticipated by Do et al (US 2015/0279815)
Regarding claim 1, Do teaches A method, comprising:
forming a first insulating layer [fig. 6C, insulating layer 330, para 70] on a conductive interconnection layer [fig. 6C, conductive layers 324 & 326, para 70];
forming a first opening extending through the first insulating layer and reaching the conductive interconnection layer [fig. 6d, openings 332, para 71];
forming a conductive body within said first opening that is in electrical contact with said interconnection layer [fig. 6E, conductive layer 338, para 72];
covering said conductive body with a first coating layer [fig. 6F, insulating layer 340, para 73];
locally perforating the first coating layer with a testing apparatus to make electrical connection to the conductive body [fig. 6G, LDA (laser direct ablation) using laser 344, para 74];
carrying out an electrical test through the testing apparatus [wherein LDA (laser direct ablation) is a test process itself para 74];
after completion of the electrical test, forming a second opening [fig. 6G, opening 342, para 74] extending through the first coating layer and reaching the conductive body (338) [fig. 6G];
and forming a conductive pillar [fig. 6H, conductive layer 348, para 75] in electrical contact with the conductive body (338) and located within said second opening (342) [fig. 6H].
Regarding claim 3, Do teaches The method of claim 1,
wherein said first coating layer (340) is made of a material providing a protection against one or more of oxidation and corrosion of said conductive body (338) [para 73, “Insulating layer 340 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, BCB, PI, PBO, polymer dielectric resist with or without fillers or fibers, or other material having similar structural and dielectric properties.” Wherein material such as silicon dioxide protects against corrosion and oxidation].
Regarding claim 4, Do teaches The method of claim 1, wherein the first coating layer (340) a material selected from the group consisting of Aluminum and Hafnium [para 73, discloses layer 340 may comprise aluminum oxide].
Regarding claim 5, Do teaches The method of claim 1, wherein covering with the first coating layer comprises performing one among:
a thermal atomic layer deposition, a plasma-assisted atomic layer deposition, and a plasma enhanced chemical vapor deposition [para 73, wherein plasma enhanced chemical vapor deposition is a type of CVD (chemical vapor deposition].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2 is rejected under 35 U.S.C. 103 as being unpatentable over Do et al (US 2015/0279815) as applied to claims 1 & 3-5 above, and further in view of Ishihara et al. (US 2019/0355516) [Hereinafter Ishihara]
Regarding claim 2, Do teaches The method of claim 1.
Do fails to explicitly disclose wherein said first coating layer (340) has a thickness less than 100 nm.
However, Ishihara teaches a dielectric layer (5) wherein, “The thickness of the dielectric layer is not particularly limited, and for example, preferably 3 nm or more and 100 nm or less, and more preferably 5 nm or more and 50 nm or less. When the dielectric layer has a thickness of 3 nm or more, the insulating property can be enhanced, which makes it possible to reduce leakage current.”
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the thickness of the first coating layer to be less than 100nm to enhance the insulating property and reduce leakage current ultimately preventing dielectric breakdown. Moreover, In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists.
Claim(s) 6 & 18 are rejected under 35 U.S.C. 103 as being unpatentable over Do et al (US 2015/0279815) as applied to claims 1 & 3-5 above, and further in view of Shioga et al. (US 2007/0176175) [Hereinafter Shioga]
Regarding claim 6, Do teaches The method of claim 1, further comprising:
forming a second insulating layer [fig. 6I, insulating layer 352, para 76] around and partially above the first coating layer [fig. 6I wherein the second insulating layer is around and above];
forming a third opening [fig. 6K, opening 364, para 79] extending through the second insulating layer (352).
Do fails to explicitly disclose forming a third opening extending through the second insulating layer to expose a surface portion of the first coating layer;
wherein forming said second opening extending through the first coating layer comprises forming the second opening through said third opening; and
wherein forming said conductive pillar located within said second opening comprises passing the conductive pillar through the second opening and said third opening.
Shioga teaches forming a third opening [fig. 2G, opening 20, para 52] extending through the second insulating layer [fig. 2G, polyimide film 19, para 66] to expose a surface portion of the first coating layer [fig. 2G, silicon nitride film 18, para 52];
wherein forming said second opening [fig. 2G opening 22, para 66] extending through the first coating layer (18) comprises forming the second opening(22) through said third opening(20) [fig. 2G]; and
wherein forming said conductive pillar [fig. 2H, Ni plating layer 26, para 53] located within said second opening (opening 22) comprises passing the conductive pillar (26) through the second opening (22) and said third opening (20) [fig. 2H].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the modified invention of Do to comprise the teachings of Shioga to form under-bump metallization (UBM) to provide reliable and robust electrical connections between layers.
Regarding claim 18, Do teaches The method of claim 17, further comprising, after having locally perforated the first coating layer:
forming one or more second insulating layers around and partially above the first coating layer [fig. 6I, insulating layer 352, para 76];
forming respective one or more second openings extending through the one or more second insulating layers [fig. 6K, opening 364, para 79] to expose a surface portion of the first coating layer;
forming a third opening [fig. 6G, opening 342, para 74] extending through the first coating layer (340) to expose a respective surface portion of the conductive body (338) [fig. 6G]; and
forming a conductive pillar [fig. 6H, conductive layer 348, para 75] in electrical contact with the conductive body (338) and located within said one or more second openings (364, fig. 6K) and said third opening (fig. 6G-6H, 342).
Do fails to explicitly disclose forming respective one or more second openings extending through the one or more second insulating layers to expose a surface portion of the first coating layer;
Shioga teaches forming an opening [fig. 2G, opening 20, para 52] extending through the second insulating layer [fig. 2G, polyimide film 19, para 66] to expose a surface portion of the first coating layer [fig. 2G, silicon nitride film 18, para 52];
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the modified invention of Do to comprise the teachings of Shioga to provide reliable and robust electrical connections between layers.
Claim(s) 7 is rejected under 35 U.S.C. 103 as being unpatentable over Do et al (US 2015/0279815) & Shioga et al. (US 2007/0176175) as applied to claims 6 above, and further in view of Kitazaki et al. (US 2015/0070851) [Hereinafter Kitazaki]
Regarding claim 7, Do teaches The method of claim 6,
wherein forming the second insulating layer (352) comprises:
[para 76] “Insulating layer 352 contains one or more layers of solder resist, SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties.”
Do fails to explicitly disclose wherein forming the second insulating layer (352) comprises:
forming a photosensitive insulating layer around and partially above the first coating layer;
forming a molding layer on the photosensitive insulating layer;
and
wherein forming said third opening (364) comprises extending the third opening through the photosensitive insulating layer and the molding layer.
Kitazaki teaches wherein a sealing (mold) layer [fig. 2, sealing layer 4, para 71] includes insulating resin to which silica (silicon dioxide) is added wherein the sealing layer (4) is formed by a molding method. Furthermore, Kitazaki teaches in para 67, wherein solder resist is known as a photosensitive resin material.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the second insulating layer (352) to comprise exemplary materials silicon dioxide (mold layer) and solder resist (a photosensitive insulating layer) wherein the opening (364) extends through. Thereby enabling miniaturization, superior adhesion, and enhanced electrical properties for high-speed and high-density applications.
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over Do et al (US 2015/0279815) & Shioga et al. (US 2007/0176175) as applied to claims 6 above, and further in view of Kim et al. (US 9659910) [Hereinafter Kim]
Regarding claim 8, Do teaches The method of claim 6,
wherein forming the second insulating layer (352) comprises
[para 76] “Insulating layer 352 contains one or more layers of solder resist, SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties.”
Do fails to explicitly disclose wherein forming the second insulating layer (352) comprises
forming a photosensitive insulating layer made of a material selected from the group consisting of: polyimide, PBO, Epoxy, and photosensitive organic material.
Kim teaches a dielectric layer [fig. 1, dielectric layer 1130, para 16] comprises of a photosensitive organic material such as solder resist.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the second insulation layer (352) to comprise solder resist as taught by Do which is a photosensitive organic material as taught by Kim. Thereby enabling accurate patterning for intricate designs and enhanced reliability due to improved electrical properties.
Claim(s) 9-10, 12, & 14 are rejected under 35 U.S.C. 103 as being unpatentable over Do et al (US 2015/0279815).
Regarding claim 9, Do teaches The method of claim 1.
Do fails to teach in fig. 6F further comprising covering the first coating layer with a second coating layer
and, before locally perforating the first coating layer, removing selective portions of the second coating layer above the location where said step of locally perforating is to be carried out.
However, Do teaches in para 73 “insulating layer 340 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, BCB, PI, PBO, polymer dielectric resist with or without fillers or fibers, or other material having similar structural and dielectric properties.” Furthermore, Do discloses in fig. 6G wherein the insulating layer 340 is selectively removed where said step of locally perforating is to be carried out.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for a layer 340 to comprise a second coating layer wherein a portion of the first & second coating layer are selectively removed prior to said step of locally perforating is to be carried out as shown in fig. 6G. to increase dielectric strength thereby improving reliability.
Regarding claim 10, Do teaches The method of claim 9,
wherein the second coating layer is made of a material configured to sustain temperatures up to 300 °C without damages [para 73 provides exemplary materials such as silicon dioxide which carries a melting point of 1650 degrees Celsius. Thereby no damage would be present at 300 degrees Celsius].
Regarding claim 12, Do teaches The method of claim 9,
wherein the second coating layer is made of a dielectric or insulating material selected from the group consisting of: Silicon Nitride, Silicon Carbon Nitride, Silicon Oxycarbide, and Silicon Oxide [para 73, “Insulating layer 340 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, BCB, PI, PBO, polymer dielectric resist with or without fillers or fibers, or other material having similar structural and dielectric properties.” ].
Regarding claim 14, Do teaches The method of claim 9,
further comprising forming a second insulating layer [fig. 6I, insulating layer 352, para 76] around and partially above the first coating layer [wherein the insulating layer 340 comprises the first & second coating layer] and further on, and in direct contact with, said second coating layer [wherein based upon claim 9 rejection the second coating layer is on top of the first coating layer thereby, the top portion of layer 340 is in direct contact with the second insulating layer (352)].
Claim(s) 11 is rejected under 35 U.S.C. 103 as being unpatentable over Do et al (US 2015/0279815) as applied to claim 9-10, 12, & 14 and further in view of Liujiang et al. (CN 102420172) [Hereinafter Liujiang].
Regarding claim 11, Do teaches The method of claim 9, wherein the second coating layer (second layer of 340) is made of silicon dioxide [para 73].
Do fails to explicitly disclose the thermal coefficient of thermal expansion of silicon dioxide is in a range of 0.5 x 10-6 to 6.0 x 10-6 /K
Liujiang teaches, “the thermal expansion coefficient of silica is about 0.5 × 10-6/ K
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the second coating layer to comprise silicon dioxide with a thermal coefficient of thermal expansion of about 0.5 × 10-6/ K which provides high thermal shock resistance. Moreover, In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists.
Claim(s) 13, 15-17, 21, & 38 are rejected under 35 U.S.C. 103 as being unpatentable over Do et al (US 2015/0279815) as applied to claim 9-10, 12, & 14 and further in view of Ishihara et al. (US 2019/0355516) [Hereinafter Ishihara]
Regarding claim 13, Do teaches The method of claim 9.
Do fails to explicitly disclose wherein the second coating layer has a thickness in a range of 0.01 µm (10nm) to 1 µm (1000 nm).
However, Ishihara teaches a dielectric (coating) layer (5) wherein, “The thickness of the dielectric layer is not particularly limited, and for example, preferably 3 nm or more and 100 nm or less, and more preferably 5 nm or more and 50 nm or less. When the dielectric layer has a thickness of 3 nm or more, the insulating property can be enhanced, which makes it possible to reduce leakage current.”
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the thickness of the coating layer to be less than 100nm to enhance the insulating property and reduce leakage current ultimately preventing dielectric breakdown. Moreover, In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists.
Regarding claim 15, Do teaches A method, comprising:
forming a first insulating layer [fig. 6C, insulating layer 330, para 70] on a last metal line of a conductive interconnection for an integrated circuit [fig. 6C, conductive layers 324 & 326, para 70];
forming a first opening [fig. 6D, openings 332, para 71]; extending through the first insulating layer and reaching an upper surface of the last metal line for the conductive interconnection[fig. 6D];
forming a conductive body of a redistribution layer within said first opening that is in electrical contact with said last metal line for the conductive interconnection [fig. 6E, conductive layer 338, para 72]; and
covering said conductive body with a first coating layer [fig. 6F, insulating layer 340, para 73];,
said first coating layer (340) configured to provide a protection against one or more of oxidation and corrosion of said conductive body [para 73, “Insulating layer 340 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, BCB, PI, PBO, polymer dielectric resist with or without fillers or fibers, or other material having similar structural and dielectric properties.” Wherein material such as silicon dioxide protects against corrosion and oxidation].
Do fails to explicitly disclose a first coating layer (340) having a thickness less than 100nm.
However, Ishihara teaches a dielectric (coating) layer (5) wherein, “The thickness of the dielectric layer is not particularly limited, and for example, preferably 3 nm or more and 100 nm or less, and more preferably 5 nm or more and 50 nm or less. When the dielectric layer has a thickness of 3 nm or more, the insulating property can be enhanced, which makes it possible to reduce leakage current.”
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the thickness of the coating layer to be less than 100nm to enhance the insulating property and reduce leakage current ultimately preventing dielectric breakdown. Moreover, In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists.
Regarding claim 16, Do teaches The method of claim 15,
wherein the first coating layer (340) comprises a material selected from the group consisting of Aluminum and Hafnium [para 73, discloses layer 340 may comprise aluminum oxide].
Regarding claim 17, Do teaches The method of claim 15, further comprising:
locally perforating the first coating layer with a testing probe or testing tip until the conductive body is electrically contacted by said testing probe or testing tip [fig. 6G, LDA (laser direct ablation) using laser 344, para 74]; and
carrying out an electrical test of the integrated circuit through said testing probe or testing tip [wherein LDA (laser direct ablation) is a test process itself para 74].
Regarding claim 21, Do teaches The method of claim 17,
wherein forming the first coating layer comprises forming a dielectric or insulating layer [para 73, states the first coating layer (340) is an insulation or dielectric layer],
Do fails to teach in fig. 6F and further comprising: completely covering the first coating layer with a second coating layer
and, before locally perforating the first coating layer, removing selective portions of the second coating layer above the location where said step of locally perforating is to be carried out.
However, Do teaches in para 73 “insulating layer 340 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, BCB, PI, PBO, polymer dielectric resist with or without fillers or fibers, or other material having similar structural and dielectric properties.” Furthermore, Do discloses in fig. 6G wherein the insulating layer 340 is selectively removed where said step of locally perforating is to be carried out.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for a layer 340 to comprise a second coating layer wherein a portion of the first & second coating layer are selectively removed prior to said step of locally perforating is to be carried out as shown in fig. 6G. to increase dielectric strength thereby improving reliability.
Regarding claim 38, The method of claim 15,
wherein said conductive interconnection is formed by a stack of metal layers for a back end of line (BEOL) of the integrated circuit that includes the last metal line in an upper most one of the metal layers in the stack
Do teaches fig. 6I, wherein the conductive interconnection (324 & 326) is a metal stack as noted in para 68 & 69, and wherein layer 326 is the last upper most metal line in the metal stack. Furthermore fig. 6L & 7 illustrates the conductive column substrate 370 to be that of a back end of line (BEOL) of the integrated circuit.
Claim(s) 19 is rejected under 35 U.S.C. 103 as being unpatentable over Do et al (US 2015/0279815) & Shioga et al. (US 2007/0176175) as applied to claims 6 & 18 above, and further in view of Kitazaki et al. (US 2015/0070851) & Kim et al. (US 2017/0373041) [Hereinafter Kim_2017]
Regarding claim 19, Do teaches The method of claim 18, wherein forming one or more second insulating layers includes:
[para 76] “Insulating layer 352 contains one or more layers of solder resist, SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties.” Furthermore Fig. 6K illustrates the second opening (364) extending through the second insulating layer (352).
Do fails to explicitly disclose wherein forming a photosensitive insulating layer around and partially above the first coating layer;
forming a molding layer on the photosensitive insulating layer; and
wherein forming said second openings comprises extending the second openings through the photosensitive insulating layer and the molding layer.
Kitazaki teaches wherein a sealing (mold) layer [fig. 2, sealing layer 4, para 71] includes insulating resin to which silica (silicon dioxide) is added wherein the sealing layer (4) is formed by a molding method. Furthermore, Kitazaki teaches in para 67, wherein solder resist is known as a photosensitive resin material.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the second insulating layer (352) to comprise exemplary materials silicon dioxide (mold layer) and solder resist (a photosensitive insulating layer) wherein the opening (364) extends through. Thereby enabling miniaturization, superior adhesion, and enhanced electrical properties for high-speed and high-density applications.
Kim_2017 teaches wherein a photosensitive insulating layer [fig. 8, photosensitive dielectric layer 700, para 44] is formed on a mold layer [fig. 8, 200T/300, para 44] thereby preventing contamination of the device.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the photosensitive insulating layer to be formed on a mold layer thereby preventing contamination within the device as taught by Kim_2017.
Claim(s) 20 is rejected under 35 U.S.C. 103 as being unpatentable over Do et al (US 2015/0279815), Shioga et al. (US 2007/0176175), Kitazaki et al. (US 2015/0070851), & Kim et al. (US 2017/0373041) as applied to claims 19 above, and further in view of Kim et al. (US 9659910)
Regarding claim 20, Do teaches The method of claim 19,
wherein forming the second insulating layer (352) comprises
[para 76] “Insulating layer 352 contains one or more layers of solder resist, SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties.”. Furthermore, the second insulating layer (352) is around and above the first coating layer (340).
Do fails to explicitly disclose further comprising forming a photosensitive insulating layer around and partially above the first coating layer (340), wherein said photosensitive insulating layer is made of a material selected from the group consisting of: polyimide, PBO, epoxy, and photosensitive organic material.
Kim teaches a dielectric layer [fig. 1, dielectric layer 1130, para 16] comprises of a photosensitive organic material such as solder resist.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the second insulation layer (352) to comprise solder resist as taught by Do which is a photosensitive organic material as taught by Kim. Thereby enabling accurate patterning for intricate designs and enhanced reliability due to enhanced electrical properties.
Claim(s) 22 is rejected under 35 U.S.C. 103 as being unpatentable over Do et al (US 2015/0279815) & Ishihara et al. (US 2019/0355516) as applied to claim 13, 15-17, 21, & 38 and further in view of Kim et al. (US 9659910) [Hereinafter Kim]
Regarding claim 22, Do teaches The method of claim 17.
Do fails to explicitly teach completely covering the first coating layer with a second coating layer;
forming a photosensitive insulating layer around and partially above the first coating layer,
wherein forming the photosensitive insulating layer includes forming a photosensitive insulating layer on and in direct contact with said second coating layer.
However, Do teaches in para 73 “insulating layer 340 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, BCB, PI, PBO, polymer dielectric resist with or without fillers or fibers, or other material having similar structural and dielectric properties.” Furthermore [Fig. 6I, para 76] Do teaches insulating layer 352 to comprise “one or more layers of solder resist, SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties.”
Kim teaches a dielectric layer [fig. 1, dielectric layer 1130, para 16] comprises of a photosensitive organic material such as solder resist.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the second insulation layer (352) to comprise solder resist as taught by Do which is a photosensitive organic material as taught by Kim in direct contact with said second coating layer of layer 340. Thereby enabling accurate patterning for intricate designs and enhanced reliability due to enhanced electrical properties.
Claim(s) 23-25 is rejected under 35 U.S.C. 103 as being unpatentable over Do et al (US 2015/0279815) & Ishihara et al. (US 2019/0355516) as applied to claim 13, 15-17, 21, & 38 and further in view of Liujiang et al. (CN 102420172) [Hereinafter Liujiang].
Regarding claim 23, The method of claim 15, further comprising
completely covering the first coating layer with a second coating layer having a coefficient of thermal expansion in the range of 0.5 x 10-6 to 6.0 x 10-6 1/K
Do teaches wherein the second coating layer (second layer of 340) is made of material such as silicon dioxide [para 73].
Liujiang teaches, “the thermal expansion coefficient of silica is about 0.5 × 10-6/ K
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the second coating layer to comprise silicon dioxide with a thermal coefficient of thermal expansion of about 0.5 × 10-6/ K which provides high thermal shock resistance. Moreover, In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists.
Regarding claim 24, Do teaches The method of claim 23,
wherein the second coating layer is made of a dielectric or insulating material selected from the group consisting of: Silicon Nitride, Silicon Carbon Nitride, Silicon Oxycarbide, and Silicon Oxide [para 73, “Insulating layer 340 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, BCB, PI, PBO, polymer dielectric resist with or without fillers or fibers, or other material having similar structural and dielectric properties.” ].
Regarding claim 25, Do teaches The method of claim 23, further comprising
forming one or more second insulating layers [fig. 6I, insulating layer 352, para 76] around and partially above the first coating layer [fig. 6I wherein the one or more second insulating layers are around and above the first coating layer of 340],
wherein forming one or more second insulating layers (352) includes
forming said one or more second insulating layers on (352), and in direct contact with, said second coating layer (340) [wherein the second coating layer of 340 is on top of the first coating layer. Thereby fig. 6I illustrates direct contact of layer 352 and top surface of 340].
Conclusion
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/FELIX B ANDREWS/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812