Prosecution Insights
Last updated: July 17, 2026
Application No. 17/751,025

DISPLAY DEVICE AND METHOD OF MANUFACTURING THE DISPLAY DEVICE

Final Rejection §103
Filed
May 23, 2022
Priority
Oct 27, 2021 — RE 10-2021-0144873
Examiner
PURVIS, SUE A
Art Unit
2800
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Display Co., Ltd.
OA Round
2 (Final)
65%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
82%
With Interview

Examiner Intelligence

Grants 65% — above average
65%
Career Allowance Rate
52 granted / 80 resolved
-3.0% vs TC avg
Strong +17% interview lift
Without
With
+16.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
16 currently pending
Career history
111
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
66.3%
+26.3% vs TC avg
§102
15.3%
-24.7% vs TC avg
§112
14.6%
-25.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 80 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 2, and 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2019/0121176) in view of Jang (US 2019/0377119). Lee discloses display device comprising: pixels (See Fig. 13, PX1, PX2, PX3); a bank (BM, [0029], Fig. 1) including an opening overlapping each of the pixels in a plan view (Fig. 13); light emitting elements (940, [0122]) disposed in the pixels; a color conversion layer (321a/321b, [0041]) disposed on the light emitting elements (940) in the opening of the bank (BM); and an optical layer (400b, [0029]) disposed on the color conversion layer (321a/321b) in the opening of the bank, wherein the optical layer (400b) includes an organic layer ([0062], [0064]) surrounding voids (H, holes, see Fig. 3, [0059]) of the optical layer (400b), and Lee does not disclose that the voids are formed without hollow particles. Jang discloses a display device with a matrix with voids and no particles. As shown in FIG. 4, the low refractive index layer (20) comprising the matrix MX and the void VD does not have particles ([0053]). It would have been obvious to modify Lee’s low refractive index optical layer to form the voids without hollow particles, as taught by Jang, in order to simplify manufacture while maintaining low refractive index and light recycling performance. Regarding claim 2, Lee in view of Jang discloses the display device of claim 1, wherein the optical layer (400b) has a refractive index of about 1.25 or less (Lee [0056]). Jang also discusses a low refractive index. It would have been obvious to form Lee’s low-index layer as the void-containing, particle-free structure of Jang to simplify fabrication while maintaining low refractive index behavior. Regarding claim 4, Lee in view of Jang discloses the display device of claim 1, wherein the voids of the optical layer have different diameters (Lee Fig. 3 or Jang Fig.4). Regarding claim 5, Lee in view of Jang discloses the display device of claim 1, wherein each of the voids of the optical layer has a diameter in a range of about 2 nm to about 150 nm ([0061]). Regarding claim 6, Lee in view of Jang discloses the display device of claim 1, wherein: the pixels include first pixels (PX1), second pixels (PX2), and third pixels (PX3), and the optical layer (400b) includes a first optical layer, a second optical layer, and a third optical layer of the first pixels, the second pixels, and the third pixels that are separated from each other (i.e., the optical layers 400b of the first, second and third pixels are separated from each other by bank members BM disposed therebetween). Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2019/0064602) in view of Jang (US 2019/0377119). Kim discloses display device comprising (Fig. 6): pixels (Fig. 5, 191, [0130]); a bank ([0140]) including an opening overlapping each of the pixels in a plan view; light emitting elements (470, [0143]) disposed in the pixels; a color conversion layer (330R/330G/330B, [0034]) disposed on the light emitting elements in the opening of the bank; and an optical layer (327, [0067]) disposed on the color conversion layer in the opening of the bank, wherein the optical layer (327) includes an organic layer surrounding voids of the optical layer (i.e., “the first buffer layer 327 may include the organic material including at least one among hollow silica, a pore derivative (porogen)”, [0070]). Kim does not disclose that the voids are formed without hollow particles. Jang discloses a display device with a matrix with voids and no particles. As shown in FIG. 4, the low refractive index layer (20) comprising the matrix MX and the void VD does not have particles ([0053]). It would have been obvious to modify the porous low refractive index buffer layer of Kim to include voids formed without hollow particles as taught by Jang, in order to maintain a low refractive index and total internal reflection while simplifying the layer structure and improving light recycling efficiency. Regarding claim 2, Kim in view of Jang discloses the display device of claim 1, wherein the optical layer (327) has a refractive index of about 1.25 or less (Kim [0067]). Jang also discusses a low refractive index. It would have been obvious to form Lee’s low-index layer as the void-containing, particle-free structure of Jang to simplify fabrication while maintaining low refractive index behavior. Regarding claim 3, Kim in view of Jang discloses display device of claim 1, wherein the optical layer (327) has a thickness in a range of about 0.2 µm to about 3.0 µm (Kim, [0074]). Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Jang as applied to claim 1 above, and further in view of Lee. Regarding claim 7, Kim in view of Jang discloses the display device of claim 1. Lee discloses a first capping layer (CL, [0104]) disposed between the color conversion layer (321a/321b, [0114]) and the optical layer (400b, [0137]). Lee also discloses a second capping layer (CL) overlapping the optical layer (400b) in a plan view. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim in view of Jang by forming the first and second cap layer with the arrangements as set forth above, in order to prevent an increase in the refractive indices of the low refractive layer, as taught by Lee ([0104]). Regarding claim 9, Kim in view of Jang and Lee discloses the display device of claim 8, wherein Lee’s second capping layer (CL) contacts the first capping layer (CL). Therefore, Kim in view of Jang as modified by Lee’s Fig. 11 from forming the first and second cap layers surrounding top, bottom and side surfaces of each of the color conversion layers, Kim’s Fig. 6 also discloses the second capping layer contacts the first capping layer on the bank. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Jang as applied to claim 1, further in view of Kim ‘946 (US 2020/0258946). Kim (Fig. 6) in view Jang discloses the light emitting elements (470), but Kim does not disclose the light emitting elements each include: a first semiconductor layer; a second semiconductor layer disposed on the first semiconductor layer; and an active layer disposed between the first semiconductor layer and the second semiconductor layer. However, Kim ‘946 (Figs. 4-5) teaches a display device comprising the light emitting elements (320, [0079]) each include: a first semiconductor layer (HTL1, [0079]); a second semiconductor layer (ETL1, [0079]) disposed on the first semiconductor layer; and an active layer (EL11, light emitting layer, [0079]) disposed between the first semiconductor layer HTL1 and the second semiconductor layer ETL1. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the light emitting elements of Kim in view of Jang to each include: a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer in order to form a known OLED that would emit light through excitons formed by holes and electrons in the first and second semiconductor layers. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Jang in view of Kim et al (US 2020/0258946). Lee (Fig. 13) discloses the light emitting elements (940), but Lee does not disclose the light emitting elements each include: a first semiconductor layer; a second semiconductor layer disposed on the first semiconductor layer; and an active layer disposed between the first semiconductor layer and the second semiconductor layer. However, Kim ‘946 (Figs. 4-5) teaches a display device comprising the light emitting elements (320, [0079]) each include: a first semiconductor layer (HTL1, [0079]); a second semiconductor layer (ETL1, [0079]) disposed on the first semiconductor layer; and an active layer (EL11, light emitting layer, [0079]) disposed between the first semiconductor layer HTL1 and the second semiconductor layer ETL1. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the light emitting elements of Lee in view of Jang each include: a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer in order to form a known OLED that would emit light through excitons formed by holes and electrons in the first and second semiconductor layers. Response to Arguments Applicant’s arguments with respect to claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUE A PURVIS whose telephone number is (571)272-1236. The examiner can normally be reached M-F 0830 to 1630. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

May 23, 2022
Application Filed
Sep 04, 2025
Non-Final Rejection mailed — §103
Nov 03, 2025
Response Filed
Jun 22, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
65%
Grant Probability
82%
With Interview (+16.9%)
3y 4m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 80 resolved cases by this examiner. Grant probability derived from career allowance rate.

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