Prosecution Insights
Last updated: April 19, 2026
Application No. 17/751,340

SEMICONDUCTOR STRUCTURE INCLUDING SEMICONDUCTOR DEVICES WITH DIFFERENT THRESHOLD VOLTAGES AND METHOD FOR MANUFACTURING THE SAME

Non-Final OA §103
Filed
May 23, 2022
Examiner
SABUR, ALIA
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
3 (Non-Final)
74%
Grant Probability
Favorable
3-4
OA Rounds
2y 5m
To Grant
83%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allow Rate
424 granted / 571 resolved
+6.3% vs TC avg
Moderate +8% lift
Without
With
+8.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
44 currently pending
Career history
615
Total Applications
across all art units

Statute-Specific Performance

§101
1.5%
-38.5% vs TC avg
§103
59.3%
+19.3% vs TC avg
§102
14.7%
-25.3% vs TC avg
§112
18.7%
-21.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 571 resolved cases

Office Action

§103
DETAILED ACTION Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 18-19, 22, and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Bao (U.S. PGPub 2023/0261074) in view of Yang (U.S. PGPub 2022/0254640). Regarding claim 18, Bao teaches a method for manufacturing a semiconductor structure, comprising: forming two patterned structures which include two channel layers, respectively, forming two interfacial layers respectively on the two channel layers, each of the two interfacial layers including an insulating material, forming two gate dielectric layers respectively over the two interfacial layers, forming two gate electrodes respectively on the two gate dielectric layers (Fig. 11, Fig. 14, channel layer 115, interfacial layer 120, gate dielectric 125, [0035], [0045], gate electrode 240, [0048]), and before forming the two gate electrodes, introducing dipole elements into the two interfacial layers so as to permit a first atomic concentration of the dipole elements in one of the two interfacial layers to be different from a second atomic concentration of the dipole elements in another one of the two interfacial layers ([0045]-[0046]). Bao does not explicitly teach wherein the dipole elements include zinc. Yang teaches introducing a dipole element into a gate dielectric layer, where the dipole element may be zinc ([0024], [0041], [0049]). Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Yang with Bao such that the dipole elements include zinc because the prior art teaches an element which differs from the claim by substitution with a different element, the claimed element is known in the art, a person of ordinary skill could have substituted one known element for another, and the combination would have yielded predictable results to one of ordinary skill in the art before the time of the invention. See MPEP 2143.I.B. Regarding claim 19, the combination of Bao and Yang teaches wherein the two gate electrodes are formed simultaneously and have a same thickness (Bao, Fig. 14, [0048], [0034]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Bao and Yang for the reasons set forth in the rejection of claim 18. Regarding claim 22, the combination of Bao and Yang teaches wherein the two gate electrodes have a same material (Bao, [0048]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Bao and Yang for the reasons set forth in the rejection of claim 18. Regarding claim 29, the combination of Bao and Yang teaches forming first gate dielectric layers respectively on the first interfacial layers, forming second gate dielectric layers respectively on the second interfacial layers (Bao, Fig. 2, structures D2/D3/D4, channel layers 115, interfacial layers 120, gate dielectrics 125, [0035], [0045]), forming a first gate electrode on the first gate dielectric layers to fill a space between two adjacent ones of the first channel layers, forming a second gate electrode on the second gate dielectric layers to fill a space between two adjacent ones of the second channel layers (Bao, Fig. 14, gate electrodes 240, [0048]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Bao and Yang for the reasons set forth in the rejection of claim 18. Allowable Subject Matter Claims 6-7, 9-12, 14-15, 23, 25-28, and 30-31 are allowed. Reasons for allowance can be found in the Office action dated 11/28/25 and remain valid. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. PGPub 2016/0148846 teaches where zinc is used as a dipole element ([0117]). Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALIA SABUR whose telephone number is (571)270-7219. The examiner can normally be reached M-F 9:30-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALIA SABUR/ Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

May 23, 2022
Application Filed
Jun 13, 2025
Non-Final Rejection — §103
Sep 16, 2025
Response Filed
Nov 24, 2025
Final Rejection — §103
Jan 28, 2026
Response after Non-Final Action
Feb 12, 2026
Request for Continued Examination
Feb 23, 2026
Response after Non-Final Action
Mar 06, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604633
DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME
2y 5m to grant Granted Apr 14, 2026
Patent 12598899
DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME
2y 5m to grant Granted Apr 07, 2026
Patent 12593602
DISPLAY PANEL, MANUFACTURING METHOD AND ELECTRONIC DEVICE
2y 5m to grant Granted Mar 31, 2026
Patent 12588243
SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME
2y 5m to grant Granted Mar 24, 2026
Patent 12575268
DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME
2y 5m to grant Granted Mar 10, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
74%
Grant Probability
83%
With Interview (+8.4%)
2y 5m
Median Time to Grant
High
PTA Risk
Based on 571 resolved cases by this examiner. Grant probability derived from career allow rate.

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