Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s Amendment filed 01/13/2026 has been accepted and is being considered. Claims 14,16,18,19, 21-24, and 26-28 are amended. No new matter has been added with these amendments.
Response to Arguments
Applicant’s Amendments to the independent claims 14, 21, and 28 have changed the scope of the claims and the scope of their corresponding dependent claims so as to distinguish from the scope of the prior art referenced in the 35 USC 103 rejections furnished in the prior office action. As such, these rejections are withdrawn.
Regarding the arguments directed towards the instant invention’s “non-obvious advantage in that they [newly amended features] allow easier patterning of the fin structures by suppressing etching residue between adjacent fin structures”, this is taken as attorney argument – assertions of non-obvious (superior and unexpected) results/advantages are best supported with experimental data and the instant specification appears to provide no experimental embodiments and/or data concerning such.
After further search and consideration, however, the Examiner makes a new grounds of rejection over 35 USC 103 as set forth in the body of the action below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 14-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liou et al (US 9324570 B1), Sung et al (US 9991131 B1, dated 06/05/2018) and Tsujita (US 2016026639 A1).
Regarding Claim 14 and 18, Liou discloses a method of manufacturing a semiconductor device, wherein a substrate 102 is provided (more specifically, the substrate includes a semiconductor layer 104 as part of the assembly – 102 and 104 taken together are considered ‘the substrate’ as claimed) , a hard mask 106 is disposed thereatop, and a sacrificial layer 110 is formed atop the hard mask layer 106. A dummy layer 112 (second hard mask layer as claimed) is formed on the sacrificial layer 110, after which a first photomask 114 is used to form a plurality of transitional masks 116a and mandrel masks 116b, where the mandrel masks 116b have a smaller line width than the transitional masks 116a. The photomasks are produced from a photoresist composition layer that may be patterned.
An etching process is used to pattern the sacrificial layer 110 and dummy layer 112 using the mandrel and transitional masks 116b and 116a to define the etched pattern and produce a sacrificial pattern defined as 110a or 110b depending on the overlying transitional mask 116a or mandrel mask 116b and 112a/112b layer regions (110a and 110b define sacrificial pattern(s) as claimed). A spacer layer 118 is then formed and patterned to form sidewall patterns for the dummy patterns 11a and 112b. The second hard mask pattern is removed. An additional hard mask 122 may be disposed over the mandrel and transitional mask layers 116 a and 116b (claim 18). The first hard mask (106) is patterned using the remaining portion of the second hard mask pattern as a mask, thus forming a third hard mask pattern (106b), after which the substrate (the assembly of 102+104) is patterned using the 106b pattern as a mask to form a fin structure 104b and additional feature structures 104a.
Mask layers are described in Col 3 Lines 13-20 as being oxide or nitride materials.
Liou discloses the limitations of the claims as discussed above regarding claim 14, however does not teach a specific numerical/measured spacing parameter(s) between dummy hard mask and active hard mask patterns – the spacings of Liou are visually provided but no measurements corresponding thereto are present.
This limitation is met by Sung.
Sung teaches a double masking process for forming semiconductor film arrays having controlled and variable fin pitch within different arrays, using a top mandrel layer overlaying a bottom mandrel layer, where sidewall structures are formed on first mandrels to define a patterned hard mask in tandem with a photoresist layer over a second region of the substrate so as to define second mandrels.
The pitch of the fin structures here may be d1 through d4, where d1, d2, d3, and d4 may each be independently ranging from 20 to 100 nm though smaller and larger pitch values are contemplated. The fin structures themselves have a line width ranging from 5-20nm. The substrate surface may have dimensions such as a diameter ranging from 50-450 mm. The specification allows for a pitch d1 and d2 (S1 and S2) where d1 is smaller than d2. See Columns 3-4.
Sung discloses that the variable fin spacing improves FinFET performance by allowing for improved electrostatic control of the device, such as when gates are wrapped around the raised channel presented by the fin (Background).
Neither Liou nor Sung teach a specific resolution limit of a lithography apparatus used in patterning structures and they do not teach particular lithographic apparatus, rather a generic photolithographic exposure.
This limitation is met by Tsujita, which discusses the formation of fin patterns having a line and space shape on a substrate. Tsujita states that the resolution limit of an ArF laser will be 36nm ([0030]). As the range of pitches proposed by Sung overlap this size parameter, the range of pitches corresponding to Sung’s d1 (claimed S1) and d2 (claimed S2) each may vary from 0.55 to 2.77 times that of the resolution limit, where graphically in Figure 1 of Sung d1 is represented as smaller than d2 (S1 is smaller than S2).
A person of ordinary skill in the art would have found it obvious to arrive at the claimed invention from the combination of Liou, Tsujita and Sung’s disclosures, incorporating the variable spacing of Sung into Liou’s methods to arrive at a variable-spaced fin structure allowing for improved electrostatic control of the resultant device.
Regarding Claims 15-17, Liou discloses the limitations of the claims as discussed above regarding claim 14, however does not teach a specific spacing parameter that corresponds to claimed S3 between dummy hard mask and active hard mask patterns.
This limitation is met by Sung.
Sung teaches a double masking process for forming semiconductor film arrays having controlled and variable fin pitch within different arrays, using a top mandrel layer overlaying a bottom mandrel layer, where sidewall structures are formed on first mandrels to define a patterned hard mask in tandem with a photoresist layer over a second region of the substrate so as to define second mandrels.
The pitch of the fin structures here may be d1 through d4, where d1, d2, d3, and d4 may each be independently ranging from 20 to 100 nm though smaller and larger pitch values are contemplated. The fin structures themselves have a line width ranging from 5-20nm. The substrate surface may have dimensions such as a diameter ranging from 50-450 mm. The specification allows for a pitch d1 and d2 (S1 and S2) where d1 is smaller than d2 (S and S1 are 50nm, S2 is 55nm) and a third pitch may, for example, be 50.5nm (S + 0.01S). See Columns 3-4.
Sung discloses that the variable fin spacing improves FinFET performance by allowing for improved electrostatic control of the device, such as when gates are wrapped around the raised channel presented by the fin (Background).
A person of ordinary skill in the art would have found it obvious to arrive at the claimed invention from the combination of Liou and Sung’s disclosures, incorporating the variable spacing of Sung into Liou’s methods to arrive at a variable-spaced fin structure allowing for improved electrostatic control of the resultant device.
Regarding Claim 19 and 20, Liou teaches the limitations of the claims as discussed above regarding claims 14 and 18, but do not teach an experimental example having an additional hard mask layer over the third hard mask patterns (between the reference’s fifth and sixth etching steps), nor does Liou teach a first hard mask layer including three layers on the substrate.
These limitations are met by Sung and Liou together.
Sung teaches a bottom spacer layer over the bottom set of features formed into the hard mask prior to further etching in Figure 10, so as to define the sidewall structures further before removing the hard mask material, where the spacer layer is a silicon oxide (Column 7-8). Incorporating the spacer layer into the method of Liou between the fifth and sixth etch would allow for the tuning of structure features such as line width.
Liou teaches a substrate assembly with a substrate 108 having a semiconductor layer 104 and a hard mask layer 106 thereatop, where the 104 layer may be SiGe (among other materials). The hard mask layer 106 may be SiN or SiO2. Sung teaches a pad oxide layer such as silicon oxide deposited on a substrate so as to serve as a buffer layer between the substrate and overlying hard mask layers. As the layer 104 of Liou is etched, the incorporation of the pad oxide layer would allow it to serve as a buffer layer to protect the underlying substrate and for further etching processing – the hard mask layer of Liou would thus be the assembly of the first pad oxide (SiO2) layer, the SiGe layer, and the overlying SiN hard mask.
A person of ordinary skill in the art would consider it obvious to incorporate spacer layer and the pad oxide layer of Sung into the method of Liou so as to attenuate feature dimensions and to protect the substrate during processing.
Claims 21-31 and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Tang et al (US 9268896 B1, dated 02/23/2016), Liou et al (US 9324570 B1), and Tsujita (US 20160260639 A1)
Regarding Claims 21-27, Tang discloses a method for forming a photomask, wherein the photomask formation method comprises providing a predetermined fin array (an initial pattern layout) having a plurality of fin patterns as described from Columns 2 -6, where the fin array includes active fins and dummy fins that are to be removed during a fin-removal process. Mandrel patterns including active and temporary are also defined in the predetermined array and may be width-adjusted. A photomask is manufactured based on the resultant mandrel patterns. As is discussed in Column 2 Lines 5-25, the spaces between fins are adjustable, and the spaces between mandrels are adjustable. In the case where a mandrel and a fin are next to each other, therefore the space between them would become adjusted (increased or decreased) by moving either the mandrel or the fin (so as to increase the space between the moved mandrel/fin and mandrel/fin next to it opposite the fin/mandrel). When the space between dummy fin patterns is not adjusted, the amount decreased between dummy fin patterns would be 0 (claim 25). The mandrels and pre-mandrels (dummy mandrels) are formed longitudinally to the fin structures (See figures 3 and 4). Tang discloses in Column 3 Lines 3-29 that the pitch may vary between 10nm and 60nm between any two adjacent fin patterns. The adjustments to pitch may take a pitch from 10nm to a pitch of 60nm (an adjustment increase range of 0% to 600%) or from 60nm to 10nm (an adjustment decrease range of 0% to 600%), or an intermediate amount such as increasing pitch by 10% (claim 22).
After determining the various parameters of the photomask, Tang’s disclosure covers a fabrication process wherein a computer-controlled device fabricates the photomask by forming mandrels on a substrate via the patterning of a material layer (a sacrificial layer) through a photomask (Column 4 Lines 46-67).
Tang does not disclose forming a photoresist pattern using the photomask over an underlying layer.
This limitation is met by Liou.
Liou discloses a method of manufacturing a semiconductor device, wherein a substrate 102 is provided (more specifically, the substrate includes a semiconductor layer 104 as part of the assembly – 102 and 104 taken together are considered ‘the substrate’ as claimed) , a hard mask 106 is disposed thereatop, and a sacrificial layer 110 is formed atop the hard mask layer 106. A dummy layer 112 (second hard mask layer as claimed) is formed on the sacrificial layer 110, after which a first photomask 114 is used to form a plurality of transitional masks 116a and mandrel masks 116b, where the mandrel masks 116b have a smaller line width than the transitional masks 116a. The masks are produced from a photoresist composition layer that may be patterned through a photomask.
Neither Liou nor Tang teach a specific resolution limit of a lithography apparatus used in patterning structures and they do not teach particular lithographic apparatus, rather a generic photolithographic exposure.
This limitation is met by Tsujita, which discusses the formation of fin patterns having a line and space shape on a substrate. Tsujita states that the resolution limit of an ArF laser will be 36nm ([0030]). As the range of pitches proposed by Sung overlap this size parameter, the range of pitches corresponding to Tang’s pitches each may vary from 0.27 to 1.66 times that of the resolution limit, overlapping the claimed range of 1.05-1.2 times the resolution limit of a lithography apparatus used in exposure. As each fin pattern may have a spacing within this range, the second spacing between dummy fin pattern may be embodied with a spacing size overlapping the claimed range.
A person of ordinary skill in the art would have found it obvious to arrive at the claimed invention from the general disclosure of the reference Tang, which discloses a method for forming a photomask, and then applying its use to the method of Liou – applying a known prior art product to a known prior art process to achieve the predictable result of a patterned photoresist pattern.
Regarding Claim 28 – 31 and 33, Tang discloses a method for forming a photomask, wherein the photomask formation method comprises providing a predetermined fin array (an initial pattern layout) having a plurality of fin patterns as described from Columns 2 -6, where the fin array includes active fins and dummy fins that are to be removed during a fin-removal process. Mandrel patterns including active and temporary are also defined in the predetermined array and may be width-adjusted. A photomask is manufactured based on the resultant mandrel patterns. As is discussed in Column 2 Lines 5-25, the spaces between fins are adjustable, and the spaces between mandrels are adjustable. In the case where a mandrel and a fin are next to each other, therefore the space between them would become adjusted (increased or decreased) by moving either the mandrel or the fin (so as to increase the space between the moved mandrel/fin and mandrel/fin next to it opposite the fin/mandrel). When the space between dummy fin patterns is not adjusted, the amount decreased between dummy fin patterns would be 0 (claim 25). The mandrels and pre-mandrels (dummy mandrels) are formed longitudinally to the fin structures (See figures 3 and 4). Tang discloses in Column 3 Lines 3-29 that the pitch may vary between 10nm and 60nm between any two adjacent fin patterns.
After determining the various parameters of the photomask, Tang’s disclosure covers a fabrication process wherein a computer-controlled device fabricates the photomask by forming mandrels on a substrate via the patterning of a material layer (a sacrificial layer) through a photomask (Column 4 Lines 46-67).
Tang does not teach a specific resolution limit of a lithography apparatus used in patterning structures and does not teach particular lithographic apparatus, rather a generic photolithographic exposure.
This limitation is met by Tsujita, which discusses the formation of fin patterns having a line and space shape on a substrate. Tsujita states that the resolution limit of an ArF laser will be 36nm ([0030]). As the range of pitches proposed by Sung overlap this size parameter, the range of pitches corresponding to Tang’s pitches each may vary from 0.27 to 1.66 times that of the resolution limit, overlapping the claimed range of 1.05-1.2 times the resolution limit of a lithography apparatus used in exposure. As each fin pattern may have a spacing within this range, the second spacing between dummy fin pattern may be embodied with a spacing size overlapping the claimed range.
Neither Tsujita nor Tang disclose a method comprising a first photoresist pattern using a first photomask over a sacrificial layer over a hard mask layer disposed over a substrate and further processing limitations. These limitations are met by Liou.
Liou discloses a method of manufacturing a semiconductor device, wherein a substrate 102 is provided (more specifically, the substrate includes a semiconductor layer 104 as part of the assembly – 102 and 104 taken together are considered ‘the substrate’ as claimed) , a hard mask 106 is disposed thereatop, and a sacrificial layer 110 is formed atop the hard mask layer 106. A dummy layer 112 (second hard mask layer as claimed) is formed on the sacrificial layer 110, after which a first photomask 114 is used to form a plurality of transitional masks 116a and mandrel masks 116b, where the mandrel masks 116b have a smaller line width than the transitional masks 116a. The photomasks are produced from a photoresist composition layer that may be patterned.
An etching process is used to pattern the sacrificial layer 110 and dummy layer 112 using the mandrel and transitional masks 116b and 116a to define the etched pattern and produce a sacrificial pattern defined as 110a or 110b depending on the overlying transitional mask 116a or mandrel mask 116b and 112a/112b layer regions (110a and 110b define sacrificial pattern(s) as claimed). A spacer layer 118 is then conformally formed and patterned to form sidewall patterns for the dummy patterns 112a and 112b and then anisotropically etched to from spacers on the sacrificial blocks 110a and 110b. The second hard mask pattern is removed. An additional hard mask 122 may be disposed over the mandrel and transitional mask layers 116 a and 116b (claim 18), which is then patterned using a second photomask for forming mask features for dummy patterns. The first hard mask (106) is patterned using the remaining portion of the second hard mask pattern as a mask, thus forming a third hard mask pattern (106b), after which the substrate (the assembly of 102+104) is patterned using the 106b pattern as a mask to form a fin structure 104b and additional feature structures 104a. Mask layers are described in Col 3 Lines 13-20 as being oxide or nitride materials, which include silicon oxide and silicon nitride. The sacrificial layer is not particularly limited by material, but would be selected from materials that could be etched, such as those of the semiconductor layer 104 which is composed of materials such as polycrystalline silicon (polysilicon), SiGe, and Si (Column 2 Line 25 to Column 3 Line 67).
A person of ordinary skill in the art would have found it obvious to arrive at the claimed invention from the general disclosure of the reference Tang, which discloses a method for forming a photomask, and then applying its use to the method of Liou – applying a known prior art product to a known prior art process to achieve the predictable result of a semiconductor manufacturing process for making a device article..
Claim 32 is rejected under 35 U.S.C. 103 as being unpatentable over Tang et al (US 9268896 B1, dated 02/23/2016), Tsujita (US 20160260639 A1) and Liou et al (US 9324570 B1) as applied to claim 29 above, and further in view of Sung et al (US 9991131 B1, dated 06/05/2018).
Liou and Tang teach the limitations of the claims as discussed above regarding claims 29 but do not teach an experimental example having an additional hard mask layer over the third hard mask patterns (between the reference’s fifth and sixth etching steps), nor does Liou teach a first hard mask layer including three layers on the substrate.
These limitations are met by Tang, Sung, and Liou together.
Sung teaches a bottom spacer layer over the bottom set of features formed into the hard mask prior to further etching in Figure 10, so as to define the sidewall structures further before removing the hard mask material, where the spacer layer is a silicon oxide (Column 7-8). Incorporating the spacer layer into the method of Liou between the fifth and sixth etch would allow for the tuning of structure features such as line width.
Liou teaches a substrate assembly with a substrate 108 having a semiconductor layer 104 and a hard mask layer 106 thereatop, where the 104 layer may be SiGe (among other materials). The hard mask layer 106 may be SiN or SiO2. Sung teaches a pad oxide layer such as silicon oxide deposited on a substrate so as to serve as a buffer layer between the substrate and overlying hard mask layers. As the layer 104 of Liou is etched, the incorporation of the pad oxide layer would allow it to serve as a buffer layer to protect the underlying substrate and for further etching processing – the hard mask layer of Liou would thus be the assembly of the first pad oxide (SiO2) layer, the SiGe layer, and the overlying SiN hard mask.
A person of ordinary skill in the art would consider it obvious to incorporate spacer layer and the pad oxide layer of Sung into the method of Liou and Tang so as to attenuate feature dimensions and to protect the substrate during processing.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW PRESTON TRAYWICK whose telephone number is (571)272-2982. The examiner can normally be reached Monday - Friday 8-5.
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/A.P.T./Examiner, Art Unit 1737
/MARK F. HUFF/Supervisory Patent Examiner, Art Unit 1737
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