DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed on September 9, 2025, with respect to the Objections to Specifications and Drawings have been fully considered but they are not persuasive. Applicant argues that the transposition of the terms “first source/drain” and “second source/drain” and the mismatch of other claim terms used versus their corresponding terms used in the Specifications does not constitute a lack of enablement. The Examiner respectfully disagrees. The previous Office Action did not cite a lack of enablement as the reason for raising the Objections. Rather, the basis of the Objections is to make the record clear such that the claim terms can be easily matched to their corresponding terms in the Specification terms and elements in the Drawings without extensive remapping that a person of ordinary skill would have to do. “Usually the terminology of the claims present on the filing date of the application follows the nomenclature of the specification, but sometimes in amending the claims or in adding new claims, new terms are introduced that do not appear in the specification. The use of a confusing variety of terms for the same thing should not be permitted,” please see MPEP § 608.01(o). Also see MPEP § 2173.03 and 37 CFR § 1.75 (d)(1).
Furthermore, regarding independent claims 1, 11, and 19, the applicant argues that Horch does not teach element 441 to be parallel to element 410, as required in claim 1. The examiner respectfully disagrees. Since elements 441 and 410 are both three-dimensional objects, then the language in claim 1 can be broadly be interpreted to mean that both of these elements extend along the vertical axis of Examiner Fig. 2 (Fig. 4A of Horch) as found in the claim 1 rejection below.
Lastly, regarding dependent claim 3, the applicant argues that element 441 is not vertically interposed between elements 422a and SD1. The examiner respectfully disagrees. Again, due to the fact that these elements are three-dimensional objects, then the term “vertically interposed” in claim 3 can be broadly be interpreted in the manner in described below. The examiner has added Examiner Fig. 3 to further clarify the matter.
In summary, this application is not placed in a condition for an allowance.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Claims 1-10 require a first memory cell, a first transistor, a first anti-fuse structure, a first gate structure, a first source/drain structure, a second source/drain structure, a first electrode, a second electrode, a first dummy gate structure, and a first insulator, which are declared in paragraph [0054] but whose description does not refer to a specific reference number in the figures. It is important that the specification shows the specific reference number associated with each claim element to overcome this lack of antecedence, as explained below.
These claims require a first electrode to be electrically coupled to the first source/drain through a first interconnect structure. Paragraph [0025] defines the first electrode to be element 210A and the second electrode to be element 210B. First, the term “a first interconnect structure” is not defined in the specifications, which is a lack of antecedence basis by itself. Second, even if the examiner liberally applies the definition of a source/drain interconnect structure MD314 in paragraph [0029] to be the first interconnect structure, Figs. 3-4 still does not show the first electrode 210A to be coupled to the first source/drain 230D through the interconnect structure MD314. Instead, these figures show the second electrode 210B is being coupled to MD314.
For the purpose of compact prosecution, the examiner treats the 210B to be the first electrode and 210A to be the second electrode.
Claims 11-18 require a first interconnect structure and a second interconnect structure that lacks antecedence basis.
Paragraph [0025] defines a first via structure 210A and a second via structure 210B and paragraph [0026] defines a third via structure 250A and a fourth via structure 250B. These claims further require “the first via structure is electrically coupled to a first portion of the active region through a first interconnect structure that perpendicularly extends across the first portion of the active region, and the third via structure is electrically coupled to a second portion of the active region through a second interconnect structure that perpendicularly extends across the second portion of the active region”, which lacks antecedence. However, neither the specifications nor the Figs. 3-4 show the first via structure 210A coupled to the active region 302 through interconnect structure MD314. Instead, the second via structure 210B is connected to MD314. For the purpose of compact prosecution, the examiner treats the 210B to be the first via structure and 210A to be the second via structure. Similarly, there are no figures that show the third via structure is electrically coupled to a second portion of the active region through a second interconnect structure.
Claims 19-20 require a first gate structure and a second gate structure, described in paragraphs [0054] and [0056], but whose description does not refer to a specific reference number in the figures. It is important that the specifications shows the specific reference number associated with each claim element to overcome this lack of antecedence, as explained below.
These two claims further require the second via structure is vertically disposed over a second gate structure, which lacks antecedence basis in the specifications. Paragraph [0044] defines the first via to be element VG320(210A) and the second via to be element VD 328 (210B). Paragraphs [0045] and [0056] also defines the first gate structure to be element 306, due to it being applied with the required first voltage and the second gate structure to be element 304, due to it being applied with the required second voltage. However, Fig. 4 shows the first via structure VG320, instead of the second via structure VD328, to be disposed over the second gate structure 304. Furthermore, the term “a first interconnect structure” is not defined in the specifications, which is a lack of antecedence basis by itself. Secondly, even if the examiner liberally applies the definition of a source/drain interconnect structure MD314 in paragraph [0029] to be the first interconnect structure, Fig. 4 still does not show the amended limitation of the first via structure VG320 being electrically coupled to a portion of an active region 302 through the interconnect structure MD314, defined as a source/drain interconnect structure in paragraph [0029], that perpendicularly extends across the portion of the active region. Instead, the second via structure VD328 is shown to be connected to MD314.
For the purpose of compact prosecution, the examiner treats the first gate structure to be element 306 and the second gate structure to be element 304 in Figs. 3 and 4 and the first via to be VD328 and the second via to be VG320.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description:
As mentioned in the specifications objections above, claims 1-10 require a first electrode to be electrically coupled to the first source/drain through a first interconnect structure which is not shown in Figs. 3 and 4.
Similarly, claims 11-18 require “the first via structure is electrically coupled to a first portion of the active region through a first interconnect structure that perpendicularly extends across the first portion of the active region, and the third via structure is electrically coupled to a second portion of the active region through a second interconnect structure that perpendicularly extends across the second portion of the active region” which is also not shown in Figs. 3 and 4.
Lastly, claims 19-20 require “the second via structure is vertically disposed over a second gate structure” and “the first via structure is electrically coupled to a portion of an active region through the interconnect structure that perpendicularly extends across the portion of the active region” that are not shown in Figs. 3 and 4.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-4 and 19 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Horch (US 9,953,990 B1).
Regarding claim 1, Horch teaches a memory device, comprising:
a first memory cell (402; see Fig. 4A) including a first transistor (408) and a first anti-fuse structure (406) electrically coupled to each other in series (as shown in Fig. 4A and Fig. 4B, 406 and 408 are serially connected; note: Fig. 4B taken along line C-C' of Fig. 4A, see Col 12, Lines. 55-57; also, Fig. 4B shows vias 422a, 421a, and 422b connecting the first electrode 416 of 406 to the source/drain of 408; hence the 408 & 406 are electrically coupled in series );
wherein the first transistor includes a first gate structure (410) extending across an active region (fin 404), a first source/drain structure (SD1, see Examiner Fig. 1; Col. 12, Ln. 44-47) disposed in a first portion (P1) of the active region (P1 is the portion of 404 under SD1), and a second source/drain structure (SD2, see Examiner Fig. 1; Col 12, Ln 37) disposed in a second portion (P2) of the active region (P2 is the portion of 404 under SD2); and
wherein the first anti-fuse structure includes a first electrode (422a, see Col. 12, Ln. 45; 422a is part of 406 as shown in Fig. 4A) electrically coupled to the first source/drain structure (422a is connected to 441 & 422b & 416 and then to SD1; see Col. 12, Ln. 44-47) through a first source/drain interconnect structure (441) that extends across (plain meaning: over, spanning) the first source/drain structure (using BRI, Examiner Fig. 1 shows 441 vertically spanning over SD1; also Examiner Fig. 2 shows the vertical sides of 441 spanning over P1, on which SD1 is disposed), a second electrode disposed ( 422d, see Col. 12, Ln. 50 ) over a first dummy gate structure (420; see Col. 12, Lines. 2; this is a dummy gate since it does not turn the transistor 408 on or off but rather used to apply a voltage to break the antifuse gate insulating layer 446, See Col. 13, Lines. 12-19; this definition of a dummy gate is congruous to Application Specification ¶ [0034]), and a first insulator (446; Col. 12, Ln. 63) laterally interposed between the first electrode and the second electrode (446 is between 422d and 422a along the horizontal axis (i.e., laterally) when viewed from the top of Fig. 4B ), wherein the first dummy gate structure extends along a first edge (Examiner Fig. 2: vertical edge of 404; using BRI, Examiner Fig. 2 shows dummy gate structure 420 extending along, and not necessarily directly on top of, the vertical edge of active region 404) of the active region, and wherein the first electrode and the second electrode are formed as via structures (Fig. 4B shows 422a and 422d as vias; see also Col. 12, Ln. 39-54 and Col 9, Ln 17-21) in a same metallization layer (the metallization layer found in insulating layer 448b; see Col. 12, Ln 44-50 and Col. 10, Ln 29-34), and wherein the first source/drain interconnection structure (441) extends in parallel with the first gate structure (410) and the first dummy gate structure (420; as shown in Examiner Fig. 2; 441, 410, and 420 the vertical surfaces of 410, 420, and 441 extend in parallel with one another along the vertical axis of the figure).
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Examiner Fig. 1. Taken from Horch Fig. 4B.
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Examiner Fig. 2. Taken from Horch Fig. 4A showing fin 404.
Regarding claim 3, Horch teaches the memory device of claim 1, wherein the first source/drain interconnect structure (441, see Examiner Fig. 3) is vertically interposed (Examiner Fig. 3, which is the top view of Examiner Fig. 1, shows 441 spanning across, i.e., in between, SD1 and 422a) between the first source/drain structure (SD1) and the first electrode (422a; also see Examiner Fig. 1 which shows 441 is between 422a and SD1 and is located on top of both elements, i.e., vertically interposed).
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Examiner Fig. 3. Taken from Horch Fig. 4A showing how S/D interconnect 441 is vertically interposed between SD1 and 441.
Regarding claim 4, Horch teaches the memory device of claim 1, wherein a programming voltage (Col. 8, Lines. 28-31: 4 volts) applied to the second electrode is configured to break down the first insulator (446; Col. 13, Lines. 12-19).
Regarding claim 19, Horch teaches a method for operating a memory device, comprising:
activating a transistor (408; see Fig. 4A, Col. 12, Ln. 15-16) of a memory cell (402) by applying a first voltage to a first gate structure (410; see Figs. 4A & 4B; Col. 12, Ln. 37) of the transistor (Col. 8, Lines 4-9: "The OTP bitcell may consist of two devices, a fuse device and a select device.”; Col. 8, Lines 28-32: "A write operation to the OTP memory cell may be performed by... gate of the NMOS select device is held at a high voltage to turn the NMOS select device on," emphasis added; hence Horch teaches a transistor 408, being a select device, whose gate structure receives a first voltage as part of doing a write operation); and
breaking down an insulator (446; see Fig. 4B; Col. 12, Ln. 63) laterally interposed (446 is laterally, i.e., horizontally, interposed between 422b & 422d when Fig. 4B is rotated counter- clockwise ) between a first via structure (422b; 422b is connected to 441 & 422a & 416, with 416 directly connected to the insulator 446; see Col. 12, Lines. 17 and 42; also see Col. 8, Lns 33-35: “The drain of the NMOS select device is held at either 0V… or to the high voltage...”) and a second via structure (422d; see Col. 12, Ln. 50) by applying a second voltage (Col. 8, Lines. 28-31: 4 volts) on the second via structure, thereby programming the memory cell (Col. 8, Lines. 28-31);
wherein the second via structure (422d) is vertically disposed over a second gate structure (420; see Col. 12, Line 2; this gate structure does not turn the transistor 408 on or off but rather used to apply a voltage to break the antifuse gate insulating layer 446, See Col. 13, Lines. 2-19; this definition of a dummy gate is congruous to Application Specification [0034] ), and the first via structure (422b) is vertically disposed over a source/drain interconnect structure (421b) that is laterally interposed between the first gate structure (410) and the second gate structure (420) (Fig. 4B, 421b is in between 410 and 420 along the horizontal axis), wherein the first via structure and the second via structure are formed in a same metallization layer (Fig. 4B shows 422b & 422d are found in the same insulating layer 448b), wherein the first via structure is electrically coupled to a portion (P1, see Examiner Fig. 1 in claim 1 rejection above) of an active region (404) through the source/drain interconnect structure (Examiner Fig. 1 shows 422b electrically coupled to P1 through 421b) that perpendicularly extends across the portion of the active region (Examiner Fig. 2 shows the vertical sides of 422b extending perpendicularly across and over P1; see Examiner Fig. 1 in claim 1 rejection above), and wherein the first gate structure (410), the second gate structure (420), and the source/drain interconnect structure (441) extend in parallel with one another (as shown in Examiner Fig. 2 in claim 1 rejection above, the vertical surfaces of 410, 420, and 441 extend in parallel with one another along the vertical axis of the figure ).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2, 5-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Horch (US 9,953,990 B1) in view of Chang (US 2021/0083065 A1).
Regarding claim 2, Horch teaches the memory device of claim 1, and further teaches the memory device wherein the first dummy gate structure (420, see Fig. 4B) extends along a first edge (left edge) of a dielectric region ( 432; see Col. 12, Ln. 62 ).
However, Horch does not teach the memory device wherein the first dummy gate structure extends along a first edge of the active region.
Chang, in the same field of invention, teaches a memory device wherein the first dummy gate structure ( WLP0; see Fig. 2 & 3A-3D; [0024]; this is a dummy gate since it does not turn on the read transistor T2 on/off but rather is used to break the dielectric layer 122A of the anti-fuse T1; see also Fig. 1; [0018, 0020]) extends along a first edge (left edge) of the active region ( 100; see Fig. 1; also marked as OD0 in Fig. 2, ¶ [0024]; fin 114 in Fig. 3A & 3C & 3D; and fin 103 in Fig. 3B).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Chang into the device of Horch to extend the dummy gate structure of the first anti-fuse structure along a first edge of the active region in a memory device comprising of a first memory cell that includes a first transistor and the first anti-fuse structure. The ordinary artisan would have been motivated to modify Horch in the manner set forth above for at least the purpose of simplifying the method of making the active region (i.e., fin) on which the first transistor and the first anti-fuse structure are mounted on by having the same material consistent throughout these two structures (Chang ([0032]: isolation region 114 may include insulating materials such as a dielectric material, e.g. silicon oxide; these material are the same materials for Horch dielectric region 432 (Horch Col 12, Ln. 62: STI oxide)).
Regarding claim 5, Horch teaches the memory device of claim 1, further comprising:
a second memory cell (Fig. 4A: bottom 402 below the top-most 402) including a second transistor (the bottom 408 below the top-most 408) and a second anti-fuse structure (the bottom 406 below the top-most 406) electrically coupled to each other in series (as shown in Fig. 4A and Fig. 4B, 406 and 408 are serially connected; note: Fig. 4B taken along line C-C' of Fig. 4A; see Col 12, Lines. 55-57; also, Fig. 4B shows vias 422a, 421a, and 422b connecting the first electrode 416 under 406 to the source/drain of 408; hence the 408 & 406 are electrically coupled in series);
wherein the second transistor includes a second gate structure (410; Figs. 4A & 4B) extending across a second active region (Fig. 4B: 404 ), a third source/drain structure (SD1; see Examiner Fig. 1 in claim 1 rejection above) disposed in a third portion (P1) of the active region, and a fourth source/drain (SD2) structure disposed in a fourth portion (P2) of the active region (Horch teaches a memory array as shown in Fig. 4A; hence the second memory cell has the same structure and elements as the first memory cell; see also Col.12, Ln 55); and
wherein the second anti-fuse structure includes a third electrode (422a) disposed electrically coupled to the third source/drain structure (SD1; Fig. 4A shows 422a is part of anti-fuse structure; 422a is connected to 441 & 422b and then to SD1; see Col. 12, Ln. 44-47), a fourth electrode (422d) disposed over a second dummy gate structure (420; see Col. 12, Lines. 2; this is a dummy gate since it does not turn the transistor 408 on or off but rather used to apply a voltage to break the antifuse gate insulating layer 446, See Col. 13, Lines. 12-19; this definition of a dummy gate is congruous to Application Specification ¶ [0034]), and a second insulator (446) laterally interposed between the third electrode and the fourth electrode (446 is in between 422d and 422a along the horizontal, i.e., lateral, axis).
However, Horch does not teach wherein the second transistor extending across the same active region of the first transistor.
Chang, in the same field of invention, teaches a memory device (10, see Fig. 1) wherein the second transistor (T4, see [0018]) extending across the same active region (100; active region is also shown as OD0 in Fig. 2, ¶ [0024]; fin 114 in Fig. 3A & 3C & 3D; and fin 103 in Fig. 3B; see also ¶ [0032, 0037]) of the first transistor (T2; [0018]).
Chang further teaches two memory cells ( 101A&101B; see Fig. 1, [0017]) each having a transistor (T2&T4) and an anti-fuse structure ( T1 &T3; see [0018, 0020]: these require a program voltage to cause a breakdown in their dielectric layers; hence T1 & T3 are anti-fuses) extending across the same active region 100.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Chang into the device of Horch wherein the first transistor and the second transistor shares the same active region in a memory device consisting of a first memory cell on top of the active region, with the first memory cell having a first transistor and a first anti-fuse structure; and a second memory cell on top of the active region, with the second memory cell having a second transistor and a second anti-fuse structure. The ordinary artisan would have been motivated to modify Horch in the manner set forth above for at least the purpose of having a compact structure and optimizing the dimensions of non-volatile memory devices (Chang [0001]: note that Chang's design enables a common source/drain region (labelled as SD-1 in Fig. 1) shared by T2 and T4; hence the ordinary skilled artisan will be motivated to save the space required for separate source/drain regions each for T2 and T4).
Regarding claim 6, Horch in view of Chang teaches the memory device of claim 5, wherein the first dummy gate structure ( WLP0; see Chang Figs. 2, 3A-3D; [0024]) and second dummy gate structure (WLP1; [0024]; WLP0 and WLP1 are dummy gate structures since they do not turn on the read transistors T2 and T4 on/off but rather are used to break the dielectric layers 122A under their structures as part of programming the anti-fuses T1 and T3) extend along a first edge (left edge) and a second edge (right edge) of the active region (100, see Fig. 1; also marked OD0 in Fig. 2 and fin 114 in Fig 3A, 3C, 3D and fin 112 in Fig. 3B), respectively (as explained in claim 5 rejection, an ordinary skilled artisan would be motivated to have the second transistor T4 (Chang Fig. 1) share the same source/drain SD-1 as the first transistor T2; hence the second dummy gate of the second antifuse T3 would then be located at the right edge of the active region 100).
Regarding claim 7, Horch in view of Chang teaches the memory device of claim 5, wherein the second portion (P2; see Examiner Fig. 1 in claim 1 rejection above; this second portion P2, when taking Horch in view of Chang, is under T2 of Chang Fig. 1) of the active region and the fourth portion ( P2; this section portion P2 would be under transistor T4 in Chang Fig. 1; see claim 5 103 rejection) of the active region merge together (Chang Fig. 1: T4 and T2 shares the same source/drain SD-1 as explained by the motivation of the ordinary skilled artisan in the claim 5 rejection).
Regarding claim 8, Horch in view of Chang teaches the memory device of claim 5, further comprising a second source/drain interconnect structure ( 441; see Examiner Fig. 1 in claim 1 rejection above; Col. 12, Ln. 42) vertically interposed between the third source/drain structure (SD1) and the third electrode (422a; 411 is located on top of and spanning both SD1 and 422a, hence it is vertically interposed between the two).
Regarding claim 9, Horch in view of Chang teaches the memory device of claim 5, wherein the first through fourth electrodes (Horch Fig. 4B: 422d & 422a) are each formed as a via structure (Horch Col 12, Lines 39-43: "The electrical connections of the FinFET 408 to other circuit elements (e.g., anti-fuse device 406) may be made through vias 422, local interconnects 421, and first metal layer 441. Vias 422a, 422b, 422c is the same as via 322a, 322b, and 322c", emphasis added).
Regarding claim 10, Horch in view of Chang teaches the memory device of claim 5, wherein the active region extend along a first lateral direction (Chang Fig. 3A: active region 114 extends along the X-axis), while the first and second dummy gate structures, and the first and second gate structures each extend along a second lateral direction perpendicular to the first lateral direction (WLP0, WLR0, WLR1, and WLP1 extends vertically along the Y-axis) (Alternatively, Horch Fig. 4A shows active region 404 extending from left-to-right while 420 & 410 extends from top-to-bottom; both directions are lateral when viewed in the context of Fig. 4B since Fig. 4A is the plan view of Fig. 4B).
Regarding claim 11, Horch teaches a memory device, comprising:
a first memory cell (402; see Fig. 4A; Col. 12, Ln. 15-16) including a first transistor (408; Col. 12, Ln. 15-16) and a first memory structure (406; Col. 12, Ln. 15-16) electrically coupled to each other in series (as shown in Fig. 4A and Fig. 4B, 406 and 408 are serially connected; note: Fig. 4B taken along line C-C' of Fig. 4A; see Col 12, Lines. 55-57; also, Fig. 4B shows vias 422a, 421a, and 422b connecting the first electrode 416 under 406 to the source/drain of 408; hence the 408 & 406 are electrically coupled in series); and
a second memory cell (see Fig. 4A: a second memory cell is located below first memory cell 402, i.e., the top-most row, with the exact same structure as 402) including a second transistor (408) and a second memory structure (406) electrically coupled to each other in series;
an active region (404, see Fig. 4A) that extends along a first lateral direction (horizontal direction as shown in Figs. 4A);
wherein the first memory structure includes a first insulator (446; see Fig. 4B, Col. 12, Ln. 63) laterally interposed between a first via structure (422a) and a second via structure (422d; 446 is in between 422a & 422d along the horizontal axis; hence it is laterally interposed between the two vias), and the second memory structure includes a second insulator (the second instance of 446 within the second memory structure in Fig. 4A) laterally interposed between a third via structure (422a of second memory structure in Fig. 4A) and a fourth via structure (422d of second memory structure in Fig. 4A), wherein the first via structure to the fourth via structure are formed in a same metallization layer (Fig. 4B shows the metallization of vias 422a & 422d are found in the same insulating layer 448b; see Col. 12, Ln 44-50 and Col. 10, Ln 29-34 ), wherein the first via structure (422a) is electrically coupled to a first portion (P1, see Examiner Figs. 1 & 2 in claim 1 rejection above) of the active region (404) through a first source/drain interconnect structure (441 & 422b & 421b) that perpendicularly extends across the first portion of the active region (Examiner Fig. 2 shows the vertical sides of 441 perpendicularly extending over and across P1 of 404), and the third via structure (442a) is electrically coupled to a second portion (P1 of the second memory structure) of the active region (404 of the second memory structure) through a second source/drain interconnect structure (441 & 422b & 421b of the second memory structure) that perpendicularly extends across the second portion of the active region (Examiner Fig. 2 in claim 1 rejection above shows the vertical sides of 441 perpendicularly extending over and across P1 of 404), and wherein the first and second source/drain interconnect structures extend in a second lateral direction (vertical direction in Fig. 4A; note: as shown in Figs. 4A and 4B, the first and second source/drain interconnect structures have vertical surfaces that extend along the vertical axis of Fig. 4B; hence these interconnect structures extend along the vertical axis) perpendicular to the first lateral direction (horizontal direction of Fig. 4A).
However, Horch does not teach a memory device wherein the first transistor and second transistor are sharing the same active region that extends along the first lateral direction, the first transistor and second transistor disposed next to each other along the first lateral direction.
Chang, in the same field of invention, teaches a memory device (10) wherein the first transistor (T2) and second transistor (T4; note: T2 and T4 are analogous to Horch's first and second transistors because these are used for reading the value of the memory structure T1 and T3; T1 and T3 being analogous to Horch's memory structure 306 since they require a voltage for programming it, see [0020]; likewise T2 & T1 are connected in series, congruous to Horch's design embodiments) are sharing the same active region ( 100; active region is also shown as OD0 in Fig. 2, [0024]; fin 114 in Fig. 3A & 3B & 3D; and fin 103 in Fig. 3B; see also [0032], [0037]) that extends along the first lateral direction (horizontal direction in Figs. 1 & 2, which is shown as X-axis in Figs. 3-4), the first transistor (T2) and the second transistor (T4) disposed next to each other along the first lateral direction (see Fig. 1).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Chang into the device of Horch wherein the first transistor and the second transistor shares the same active region in a memory device consisting of a first memory cell on top of the active region, with the first memory cell having a first transistor and a first memory structure; and a second memory cell on top of the active region, with the second memory cell having a second transistor and a second memory structure, and wherein the active region extends along the first lateral direction, the first transistor and second transistor disposed next to each other along the first lateral direction. The ordinary artisan would have been motivated to modify Horch in the manner set forth above for at least the purpose of having a compact structure and optimizing the dimensions of non-volatile memory devices (Chang [0001]: note that Chang's design enables a common source/drain region (labelled as SD-1 in Fig. 1) shared by T2 and T4; hence the ordinary skilled artisan will be motivated to save the space required for separate source/drain regions each for T2 and T4).
Regarding claim 12, Horch in view of Chang teaches the memory device of claim 11, wherein the second via structure ( 422d; see Horch Fig. 4B) is configured to apply a first breakdown voltage (Col. 8, Lines. 28-31: 4V) on the first insulator 446 to short the second (422d) and first via structures (422a; Col. 13, Lines. 12-19; it is known in the art that rupturing a dielectric between a first and a second via will cause a short between the two vias), and the fourth via structure 422d (of second memory cell) is configured to apply a second breakdown voltage (Col. 8, Lines. 28-31: 4V) on the second insulator 446 (of second memory cell) to short the fourth 422d and third via 422a (of second memory cell) structures (Col. 13, Lines. 12-19; it is known in the art that rupturing a dielectric between a first and a second via will cause a short between the two vias).
Regarding claim 13, Horch in view of Chang teaches the memory device of claim 11, wherein the second via structure (422d; see Horch Fig. 4B; 422d of the first memory cell) and fourth via structure (422d of the second memory cell) are in direct contact with a first dummy gate structure (420 of the first memory cell) and a second dummy gate structure (420 of the second memory cell), respectively.
Regarding claim 14, Horch in view of Chang teaches the memory device of claim 13, wherein the first dummy gate structure (WLP0; see Chang Figs. 2, 3A-3D; [0024]) and second dummy gate structure (WLP1; WPL0 and WLP1 are dummy gate structures since they do not turn read transistors T2 & T4 on/off but rather are used to break the dielectric layers 122A) extend along opposite edges (left and right edges) of the active region (100, see Fig. 2; also marked OD0 in Fig. 3 and fin 114 in Figs. 3A, 3C, and 3D and fin 112 in Fig. 3B), respectively (as explained in claim 11 rejection, an ordinary skilled artisan would be motivated to have the second transistor T4 share the same source/drain SD-1 as the first transistor T2; hence the second dummy gate of the second memory structure T3 would then be located at the right edge of the active region 100).
Regarding claim 15, Horch in view of Chang teaches the memory device of claim 14, wherein the first transistor (408, see Horch Fig. 4A; the 408 of the first memory cell) includes a first gate structure (410, see Horch Fig. 4B; Col. 12, Ln. 37) and the second transistor (408, see Horch Fig. 4A; the 408 of second memory cell) includes a second gate structure ( 410, see Horch Fig. 4B; Col. 12, Ln. 37; this is the 410 for the second memory cell), and wherein the first and second dummy gate structures 420, and the first and second gate structures are in parallel with each other (Horch Fig. 4A shows 410 & 420 are in parallel with each other along the vertical axis, with the second set of 410 & 420 added to the right of Fig. 4A as shown by Chang in Fig. 1, referring to elements T4 and T3).
Regarding claim 16, Horch in view of Chang teaches the memory device of claim 15, wherein the active region include a third portion (P2, see Examiner Fig. 1) laterally interposed between the first and second gate structures (as mentioned in claim 11 rejection and referring to Chang Fig. 3A, the ordinary skilled artisan will be motivated to add the second gate structure WLR1 and the second memory structure WLP1 to the right of P2, i.e., the region of 114 under SD2 is analogous to P2 of Horch, the effect of this is that P2 is in between the first gate structure WLR0 of the first memory cell and the second gate structure WLR1 of the second memory cell), wherein the first transistor includes a second source/drain structure (SD2 of the first memory cell; Col 12, Ln 37) and the second transistor includes a fourth source/drain structure (SD2 of the second memory cell; Col 12, Ln 37), and wherein the second and fourth source/drain structures are disposed in the portion (P2) of the active region (as illustrated in Chang Fig. 1, SD-1 is above the portion P2 of the active region shared by both source/drain regions of T2 & T4; also see Chang Fig. 3B where P2 is the region under SD2).
Regarding claim 17, Horch in view of Chang teaches the memory device of claim 15, wherein the first and third via structures (422a; see Horch Fig. 4B) are in direct contact with the first source/drain interconnect structure ( 441 & 422b & 421b) and the second source/drain interconnect structure (second instantiation of 441 & 422b & 421b for the second memory cell), respectively, the first source/drain interconnect structure laterally interposed between the first dummy gate structure (420) and the first gate structure (410), the second source/drain interconnect structure laterally interposed between the second dummy gate structure (420) and the second gate structure (410; Fig. 4B shows 441 laterally interposed between 420 and 410).
Regarding claim 18, Horch in view of Chang teaches the memory device of claim 17, wherein the first transistor includes a first source/drain structure (422b; Examiner Fig. 1 illustrates that SD1, which 422b is connected to, is a source/drain; also: Col. 12, Ln. 44-47: "A first metal layer 441 may be patterned to connect via 422a and via 422b, thus connecting the first electrode 416 to the drain or the source of transistor 408", emphasis added; hence SD1 is a source/drain of 408; and hence 422b is a source/drain structure) and the second transistor includes a third source/drain structure (the 422b of the second transistor in the second memory cell), and wherein the first source/drain structure and third source/drain structure are in direct contact with the first source/drain interconnect structure and the second source/drain interconnect structure, respectively (Examiner Fig. 1 shows 422b is directly connected to 441).
Regarding claim 20, Horch teaches the method of claim 19, wherein the second gate structure (420, see Fig. 4B) extends along an edge (left edge) of an oxide region (432, see Col. 12, Ln. 62), while the first gate structure (410) extends across the active region (410 extends across 404) with two portions (P1&P2, see Examiner Fig. 1 in claim 1 rejection above) of the active region disposed on opposite sides of the first gate structure (P1 & P2 are on opposite sides of 410).
However, Horch does not teach the memory device wherein the second gate structure extends along a first edge of the active region.
Chang, in the same field of invention, teaches a memory device wherein the second gate structure (WLPO; Fig. 2 & 3A-3D; [0024]; WLPO is analogous to Horch's second gate structure since it does not turn on the read transistor T2 on/off but rather is used to break the dielectric layer 122A under it as part of programming the anti-fuse T1) extends along a first edge (left edge) of the active region (100; see Fig. 1; also marked as ODO in Fig. 2, 4; or fin 114 in Fig. 3A & 3C & 3D; or fin 103 in Fig. 3B).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Chang into the device of Horch to extend the second gate structure of the memory device along a first edge of the active region in a memory device comprising of a first gate structure and a second gate structure, wherein a first voltage is applied to the first gate structure and a second voltage is applied to the second gate structure when programming the memory device. The ordinary artisan would have been motivated to modify Horch in the manner set forth above for at least the purpose of simplifying the method of making the active region (i.e., fin) on which the first gate structure and the second gate structure is mounted on by having the same material consistent throughout the device (Chang [0032]: isolation region 114 may include insulating materials such as a dielectric material, e.g. silicon oxide; these material are the same materials for Horch dielectric region 432 (Horch Col 12, Ln. 62: STI oxide)).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DOUGLAS YAP/Assistant Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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