DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Group I and Species 1, was elected.
Response filed June 10, 2026 is acknowledged. Non-Elected Invention, and Species, Claims 4, 9-16 and 18 have been withdrawn from consideration. Claims 1-18 are pending.
Action on Group I, Species 1, claims 1-3, 5-8 and 17 follows.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-8 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over INOUE et al. (US. Patent No. 5,773,355) in view of WANG et al. (US. Pub. No. 2018/0330983).
With respect to claim 1, INOUE teaches a method for manufacturing a semiconductor-on-insulator structure, substantially as claimed including the following steps:
- providing an FD-SOI substrate successively comprising, from its base to its top:
* a monocrystalline semiconductor substrate (103) having electrical resistivity ranging between 0.001 Ω.cm and 106 Ω.cm, hence includes the range of 500 Ω.cm and 30 k Ω.cm, **an interstitial oxygen content (0i) ranging between 20 and 40 old ppma, and having first P- or N-type doping;
* an electrically insulating layer (121) having a thickness about 400 nm, hence within the range of 20 nm and 400 nm;
* a monocrystalline semiconductive layer (101a) having P-type doping;
- heat treating the FD-SOI substrate at a temperature 1000 °C to 1300 °C, hence encompasses greater than or equal to 1175 °C, for a time of two hours or more, hence encompasses greater than or equal to 1 hour, in order to form a P-N junction (not shown) in the monocrystalline semiconductor substrate (103) at a determined depth with respect to the electrically insulating layer (121),
* by diffusing P-type dopants from the monocrystalline semi-conductive layer (101a) through the electrically insulating layer (121) in the substrate; and
* if the substrate (103) has P-type doping, forming, in the substrate, heat donors by precipitation of the interstitial oxygen;
to form, in the substrate, a first region having N-type doping extending between the base of the substrate and the P-N junction (not shown) and a second P-doped region (not shown) located between the first region and the electrically insulating layer (121). (See FIGs. 1, 5, 6, 18, 22, 27, 28, 33, 37).
Thus INUOE is shown to teach all the features of the claim with the exception of explicitly disclosing the interstitial oxygen content of the monocrystalline semiconductor substrate (103).
However, WANG teaches a method for manufacturing a semiconductor-on-insulator structure, including the following steps:
- providing an FD-SOI substrate successively comprising, from its base to its top:
* a monocrystalline semiconductor substrate (10) having electrical resistivity of at least 500 Ω.cm, an interstitial oxygen content ranging between 10 and 35 ppma, hence overlaps the range of 20 and 40 old ppma, and having first P- or N-type doping. (See FIGs. 1D-E).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to provide the conventional FD-SOI substrate of INOUE having the interstitial oxygen content as taught by WANG for the same intended purpose of forming high quality SOI substrate.
Regarding the formation of P-N junction in the monocrystalline semiconductor substrate, the heat treating of the SOI substrate of INOUE of up to 1300 °C and the duration greater than 1 hour, would inherently result in:
1) diffusing (out-diffusion process) P-type dopant from the monocrystalline semiconductor layer (101a) into the monocrystalline semiconductor substrate (103) of N-type to form the P-N junction; or
2) converting P-type substrate (103) to N-type through heat donors by precipitation of interstitial oxygen and diffusing (out-diffusion process) P-type dopant from the monocrystalline semiconductor layer (101a) into the converted P-type monocrystalline semiconductor substrate (103) into N-type to form the P-N junction.
With respect to claim 2, the monocrystalline substrate (103) of INOUE or WANG is made of silicon and/or the monocrystalline layer is a silicon layer.
With respect to claim 3, In view of WANG, the FD- SOI substrate is obtained by transferring a layer (62) of a donor substrate onto a recipient substrate (10), according to the following steps: - supplying:
* the donor substrate comprising a monocrystalline semiconductive layer (30) having P-type doping, and an embrittlement zone (40) located in the monocrystalline silicon layer (30) defining the layer (62) to be transferred; and
* the monocrystalline semiconductor recipient substrate (10) having electrical resistivity ranging between 500 Ω.cm and 30 k Ω.cm, an interstitial oxygen content ranging between 20 and 40 old ppma, and first P- or N-type doping;
- bonding the donor substrate (30) onto the recipient substrate (10) by means of an electrically insulating layer (42), the thickness of which ranges between 20 nm and 400 nm;
- detaching the donor substrate (30) along the embrittlement zone (40) in order to form the FD-SOI substrate. (See FIGs. 1D-E).
With respect to claim 5, in view of WANG, the embrittlement zone (40) is formed by implanting atomic species in the donor substrate (30) so as to define the transfer layer (62).
With respect to claim 6, the recipient substrate (103) and the monocrystalline layer (101) of the donor substrate of INOUE are P-doped with boron.
With respect to claim 7, the P-N junction (not shown) of INOUE is formed at a depth ranging between 1 µm and 5 µm from the electrically insulating layer (102).
Regarding the depth of the P-N junction, the diffusion depth of the P-type dopant is a depend on temperature and duration of the thermal process. Since the thermal process of INOUE being performed similar in scope of the claims, the limitation: “the P-N junction is formed at a depth ranging between 1 µm and 5 µm from the electrically insulating layer” is obviously met.
With respect to claim 8, the electrically insulating layer of INOUE or WANG comprises a silicon oxide layer.
With respect to claim 17, in view of WANG, the FD-SOI substrate is obtained by transferring a layer (62) of a donor substrate (30) onto a recipient substrate (10), according to the following steps:
- supplying: * the donor substrate (30) comprising a monocrystalline semiconductor layer having P-type doping, and an embrittlement zone (40) located in the monocrystalline silicon layer defining the layer (62) to be transferred; and
* the monocrystalline semiconductor recipient substrate (10) having electrical resistivity ranging between 500 Ω.cm and 30 k Ω.cm, an interstitial oxygen content ranging between 20 and 40 old ppma, and first P- or N-type doping;
- bonding the donor substrate (30) onto the recipient substrate (10) by way of an electrically insulating layer (42), the thickness of which ranges between 20 nm and 400 nm; and
- detaching the donor substrate along the embrittlement zone (40) to form the FD-SOI substrate. (See FIGs. 1D-1E).
Response to Arguments
Applicant's arguments filed June 10, 2026 have been fully considered but they are not persuasive.
Applicant argues:
Inoue, Wang, and their combination do not describe at least "heat treating the FD-SOI substrate at a temperature greater than or equal to 1175°C for a time greater than or equal to 1 hour, to form a P-N junction in the monocrystalline semiconductor substrate at a determined depth with respect to the electrically insulating layer by diffusing P-type dopants from the monocrystalline semiconductor layer through the electrically insulating laver in the substrate" as recited by independent claim 1.
However, regarding the “heat treating the FD-SOI substrate at a temperature greater than or equal to 1175°C for a time greater than or equal to 1 hour”, INOUE, col. 13, lines 23-30, explicitly teaches: “In the present embodiment, … The out diffusion was performed under the conditions of a pressure of 10-7-500 Torr, a H2 flow rate of 10 liters/min-200 liters/min, and a temperature of 1000 °C -1300 °C. As an example, FIG. 28 illustrates the results of experiments of out diffusion of boron at a pressure of 80 Torr, an H2 flow rate of 100 liters/min, and a temperature of 1150 °C.
As shown in FIG. 28, the diffusion time is varying from 120 min to as much as 480 min, which is greater than or equal to 1 hour.
Therefore, INOUE clearly teaches the limitations: heat treating the FD-SOI substrate at a temperature greater than or equal to 1175°C for a time greater than or equal to 1 hour.
Applicant further argues:
Independent claim 1 further recites: "heat treating the FD-SOI substrate at a temperature greater than or equal to 1175°C for a time greater than or equal to 1 hour, to form a P-N junction in the monocrystalline semiconductor substrate at a determined depth with respect to the electrically insulating laver by diffusing P-type dopants from the monocrystalline semiconductor laver through the electrically insulating laver in the substrate.” Emphasis added. Inoue also does not disclose, teach, or otherwise render obvious at least these features.
However, the limitation: “… to form a P-N junction in the monocrystalline semiconductor substrate at a determined depth with respect to the electrically insulating laver by diffusing P-type dopants from the monocrystalline semiconductor laver through the electrically insulating laver in the substrate” is an inherent result of the heat treating action.
INOUE col. 5, lines 18-21, explicitly teaches: An n-type substrate or a p-type substrate may be used as the silicon substrate 103, and the resistivity of the silicon substrate 103 may have any value between 0.001 and 106 Ω.cm.
According to INOUE, the substrate 103 can be either n-type or p-type; and the monocrystalline semiconductor layer 101b is a p-type. In view of WANG, wafer 10 comprises interstitial oxygen.
The heat treatment, as discussed above, of the SOI work piece that includes p-type layer 101b on the wafer 103 of n-type or p-type would obviously result in: p-type dopant, in this case boron, a fast diffuser, of the p-type 101b diffuses into substrate 103.
There are two scenarios:
1) if wafer 103 is a p-type, the interstitial oxygen in the p-type wafer 103, in view of WANG, would undergo heat donor precipitation to form n-type substrate. This is well known in the art. Combining p-type dopant diffusing from layer 101b, wafer 103, now n-type, would obviously form p-n junction at a predetermined depth.
2) if the wafer 103 is an n-type, no heat donor precipitation occurs even with interstitial oxygen, the p-type dopant diffusing from layer 101b, wafer 103 an n-type, would obviously form p-n junction at a predetermined depth.
Note that, INOUE explicitly teaches that boron is out diffusion from layer 101b. Although INOUE does not show the diffusion of p-type dopant in layer 101b into wafer 103, however, under the heat treatment of greater than or equal to 1175 °C for a time greater than or equal to 1 hour, as discussed above, the diffusion of p-type dopant in layer 101b into the wafer 103 is inherently occurred.
Therefore, INOUE, in view of WANG, implicitly teaches the claimed limitations, forming p-n junction at a predetermined depth with respect to the insulation layer.
Note that, the term “out diffuse” does not means up only. “out diffuse” means diffuse out of the layer.
The applicant uses a correct term “diffusion away from”
Applicant, however, fails to provide any evidence to the contrary.
The rejection is therefore, maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ANH D MAI/ Primary Examiner, Art Unit 2893
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