DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Group I and Species 1, was elected.
Non-Elected Invention, and Species, Claims 4, 18 and 9-16 have been withdrawn from consideration. Claims 1-18 are pending.
Action on Group I, Species 1, claims 1-3, 5-8 and 17 follows.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on February 06, 2026 was filed after the mailing date of the Office Action on October 31, 2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-8 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over INOUE et al. (US. Patent No. 5,773,355) in view of WANG et al. (US. Pub. No. 2018/0330983).
With respect to claim 1, INOUE teaches a method for manufacturing a semiconductor-on-insulator structure, substantially as claimed including the following steps:
- providing an FD-SOI substrate successively comprising, from its base to its top:
* a monocrystalline semiconductor substrate (103) having electrical resistivity ranging between 0.001 Ω.cm and 106 Ω.cm, hence includes the range of 500 Ω.cm and 30 k Ω.cm, **an interstitial oxygen content (0i) ranging between 20 and 40 old ppma, and having first P- or N-type doping;
* an electrically insulating layer (121) having a thickness about 400 nm, hence within the range of 20 nm and 400 nm;
* a monocrystalline semiconductive layer (101a) having P-type doping;
- heat treating the FD-SOI substrate at a temperature 1000 °C to 1300 °C, hence encompasses greater than or equal to 1175 °C for a time of two hours or more, hence encompasses greater than or equal to 1 hour, in order to form a P-N junction (not shown) in the monocrystalline semiconductor substrate (103) at a determined depth with respect to the electrically insulating layer (121),
* by diffusing P-type dopants from the monocrystalline semi-conductive layer (101a) through the electrically insulating layer (121) in the substrate; and
* if the substrate (103) has P-type doping, forming, in the substrate, heat donors by precipitation of the interstitial oxygen;
to form, in the substrate, a first region having N-type doping extending between the base of the substrate and the P-N junction (not shown) and a second P-doped region (not shown) located between the first region and the electrically insulating layer (121). (See FIGs. 1, 5, 6, 18, 22, 27, 28, 33, 37).
Thus INUOE is shown to teach all the features of the claim with the exception of explicitly disclosing the interstitial oxygen content of the monocrystalline semiconductor substrate (103).
However, WANG teaches a method for manufacturing a semiconductor-on-insulator structure, including the following steps:
- providing an FD-SOI substrate successively comprising, from its base to its top:
* a monocrystalline semiconductor substrate (10) having electrical resistivity of at least 500 Ω.cm, an interstitial oxygen content ranging between 10 and 35 ppma, hence overlaps the range of 20 and 40 old ppma, and having first P- or N-type doping. (See FIGs. 1D-E).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to provide the conventional FD-SOI substrate of INOUE having the interstitial oxygen content as taught by WANG for the same intended purpose of forming high quality SOI substrate.
Regarding the formation of P-N junction in the monocrystalline semiconductor substrate, the heat treating of the SOI substrate of INOUE of up to 1300 °C and the duration greater than 1 hour, would inherently result in:
1) diffusing (out-diffusion process) P-type dopant from the monocrystalline semiconductor layer (101a) into the monocrystalline semiconductor substrate (103) of N-type to form the P-N junction; or
2) converting P-type substrate (103) to N-type through heat donors by precipitation of interstitial oxygen and diffusing (out-diffusion process) P-type dopant from the monocrystalline semiconductor layer (101a) into the converted P-type monocrystalline semiconductor substrate (103) into N-type to form the P-N junction.
With respect to claim 2, the monocrystalline substrate (103) of INOUE or WANG is made of silicon and/or the monocrystalline layer is a silicon layer.
With respect to claim 3, In view of WANG, the FD- SOI substrate is obtained by transferring a layer (62) of a donor substrate onto a recipient substrate (10), according to the following steps: - supplying:
* the donor substrate comprising a monocrystalline semiconductive layer (30) having P-type doping, and an embrittlement zone (40) located in the monocrystalline silicon layer (30) defining the layer (62) to be transferred; and
* the monocrystalline semiconductor recipient substrate (10) having electrical resistivity ranging between 500 Ω.cm and 30 k Ω.cm, an interstitial oxygen content ranging between 20 and 40 old ppma, and first P- or N-type doping;
- bonding the donor substrate (30) onto the recipient substrate (10) by means of an electrically insulating layer (42), the thickness of which ranges between 20 nm and 400 nm;
- detaching the donor substrate (30) along the embrittlement zone (40) in order to form the FD-SOI substrate. (See FIGs. 1D-E).
With respect to claim 5, in view of WANG, the embrittlement zone (40) is formed by implanting atomic species in the donor substrate (30) so as to define the transfer layer (62).
With respect to claim 6, the recipient substrate (103) and the monocrystalline layer (101) of the donor substrate of INOUE are P-doped with boron.
With respect to claim 7, the P-N junction (not shown) of INOUE is formed at a depth ranging between 1 µm and 5 µm from the electrically insulating layer (102).
Regarding the depth of the P-N junction, the diffusion depth of the P-type dopant is a depend on temperature and duration of the thermal process. Since the thermal process of INOUE being performed similar in scope of the claims, the limitation: “the P-N junction is formed at a depth ranging between 1 µm and 5 µm from the electrically insulating layer” is obviously met.
With respect to claim 8, the electrically insulating layer of INOUE or WANG comprises a silicon oxide layer.
With respect to claim 17, in view of WANG, the FD-SOI substrate is obtained by transferring a layer (62) of a donor substrate (30) onto a recipient substrate (10), according to the following steps:
- supplying: * the donor substrate (30) comprising a monocrystalline semiconductor layer having P-type doping, and an embrittlement zone (40) located in the monocrystalline silicon layer defining the layer (62) to be transferred; and
* the monocrystalline semiconductor recipient substrate (10) having electrical resistivity ranging between 500 Ω.cm and 30 k Ω.cm, an interstitial oxygen content ranging between 20 and 40 old ppma, and first P- or N-type doping;
- bonding the donor substrate (30) onto the recipient substrate (10) by way of an electrically insulating layer (42), the thickness of which ranges between 20 nm and 400 nm; and
- detaching the donor substrate along the embrittlement zone (40) to form the FD-SOI substrate. (See FIGs. 1D-1E).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH D MAI whose telephone number is (571)272-1710 (Email: Anh.Mai2@uspto.gov). The examiner can normally be reached 10:00-4:00PM.
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/ANH D MAI/ Primary Examiner, Art Unit 2893
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