Office Action Predictor
Last updated: April 17, 2026
Application No. 17/758,624

METHOD OF JOINING TWO SEMI-CONDUCTOR SUBSTRATES

Final Rejection §103
Filed
Jul 11, 2022
Examiner
WILCZEWSKI, MARY A
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
soitec
OA Round
3 (Final)
85%
Grant Probability
Favorable
4-5
OA Rounds
2y 10m
To Grant
95%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allow Rate
703 granted / 828 resolved
+16.9% vs TC avg
Moderate +10% lift
Without
With
+10.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
34 currently pending
Career history
862
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
40.5%
+0.5% vs TC avg
§102
25.6%
-14.4% vs TC avg
§112
24.4%
-15.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 828 resolved cases

Office Action

§103
DETAILED ACTION This Office action is in response to the Response filed on 17 February 2026. Claims 1-20 are pending in the application. This application is a national stage application filed under 35 USC 371 of PCT/FR2020/052439, filed on 15 December 2020, which claims priority to FR2000140, filed on 09 January 2020. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3, 6, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Takizawa et al., JP 2002-16239, in view of JP 6182476, cited by Applicant on the Information Disclosure Statement submitted on 01 April 2025, both of record. With respect to independent claim 1, Takizawa et al. disclose a method for joining two semiconductor substrates by molecular adhesion, shown in Figs. 3(a)-3(g) and 2(a)-2(d), the method comprising: a step a) of bringing a first 1/101 and a second substrate 2 into intimate contact to form an assembly having a bonding interface, as shown in Fig. 3(d) and 2(a); a step b) of bonding the first 1 and second 2 substrates to form the bonding interface, this step b) generating bubbles 3 and 4 at the bonding interface, see Figs. 3(d) and 2(a) and paragraphs [0002], [0005], [0017] (“The first substrate 1 and the separately prepared second substrate (handle wafer) 2 are adhered so as to sandwich the O .sub.2 layer 504 therebetween. At this time, voids (bubbles) 3 may be taken in near the periphery of the substrate due to the above-described cause (see FIG. 6). In the step shown in FIG. 3E, the presence or absence and position of the void are confirmed by using, for example, an infrared transmission type void observation device, and if there is a void, FIGS. By applying the method described with reference to FIG. 2D and FIGS. 2A to 2D, the void is removed (the substrates 1 and 2 are completely adhered)”); a debonding step c) of at least partially debonding the first 1 and second 2 substrates at the bonding interface to eliminate the bubbles 3 and 4, see Figs. 2(b) and 2(c) (“First, in the step shown in FIG. 1A, one of the voids (poorly adhered portions) 3, 4 confirmed using, for example, an infrared transmission type void observation device (FIG. 1). In (a), a wedge 5 is applied between the two substrates 1 and 2 constituting the bonded substrate 100 near the void 3). Next, in the step shown in FIG. Are gradually inserted into the bonded substrate 100, so that the two substrates 1, 2 Are partially separated (peeled). Here, the wedge 5 is inserted until the void is completely taken into the separated portion. Next, in the step shown in FIG. 1C, the wedge 5 inserted into the bonded substrate 100 is gently pulled out. As a result, the separated portion (including the initial void portion) between the two substrates 1 and 2 constituting the bonded substrate 100 Is extruded, and the separated portion comes into close contact. Through the above steps, one void is removed. Next, the other voids (the voids 4 in FIG. 1A) are subjected to the steps shown in FIGS. 1A to 1D, whereby the other voids can be removed. According to this method for removing voids, the voids in the bonded substrate can be removed to such an extent that the subsequent steps are not affected, and the yield can be improved.“); and a step d) of bringing the first 1 and the second substrate 2 back into intimate contact at the bonding interface to reform the assembly, as shown in Fig. 2(d). Although Takizawa et al. disclose a step b) of bonding the first 1 and second 2 substrates to form the bonding interface, this step b) generating bubbles 3 and 4 at the bonding interface, Takizawa et al. do not disclose a step b) of reaction-annealing the bonding interface at a first temperature, higher than a predetermined first temperature. However, in the same field of endeavor, JP 6182476 discloses a step of bonding the first W1 and second W2 substrates by heating to form the bonding interface, this heat-bonding step generating bubbles at the bonding interface, see Figs. 20A-20E {“By the way, when the upper wafer W1 and the lower wafer W2 are bonded in stages from the central portions W1a and W2a toward the peripheral portions W1b and W2b as described above, the peripheral edges of the bonded upper wafer W1 and lower wafer W2 are joined. Bubbles may be generated near the portions W1b and W2b.”). JP 6182476 discloses in bonding wafer W1 and wafer W2, a first heating mechanism 242 is used to heat wafer W1 and a second heating mechanism 262 is used to heat wafer W2, see Figs. 16D-16H. In light of the disclosure of JP 6182476, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the bubbles 3 and 4 formed in the known method of Takizawa et al. could have been formed by reaction-annealing the bonding interface at a first temperature, higher than a predetermined first temperature (room temperature). Since the substrates (or wafers) are heated during bonding, as shown in Figs. 16D-16H of JP. 6182476, it is obvious the boning interface would be “reaction-annealed”. With respect to claim 2, in the method of Takizawa et al., the debonding step c) is performed under a controlled atmosphere (“A method of driving a bundled fluid (liquid or gas) into the 00 edge is preferable. In the latter case, After the start of the separation process is formed by inserting a wedge into a part of the edge of the porous Si layer 102, for example, a bundled fluid (liquid or gas) is driven toward the start. Good. Examples of the fluid include water, an organic solvent such as alcohol, an acid such as hydrofluoric acid, an alkali such as potassium hydroxide, a liquid having an etching action capable of selectively etching the porous Si layer 102, and the like. It is suitable. Further, a low-temperature cooling medium or a super-cooling medium can be adopted as the fluid. Furthermore, as a fluid, air, nitrogen gas, Gases such as carbon dioxide gas and rare gas can also be adopted.”). .With respect to claim 3, in the method of Takizawa et al., the controlled atmosphere of the debonding step c) comprises an anhydrous atmosphere or vacuum (“Gases such as carbon dioxide gas and rare gas can also be adopted.”). With respect to claim 6, in the method of Takizawa et al., the debonding step c) comprises mechanically separating the first 1 and second 2 substrates by inserting a blade 5 between the first 1 and second 2 substrates at the bonding interface, as shown in Figs. 2(a)-2(d), see the Abstract (“Then, a wedge 5 is inserted near a void 3 to temporarily separate (strip off) a part of the substrate which includes the void 3. Thereafter, the wedge 5 is pulled off to cause the separated part to airtightly adhere to its original place again.”).. With respect to claim 16, in the method of Takizawa et al., the debonding step c) comprises mechanically separating the first 1 and second 2 substrates by inserting a blade 5 between the first 1 and second 2 substrates at the bonding interface, as shown in Figs. 2(a)-2(d), see the Abstract (“Then, a wedge 5 is inserted near a void 3 to temporarily separate (strip off) a part of the substrate which includes the void 3. Thereafter, the wedge 5 is pulled off to cause the separated part to airtightly adhere to its original place again.”). Claims 4-5 and 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Takizawa et al., JP 2002-16239, in view of JP 6182476, as applied to claim 1 above, and further in view of Cha et al., US 2007/0158831, all of record. Takizawa et al. et al. and JP 6182476 are applied as above. With respect to claims 4 and 14, in the method of Cha et al., the debonding is performed at a temperature of about 200oC. to about 900oC, see paragraph [0039]. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the debonding step c) in the known method of Takizawa et al. could be carried out at least partially at a second temperature higher than or equal to ambient temperature, since it is known in the art to debond substrates at temperatures higher than or equal to ambient temperature, and debonding at high temperatures will reduce stress on the substrates. With respect to claims 5 and 15, since Cha et al. teach a debonding temperature of about 200oC. to about 900oC (see paragraph [0039]), it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the debonding step c) in the known method of Takizawa et al. could be carried out at a temperature lower than 700°C, since it is known in the art to debond substrates at a temperature of about 200oC. to about 900oC, and debonding at these temperatures will reduce stress on the substrates. With respect to claim 11, in the method of Cha et al., the debonding is performed at a temperature of about 200oC. to about 900oC, see paragraph [0039]. Therefore, it would have been obvious to the skilled artisan that the debonding step c) in the known method of Landru et al. could be carried out entirely at a second temperature higher than or equal to ambient temperature, since it is known in the art to debond substrates at temperatures higher than or equal to ambient temperature, and debonding at high temperatures will reduce stress on the substrates. With respect to claim 12, since Cha et al. teach a debonding temperature of about 200oC. to about 900oC, it would have been obvious to the skilled artisan that the second temperature could be lower than 200°C. With respect to claim 13, Cha et al. teach a debonding temperature of about 200oC. to about 900oC, see paragraph [0039]. . In light of this disclosure, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the second temperature could have been lower than 100oC, since the debonding temperature is a result-effective variable. Therefore, the determination of the optimum or workable debonding temperatures would be characterized as routine experimentation. The claimed debonding temperatures are not deemed to patentably distinguish Applicant’s claimed method from that of the applied prior art. Claims 7-10 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Takizawa et al., JP 2002-16239, in view of JP 6182476, as applied to claims 1 and 3 above, and further in view of Henley et al., US 6,048,411, all of record. Takizawa et al. and JP 6182476 are applied as above. With respect to claim 7, neither Takizawa et al. nor JP 6182476 disclose after step d), a step e) of thinning the first substrate in order to form a thin layer. In the same field of endeavor, Henley et al. disclose thinning a first substrate 40 after a bonding step d) in order to form a thin layer 45, see Figs. 5 and 6 and column 6, lines 27-43. It would have been obvious to one skilled in the art to thin one of the substrates after rebonding in the known method of Takizawa et al. to form a thin layer, since the resulting structure is suitable for use in integrated circuit manufacturing processes, without having to deposit an epitaxial layer, thereby providing a substitute for an epitaxial layer using a method that is both cost effective and efficient. With respect to claim 8, in the method of Henley et al., the first substrate 40 comprises a main face 44 (shown in Fig. 4) and a buried weakened plane 33 (shown in Fig. 4), the thin layer 45 being defined between the main face 44 and the buried weakened plane 41, as shown in Figs. 5 and 6. Due to the advantages associated with the technique of Henley et al., it would have been obvious to one skilled in the art to use this technique in the known method of Takizawa et al. With respect to claim 9, as shown in Figs. 5 and 6, the technique of Henley et al. comprises splitting along the buried weakened plane 41 in order to transfer the thin layer 45 onto the second substrate. Due to the advantages associated with the technique of Henley et al., it would have been obvious to one skilled in the art to use this technique in the known method of Takizawa et al. With respect to claim 10, in the method of Takizawa et al. in view of JP 6182476 and Henley et al., step e) comprises a heat treatment (see column 5, lines 65-67, and column 6, lines 34-41, of Henley et al.) at a temperature higher than or equal to a predetermined second temperature (500oC, see column 5, lines 8-10, of Henley et al.) causing spontaneous splitting along the buried weakened plane (see column 6, lines 27-43, of Henley et al.); and the first temperature of step b) (see claim 8 of Henley et al.) and the second temperature of step c) (in the method of Cha et al., the debonding is performed at a temperature of about 200oC) are lower than the predetermined second temperature (500oC). In light of the teachings of the applied prior art, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use relatively low temperatures during the bonding, debonding, and splitting processes in order to reduce any thermal damage to the substrates or the separated film. With respect to claim 17, none of Landru et al., Lin et al., and Cha et al. disclose after step d), a step e) of thinning the first substrate in order to form a thin layer. In the same field of endeavor, Henley et al. disclose thinning a first substrate 40 after a bonding step d) in order to form a thin layer 45, see Figs. 5 and 6 and column 6, lines 27-43. It would have been obvious to one skilled in the art to thin one of the substrates after rebonding in the known method of Landru et al. to form a thin layer, since the resulting structure is suitable for use in integrated circuit manufacturing processes, without having to deposit an epitaxial layer, thereby providing a substitute for an epitaxial layer using a method that is both cost effective and efficient. With respect to claim 18, in the method of Henley et al., the first substrate 40 comprises a main face 44 (shown in Fig. 4) and a buried weakened plane 33 (shown in Fig. 4), the thin layer 45 being defined between the main face 44 and the buried weakened plane 41, as shown in Figs. 5 and 6. Due to the advantages associated with the technique of Henley et al., it would have been obvious to one skilled in the art to use this technique in the known method of Landru et al. With respect to claim 19, as shown in Figs. 5 and 6, the technique of Henley et al. comprises splitting along the buried weakened plane 41 in order to transfer the thin layer 45 onto the second substrate. Due to the advantages associated with the technique of Henley et al., it would have been obvious to one skilled in the art to use this technique in the known method of Landru et al. With respect to claim 20, in the method of Landru et al. in view of Cha et al. and Henley et al., step e) comprises a heat treatment (see column 5, lines 65-67, and column 6, lines 34-41, of Henley et al.) at a temperature higher than or equal to a predetermined second temperature (500oC, see column 5, lines 8-10, of Henley et al.) causing spontaneous splitting along the buried weakened plane (see column 6, lines 27-43, of Henley et al.); and the first temperature of step b) (see claim 8 of Henley et al.) and the second temperature of step c) (in the method of Cha et al., the debonding is performed at a temperature of about 200oC) are lower than the predetermined second temperature (500oC). In light of the teachings of the applied prior art, it would have been obvious to the skilled artisan to use relatively low temperatures during the bonding, debonding, and splitting processes in order to reduce any thermal damage to the substrates or the separated film. Response to Arguments Applicant's arguments filed 17 February 2026 have been fully considered but they are not persuasive. Applicant has pointed out that Takizawa discloses performing a heat treatment at 1000 oC for strengthening the bond between the substrates 1 and 2 after performing the void removal process as described with reference to FIG. 3(d), but never teaches or suggests in any way debonding the first and second substrates 1, 2 along the bonding interface thereafter. Applicant has argued that Takizawa does not teach or suggest that this heat treatment generates any bubbles at the bonding interface, so the POSITA would have no motivation to contemplate temporarily debonding the substrates 1, 2 along the bonding interface after conducting the heat treatment to strengthen the bond therebetween. Firstly, the language of claim 1 is open-ended, and therefore, does not preclude a subsequent heat treatment. It has been well established that the transitional term “comprising” is synonymous with "including," "containing," or "characterized by," is inclusive or open-ended and does not exclude additional, unrecited elements or method steps. See, e.g., Mars Inc. v. H.J. Heinz Co., 377 F.3d 1369, 1376, 71 USPQ2d 1837, 1843 (Fed. Cir. 2004). Secondly, Takizawa et al. has not been relied upon to teach reaction-annealing the bonding surface. JP 6182476 has been relied upon to teach reaction-annealing bonding of two wafers and clearly recognizes that this reaction-annealing bonding of the two wafers generates bubbles at the bonding interface. Since the claims have been rejected over Takizawa et al. in view of JP6182476, Takizawa et al. need not teach or suggest that heat treatment performed at 1000 oC generates bubbles at the bonding interface. The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). Hence, Takizawa et al. need not teach that the heat treatment at 1000 oC generates bubbles at the bonding interface, since this is clearly taught by JP 6182476. Takizawa et al. clearly teaches that bringing a first and a second substrate into intimate contact to form an assembly having a bonding interface generates bubbles at the bonding interface. The secondary reference JP 6182476 has been relied on to teach reaction-annealing the first and second substrate which is also known to generate bubbles at the bonding interface. Applicant has further argued that JP 6182476 (Mimura) does not teach or suggest any temperature for which the wafers W1 and W2 are heated. However, independent claim 1 does not require any specific temperature. Claim 1 merely requires reaction-annealing “at a first temperature, higher than a predetermined first temperature”. Secondly, Applicant has argued that Mimura expressly teaches that the wafers W1, W2 are simply joined by "van der Waals forces (intermolecular forces)" after bonding. Mimura, [0084]. Applicant further argued that Mimura does not appear to teach or suggest any heat treatment or anneal for strengthening the bond between the wafers W1 and W2. However, this is not accurate. JP 6182476 clearly teaches that wafers W1 and W2 are brought into contact (that is, bonded) with Van der Waals force and hydrogen bonding. While JP6182476 (Mimura) teaches that bonding starts with pressing the wafers together and generating Van der Waals force between the bonding surfaces, JP6182476 (Mimura) further teaches that the wafers are then hydrogen-bonded, which occurs during heating of the wafers. The bonding apparatus of JP 6182476 clearly has heaters, and it is well known that temperature is a crucial factor influencing the strength of hydrogen bonds (H-bonds). An increase in temperature enhances molecular vibrations due to increased kinetic energy, thereby the bonding strength increases. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the bubbles 3 and 4 formed in the known method of Takizawa et al. could have been formed by reaction-annealing the bonding interface at a first temperature, higher than a predetermined first temperature (room temperature, at which Van der Waals bonding occurs in the method of JP 6182476 (Mimura)). Applicant has further argued that JP 6182476 (Mimura) does not teach debonding. However, JP 6182476 need not teach this, since this limitation is taught by Takizawa et a. As noted above, the test for obviousness is not whether the claimed invention is expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). Hence, JP 6182476 (Mimura) need not teach debonding, since debonding is clearly taught by Takizawa et al. Applicant has argued the references individually and has not set forth any arguments specifically traversing the combination of Takizawa and JP6182476. Admittedly, neither Takizawa et al. nor JP 6182476 anticipate Applicant’s claimed method as recited in independent claim 1. However, claim 1 is deemed obvious over the combination of Takizawa and JP6182476, as set forth in the rejection herein. One cannot show non-obviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Applicant has further argued the rejections with respect to the tertiary reference to Cha rt al., US 2007/0158831. Applicant has argued that there is no teaching or suggestion in Cha that would have motivated a POSITA to modify the method of Takizawa in any way that would arrive at a method according to claim 1. However, Cha et al. was not applied in the rejection of claim 1. For the reasons provided above, the combination of Takizawa and JP6182476 are deemed to render the method of claim 1 obvious, and the previous rejections made over Takizawa in view of JP6182476 have been maintained. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARY A WILCZEWSKI whose telephone number is (571)272-1849. The examiner can normally be reached M-TH 7:30 AM-5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. MARY A. WILCZEWSKI Primary Examiner Art Unit 2898 /MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898
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Prosecution Timeline

Jul 11, 2022
Application Filed
May 15, 2025
Non-Final Rejection — §103
Aug 05, 2025
Response Filed
Nov 13, 2025
Non-Final Rejection — §103
Feb 17, 2026
Response Filed
Mar 09, 2026
Final Rejection — §103
Apr 15, 2026
Response after Non-Final Action

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