Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 1-11, 13-50 are pending in this application.
Applicant elected without traverse invention I (claims 1-30 and 49-50), species 1 (claims 1, 11-30 and 49-50) in the reply filed on March 4, 2025.
Claims 2-10, 31-48 remain withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention and/or species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on March 4, 2025.
The Examiner notes that claims 1, 11, 13-30, and 49-50 are examined and claims 2-10 and 31-48 are withdrawn.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. CN202010072920.X, filed on January 21, 2020, parent Application No. 202010073094.0, filed on Jan 21, 2020, and parent Application No. 202010445827.9, filed on May 22, 2020.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed March 30, 2026 and supplemental amendment filed April 7, 2026. Claim 1 is amended. Claims 2-10, 31-48 remain withdrawn. The Examiner notes that claims 1, 11, 13-30, and 49-50 are examined.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 11, 13-18, 24-30, 49, and 50 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhu (US 2018/0097106 A1), hereinafter referred to as Zhu-1.
With respect to claim 1, Zhu-1 teaches in Figs. 12-13:
A semiconductor device, comprising:
a channel portion (channel layer 1059) on a substrate (substrate 1001),
wherein the channel portion comprises a curved nanosheet/nanowire (para. 59,
channel layer may have thickness 2-10 nm; and is curved at least in a horizontal cross section around 1003 para. 83) with a C-shaped cross section (See Fig. 12);
source/drain portions (doped regions 1055, para 51, “one of the source/drain regions may be formed in the buffer layer 1031, and the other of the source/drain regions may be formed in the semiconductor layer 1005”) respectively located at upper and lower ends of the channel portion (1059) with respect to the substrate (1001) (Fig. 13);
and a gate stack (gate dielectric layer 1015 and gate conductor layer 1017) surrounding a periphery of the channel portion (1059) (Fig. 13)
wherein the curved nanosheet/nanowire comprises a first sidewall and a second sidewall (see annotated Fig. 13 below),
a cross section of each of the first sidewall and the second sidewall is a C-shaped cross section with an opening towards a same direction (opens to left) (see annotated Fig. 13 below),
the first sidewall and the second sidewall extend between the source/drain portions (1055) respectively located at the upper and lower ends of the channel portion (1059),
and the first sidewall and the second sidewall are arc-shaped sidewalls parallel to each other (see annotated Fig. 13 below, sidewalls have a cross section that is arc-shaped under broadest reasonable interpretation of the term “arc-shaped”)
and wherein the curved nanosheet/nanowire (channel layer 1059) has a substantially uniform thickness (para. 59 “channel layer may have a substantially even thickness”)
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Note: The Examiner considers the broadest reasonable interpretation of “arc-shaped” based on a definition of “arc” that means “something arched or curved” (Merriam-Webster definition 2A). Although arches are often curved, arches such as “flat arches” have a similar shape to the cross section of the sidewalls of the channel.
With respect to claim 11, Zhu-1 further teaches:
The semiconductor device according to claim 1,
wherein at least a part of the gate stack (1015 and 1017) close to the channel portion (1059) is substantially coplanar (bottom of 1059 and 1015 on left side are disposed on same plane) with the channel portion (1059) (Fig. 13).
With respect to claim 13, Zhu-1 further teaches:
The semiconductor device according to claim 1,
wherein a size of the source/drain portions (155) in the lateral direction (left/right parallel with the surface of the substrate) with respect to the substrate (1001) is greater than a size of the channel portion in a corresponding direction (see annotated Fig. 19 below).
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With respect to claim 14, Zhu-1 further teaches:
The semiconductor device according to claim 1,
wherein the channel portion (1059) presents an inwardly concaved C shape on each of two sides in the lateral direction with respect to the substrate (See Fig. 13).
With respect to claim 15, Zhu-1 further teaches:
The semiconductor device according to claim 1, further comprising:
a first semiconductor layer (semiconductor layer 1005) and a second semiconductor layer (buffer layer 1031) that are respectively located at the upper end and the lower end of the channel portion with respect to the substrate (Fig. 19),
wherein the source/drain portions (1055) are respectively arranged in the first semiconductor layer and the second semiconductor layer (para 51, “one of the source/drain regions may be formed in the buffer layer 1031, and the other of the source/drain regions may be formed in the semiconductor layer 1005”).
With respect to claim 16, Zhu-1 further teaches:
wherein the source/drain portions (1055) are a doped region (para. 51 “the dopants included in the dopant source layer 1009 may be driven into the active region by, for example, annealing, so that doped regions 1055 are formed therein”) formed in a part of the first semiconductor layer (semiconductor layer 1005) on a side of an opening of the C shape (above the opening of the C shape of 1059) and a doped region formed in a part of the second semiconductor layer (buffer layer 1031) on a side of the opening of the C shape (below the opening of the C shape of 1059), respectively.
With respect to claim 17, Zhu-1 further teaches:
The semiconductor device according to claim 16,
wherein there are doping concentration interfaces (boundary between 1055 and undoped part of 1005 and boundary between 1055 and undoped part of 1031), that are in a substantially vertical direction with respect to the substrate (boundaries are above the substrate and both boundaries contain a vertical portion), between the source/drain portions (1055) and other parts of the first semiconductor layer (1005) and the second semiconductor layer (1031).
With respect to claim 18, Zhu-1 further teaches:
The semiconductor device according to claim 17,
wherein the doping concentration interface between one of the source/drain portions at the upper end and the other parts of the first semiconductor layer in the vertical direction (vertical part of boundary between undoped part of 1005 and 1055) is substantially aligned with the doping concentration interface between one of the source/drain portions at the lower end and the other parts of the second semiconductor layer in the vertical direction (vertical part of boundary between undoped part of 1031 and 1055) (see annotated Fig. 18, both fall along vertical dotted line).
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With respect to claim 24, Zhu-1 further teaches:
The semiconductor device according to claim 15,
wherein at least an upper part of a peripheral wall of the second semiconductor layer (left edge of upper part of 1031) at the lower end of the channel portion is substantially aligned with a peripheral wall of the first semiconductor layer at the upper end of the channel portion (left edge of 1005) (see annotated Fig. 18 above, aligned along vertical dotted line.)
With respect to claim 25, Zhu-1 further teaches:
The semiconductor device according to claim 1,
wherein the curved nanosheet/nanowire (channel layer 1059) contains a single crystal material (Para. 21 “The channel layer may be made of a single-crystalline semiconductor material.”)
With respect to claim 26, Zhu-1 further teaches:
The semiconductor device according to claim 1,
wherein a plurality of the semiconductor devices are provided on the substrate (See Fig. 13, there is a left and right device as claimed in claim 1), and the C shapes of at least one pair of the semiconductor devices are opposite to each other (left and right device in Fig. 13).
With respect to claim 27, Zhu-1 further teaches:
The semiconductor device according to claim 26,
wherein channel portions (channel portions 1059 of left and right devices) of the pair of the semiconductor devices are substantially coplanar (Fig. 13).
With respect to claim 28, Zhu-1 further teaches:
The semiconductor device according to claim 27,
wherein source/drain portions of the pair of the semiconductor devices at the upper end (1055 embedded in 1005) are substantially coplanar (See Fig. 13, source is shared between the two devices), and source/drain portions of the pair of the semiconductor devices at the lower end (1055 embedded in 1031) are substantially coplanar (see Fig. 13, 1055 is implanted to substantially the same depth in 1031 on both sides).
With respect to claim 29, Zhu-1 further teaches:
The semiconductor device according to claim 26,
wherein the C shapes of the pair of the semiconductor devices are symmetrical with each other (Fig. 13, mirror symmetric across vertical plane through center of precursor channel layer 1003).
With respect to claim 30, Zhu-1 further teaches:
The semiconductor device according to claim 1,
wherein gate lengths (vertical length of gate conductor layer 1017 within the C of channel layer 1059) of the gate stacks at two opposite sides of the C-shaped curved nanosheet/nanowire (gate conductor layer within left channel and gate conductor layer within right channel) are substantially equal.
With respect to claim 49, Zhu-1 further teaches:
An electronic apparatus, comprising the semiconductor device according to claim 1 (para. 94 “Such an electronic device may comprise, for example, a smart phone, a computer, a tablet Personal Computer (PC), an artificial intelligence, a wearable smart device, a mobile power supply, or the like”)
With respect to claim 50, Zhu-1 further teaches:
The electronic apparatus according to claim 49, comprising a smartphone, a computer, a tablet computer, a wearable smart apparatus, or a portable power supply (para. 94 “Such an electronic device may comprise, for example, a smart phone, a computer, a tablet Personal Computer (PC), an artificial intelligence, a wearable smart device, a mobile power supply, or the like”).
Claims 19-23 are rejected under 35 U.S.C. 103 as being unpatentable over Zhu-1 (US 2018/0097106 A1) in view of Zhu (US 2018/0096896 A1), hereinafter referred to as Zhu-2.
With respect to claim 19, Zhu-1 teaches all limitations of claim 16 upon which claim 19 depends. Zhu-1 fails to teach:
wherein at least a part of the periphery of the gate stack
extends along a corresponding periphery of the first semiconductor layer at the upper end of the channel portion.
Zhu-2 teaches in Fig. 24:
wherein at least a part of the periphery of the gate stack (second gate dielectric 1045)
extends along a corresponding periphery of the first semiconductor layer (third source/drain layer 1011, para. 29 “1011 may comprise the same semiconductor material”) at the upper end of the channel portion (second channel portion 1009).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Zhu-2 into the device of Zhu-1 to include a portion of the gate stack that extends along a periphery of the first semiconductor layer. The ordinary artisan would have been motivated to modify Zhu-1 in the manner set forth above for the purpose of making a stacked semiconductor device with a laterally recessed channel (para. 75 of Zhu-2).
With respect to claim 20, Zhu-1/Zhu-2 further teaches:
wherein a gate conductor layer (second gate conductor layer 1047 of Zhu-2) of the gate stack (gate stack 1045 and 1047 of Zhu-2) further comprises
a part that extends beyond the periphery of the first semiconductor layer (1011) in the lateral direction with respect to the substrate to be used as a pad (Fig. 24, 1047 extends beyond the end of 1011 in the horizontal direction).
With respect to claim 21, Zhu-1 teaches all limitations of claim 15 upon which claim 21 depends. Zhu-1 further teaches:
dielectric layers (dielectric spacer 1061) that are respectively located at the upper end and the lower end of the channel portion with respect to the substrate (Fig. 18),
Zhu-1 fails to teach:
and respectively surround at least a part of a periphery of each of the first semiconductor layer and the second semiconductor layer, wherein the dielectric layers are substantially coplanar with the first semiconductor layer or the second semiconductor layer, respectively.
Zhu-2 teaches:
dielectric layers (second gate dielectric layer 1045 and first gate dielectric layer 1029) that are respectively located at the upper end (channel layer 1009) and the lower end (channel layer 1005) of the channel portion with respect to the substrate (substrate 1001),
and respectively surround at least a part of a periphery of each of the first semiconductor layer (source/drain layer 1011, which may comprise semiconductor material per para. 29) and the second semiconductor layer (source/drain layer 1007, which may comprise semiconductor material per para. 29), wherein the dielectric layers are substantially coplanar with the first semiconductor layer or the second semiconductor layer, respectively (both dielectric layers and both semiconductor layers include points in the cross-section plane shown in Fig. 24.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Zhu-2 into the device of Zhu-1 to include a dielectric layers surrounding a periphery of the semiconductor layers. The ordinary artisan would have been motivated to modify Zhu-1 in the manner set forth above for the purpose of making a stacked semiconductor device with a laterally recessed channel (para. 75 of Zhu-2).
With respect to claim 22, Zhu-1/Zhu-2 further teaches:
wherein at least a part of the periphery of the gate stack (boundary of second gate conductor layer 1047 of Zhu-2) extends along corresponding peripheries of both the dielectric layer (1045 of Zhu-2) and the first semiconductor layer (1011 of Zhu-2) at the upper end of the channel portion (1009 of Zhu-2) (Fig. 24 of Zhu-2).
With respect to claim 23, Zhu-1/Zhu-2 further teaches:
wherein a gate conductor layer of the gate stack (1047 of Zhu-2) further comprises a part that extends beyond the peripheries of both the dielectric layer and the first semiconductor layer at the upper end of the channel portion (thinner portion of 1045 extends beyond the extent of the periphery of 1011 and part of 1045 that surrounds 1011) in the lateral direction (left/right direction) with respect to the substrate (substrate 1001) to be used as a pad.
Response to Arguments
Applicant’s arguments with respect to claims 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant amended to cite “the first sidewall and the second sidewall are arc- shaped sidewalls parallel to each other” and argues that Zhu-1 does not read on the limitation because the channel layer 1059 is straight line shaped. The Examiner takes the position that a broadest reasonable interpretation of “arc-shaped” does not prevent the sidewalls to include straight lines. The definition of “arc-shaped” relied upon is “something arched or curved.” The figure below includes a variety of arches, including a flat arch which appears similar to the cross section of the channel of Zhu-1. The Examiner further notes that although Zhu-1 shows in a plan view that the channel has straight lines and sharp corners, the ordinary artisan would understand that limitations of nanoscale manufacturing processes would prevent the completely straight lines with sharp corners from occurring and that the RIE used to remove the position hold layer followed by deposition or epitaxy to form channel layer 1059 would naturally lead to a curve of the c-shaped channel layer. Arguments are therefore found unpersuasive and new grounds of rejection based on Zhu-1 necessitated by the amendment are introduced.
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Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
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/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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