DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/30/2025 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 2, and 26 have been considered but are moot because of the new ground of rejection.
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, 6-8, 11, 22-23, and 25-26 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura et al. (US 2018/0374529 A1), hereafter “Kimura”, in view of Tsai et al. (US 2007/0020953 A1), hereafter “Tsai”, and further in view of Kim et al. (US 2015/0279857 A1), hereafter “Kim”.
As to claim 1, Kimura teaches a method for manufacturing a memory device, comprising:
forming a first insulator (⁋ [0130], 101A, Fig. 14A) over a substrate (⁋ [0130]);
forming a first conductor (⁋ [0130], 132A, Fig. 14A) over the first insulator;
forming a second insulator (101C) over the first conductor;
forming a third insulator (101D) over the second insulator;
forming a fourth insulator (101E) over the third insulator;
forming a first opening (⁋ [0145], 191, Fig. 14B) penetrating the first insulator, the first conductor, the second insulator, the third insulator, and the fourth insulator;
forming a second opening (⁋ [0147], 192A, Fig. 15A) in the first conductor so as to extend the first opening in the first conductor;
forming, in the first opening and the second opening, a fifth insulator (⁋ [0149], 102, Fig. 15B) covering a side surface of the first insulator, a side surface of the first conductor, a side surface of the second insulator, a side surface of the third insulator, and a side surface of the fourth insulator;
forming a second conductor (⁋⁋ [0150]-[0151], 133, Fig. 16A) in contact with the fifth insulator so as to be embedded in the second opening;
processing the second conductor (⁋ [0153]);
forming a first oxide semiconductor (⁋ [0157], 151, Fig. 17A) in contact with the fifth insulator and the second conductor;
forming a sixth insulator (⁋ [0162], 103, Fig. 17B) in contact with the first oxide semiconductor;
forming a second oxide semiconductor (⁋ [0162], 152, Fig. 17B) in contact with the sixth insulator;
removing the third insulator (⁋ [0179], Fig. 21A, “selectively removed”); and
forming a third conductor (⁋ [0130], 131B, Fig. 14A) between the second insulator and the fourth insulator,
wherein the first conductor (132A) comprises a region configured to function as a first electrode of a capacitor (⁋ [0155], Fig. 16B, “the capacitor CS is formed in a region 181A”),
wherein the second conductor (133a) comprises a first region configured to function as a gate electrode of a first transistor (⁋ [0169], “the conductor 133a (the conductor 133b) function as the gate electrode”) and a second region configured to function as a second electrode of the capacitor (⁋ [0155], “conductor 133a (the conductor 133b) functions as the other electrode of the capacitor CS”),
wherein the third conductor (131A) comprises a region configured to function as a gate electrode of a second transistor (⁋ [0136], “The conductor 131A (the conductor 131B) functions as the wiring WWL in FIG. 1C”; Examiner notes Fig. 1C shows WWL configured to function as the gate electrode of WTr),
wherein the first oxide semiconductor (151) comprises a region configured to function as a channel formation region of the second transistor (⁋ [0164], “the region 151a of the semiconductor 151 functions as the channel formation region”),
wherein the second oxide semiconductor (152) comprises a region configured to function as a channel formation region of the first transistor (⁋ [0169], “the semiconductor 152 functions as the channel formation region”),
wherein the fifth insulator (102) comprises a region configured to function as a gate insulator of the second transistor (one skilled in the art would understand that since 102 separates semiconductor 151 and gate 131A that 102 serves as the gate insulating layer),
wherein the sixth insulator (103) comprises a region configured to function as a gate insulator of the first transistor (⁋ [0169], Fig. 18A, 133a+151a+15b serve as the gate electrode, and 152 as the channel of transistor RTr, one skilled in the art would understand that the insulating layer 103 therebetween would serve as the gate insulating layer).
Kimura fails to teach wherein the fifth insulator is formed by performing, a plurality of times, a cycle comprising: a first step of supplying a gas including silicon and an oxidizing gas into a chamber where the substrate is placed; a second step of stopping the supply of the gas including silicon into the chamber; and a third step of generating plasma including the oxidizing gas in the chamber, and processing the second conductor so as not to be positioned in the first opening.
Tsai teaches a method of creating an insulating layer which comprises of a first step (⁋[0035], 514+518 or 522, Fig. 7) of supplying a gas including silicon (⁋ [0022], 30, “first gas”) and an oxidizing gas (⁋[0024], 32, second gas) into a chamber where the substrate is placed;
a second step (516 or 526) of stopping the supply of the gas including silicon into the chamber; and
a third step (518 or 528) of generating plasma including the oxidizing gas in the chamber.
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the dielectric layer formation steps as taught by Tsai with the manufacturing method of Kimura to form dielectric films having high density and improved adhesion with adjacent layers (⁋ [0018]).
Additionally, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103."KSR, 550 U.S. at 421, 82 USPQ2d at 1397.
Kimura and Tsai fail to teach processing the second conductor so as not to be positioned in the first opening.
Kim teaches a similar device with a trench/opening (⁋ [0065], 150, Fig. 13A) with an insulator (⁋ [0062], 168, Fig. 14A) and conductive layer (⁋ [0096], 170) within the opening and the conductive layer is processed to form gate electrodes (⁋ [0098], 172, Fig. 15A) truncated/not positioned in the opening.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the truncated conductor teaching of Kim to the method of Kimura and Tsai so the gate electrodes adjacent to each other in the third direction may be physically separated from each other to reduce or prevent a short between the gate electrodes (⁋ [0098]).
As to claim 2, Kimura teaches a method for manufacturing a memory device, comprising:
forming a first insulator (⁋ [0130], 101A, Fig. 14A) over a substrate (⁋ [0130]);
forming a first conductor (⁋ [0130], 132A, Fig. 14A) over the first insulator;
forming a second insulator (101C) over the first conductor;
forming a third insulator (101D) over the second insulator;
forming a fourth insulator (101E) over the third insulator;
forming an opening (⁋ [0145], 191, Fig. 14B) penetrating the first insulator, the first conductor, the second insulator, the third insulator, and the fourth insulator;
forming a depressed portion of the first conductor (⁋ [0147], 192A, Fig. 15A) so as to extend the opening in the first conductor;
forming, in the opening and the depressed portion of the first conductor, a fifth insulator (⁋ [0149], 102, Fig. 15B) covering a side surface of the first insulator, a side surface of the first conductor, a side surface of the second insulator, a side surface of the third insulator, and a side surface of the fourth insulator;
forming a second conductor (⁋⁋ [0150]-[0151], 133, Fig. 16A) between the first insulator and the second insulator;
forming a first oxide semiconductor (⁋ [0157], 151, Fig. 17A) in contact with the fifth insulator and the second conductor;
forming a sixth insulator (⁋ [0162], 103, Fig. 17B) in contact with the first oxide semiconductor;
forming a second oxide semiconductor (⁋ [0162], 152, Fig. 17B) in contact with the sixth insulator;
removing the third insulator (⁋ [0179], Fig. 21A, “selectively removed”); and
forming a third conductor (⁋ [0130], 131B, Fig. 14A) between the second insulator and the fourth insulator,
wherein the first conductor (132A) comprises a region configured to function as a first electrode of a capacitor (⁋ [0155], Fig. 16B, “the capacitor CS is formed in a region 181A”),
wherein the second conductor (133a) comprises a first region configured to function as a gate electrode of a first transistor (⁋ [0169], “the conductor 133a (the conductor 133b) function as the gate electrode”) and a second region configured to function as a second electrode of the capacitor (⁋ [0155], “conductor 133a (the conductor 133b) functions as the other electrode of the capacitor CS”),
wherein the third conductor (131A) comprises a region configured to function as a gate electrode of a second transistor (⁋ [0136], “The conductor 131A (the conductor 131B) functions as the wiring WWL in FIG. 1C”; Examiner notes Fig. 1C shows WWL configured to function as the gate electrode of WTr),
wherein the first oxide semiconductor (151) comprises a region configured to function as a channel formation region of the second transistor (⁋ [0164], “the region 151a of the semiconductor 151 functions as the channel formation region”),
wherein the second oxide semiconductor (152) comprises a region configured to function as a second channel formation region of the first transistor (⁋ [0169], “the semiconductor 152 functions as the channel formation region”),
wherein the fifth insulator (102) comprises a region configured to function as a gate insulator of the second transistor (one skilled in the art would understand that since 102 separates semiconductor 151 and gate 131A that 102 serves as the gate insulating layer),
wherein the sixth insulator (103) comprises a region configured to function as a gate insulator of the first transistor (⁋ [0169], Fig. 18A, 133a+151a+15b serve as the gate electrode, and 152 as the channel of transistor RTr, one skilled in the art would understand that the insulating layer 103 therebetween would serve as the gate insulating layer).
Kimura fails to teach wherein the fifth insulator is formed by performing, a plurality of times, a cycle comprising: a first step of supplying a gas including silicon and an oxidizing gas into a chamber where the substrate is placed; a second step of stopping the supply of the gas including silicon into the chamber; and a third step of generating plasma including the oxidizing gas in the chamber, forming a second conductor so as not to be positioned in the opening.
Tsai teaches a method of creating an insulating layer which comprises of a first step (⁋[0035], 514+518 or 522, Fig. 7) of supplying a gas including silicon (⁋ [0022], 30, “first gas”) and an oxidizing gas (⁋[0024], 32, second gas) into a chamber where the substrate is placed;
a second step (516 or 526) of stopping the supply of the gas including silicon into the chamber; and
a third step (518 or 528) of generating plasma including the oxidizing gas in the chamber.
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the dielectric layer formation steps as taught by Tsai with the manufacturing method of Kimura to form dielectric films having high density and improved adhesion with adjacent layers (⁋ [0018]).
Additionally, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103."KSR, 550 U.S. at 421, 82 USPQ2d at 1397.
Kimura and Tsai fail to teach forming a second conductor so as not to be positioned in the opening.
Kim teaches a similar device with a trench/opening (⁋ [0065], 150, Fig. 13A) with an insulator (⁋ [0062], 168, Fig. 14A) and conductive layer (⁋ [0096], 170) within the opening and the conductive layer is processed to form gate electrodes/conductor (⁋ [0098], 172, Fig. 15A) truncated/not positioned in the opening.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the truncated conductor teaching of Kim to the method of Kimura and Tsai so the gate electrodes adjacent to each other in the third direction may be physically separated from each other to reduce or prevent a short between the gate electrodes (⁋ [0098]).
As to claim 3, The method for manufacturing a memory device, according to claim 1,
Tsai teaches wherein the gas including silicon is SiH4 (⁋ [0022]).
As to claim 4, The method for manufacturing a memory device, according to claim 1,
Tsai teaches wherein the oxidizing gas is N2O (⁋ [0024]).
As to claim 6, The method for manufacturing a memory device according 1,
Kimura teaches wherein the first oxide semiconductor includes indium, an element M, and zinc, and
wherein the element M is one or more selected from aluminum, gallium (⁋ [0138], indium gallium zinc oxide), yttrium, tin, and titanium.
As to claim 7, The method for manufacturing a memory device, according to claim 1,
Kimura teaches wherein the first oxide semiconductor has crystallinity (⁋ [0242]).
As to claim 8, The method for manufacturing a memory device, according to claim 1,
Kimura teaches wherein the first oxide semiconductor includes a region where a c-axis is aligned with a direction normal to a side surface of the third conductor, in the first opening (⁋⁋ [0239]-[0240]; 151 perpendicular to a side surface of 133a).
As to claim 11, The method for manufacturing a memory device, according to claim 2,
Kimura teaches wherein the first oxide semiconductor has crystallinity (⁋ [0242]).
As to claim 22, The method for manufacturing a memory device, according to claim 2,
Tsai teaches wherein the gas including silicon is SiH4 (⁋ [0022]).
As to claim 23, The method for manufacturing a memory device, according to claim 2,
Tsai teaches wherein the oxidizing gas is N2O (⁋ [0024]).
As to claim 25, The method for manufacturing a memory device according to claim 1,
Kimura teaches wherein the first oxide semiconductor includes indium, an element M, and zinc, and wherein the element M is one or more selected from aluminum, gallium (⁋ [0138], indium gallium zinc oxide), yttrium, tin, and titanium.
As to claim 26, Kimura teaches a method for manufacturing a memory device, comprising:
forming a first insulator (⁋ [0130], 101A, Fig. 14A) over a substrate (⁋ [0130]);
forming a first conductor (⁋ [0130], 132A, Fig. 14A) over the first insulator;
forming a second insulator (101C) over the first conductor;
forming a third insulator (101D) over the second insulator;
forming an opening (⁋ [0145], 191, Fig. 14B) penetrating the first insulator, the first conductor, the second insulator, and the third insulator;
forminq a depressed portion of the first conductor (⁋ [0147], 192A, Fig. 15A) so as to extend the opening in the first conductor;
forming, in the opening and the depressed portion of the first conductor, a fourth insulator (⁋ [0149], 102, Fig. 15B) covering a side surface of the first insulator, a side surface of the first conductor, a side surface of the second insulator, and a side surface of the third insulator;
forming a second conductor (⁋⁋ [0150]-[0151], 133, Fig. 16A) between the first insulator and the second insulator;
forming a first oxide semiconductor (⁋ [0157], 151, Fig. 17A) in contact with the fourth insulator and the second conductor;
forming a fifth insulator (⁋ [0162], 103, Fig. 17B) in contact with the first oxide semiconductor;
forming a second oxide semiconductor (⁋ [0162], 152, Fig. 17B) in contact with the fifth insulator; and
forming a third conductor (⁋ [0130], 131B, Fig. 14A) between the second insulator and the third insulator,
wherein the first conductor (132A) comprises a region configured to function as a first electrode of a capacitor (⁋ [0155], Fig. 16B, “the capacitor CS is formed in a region 181A”),
wherein the second conductor (133a) comprises a first region configured to function as a gate electrode of a first transistor (⁋ [0169], “the conductor 133a (the conductor 133b) function as the gate electrode”) and a second region configured to function as a second electrode of the capacitor (⁋ [0155], “conductor 133a (the conductor 133b) functions as the other electrode of the capacitor CS”),
wherein the third conductor (131A) comprises a region configured to function as a gate electrode of a second transistor (⁋ [0136], “The conductor 131A (the conductor 131B) functions as the wiring WWL in FIG. 1C”; Examiner notes Fig. 1C shows WWL configured to function as the gate electrode of WTr),
wherein the first oxide semiconductor (151) comprises a region configured to function as a channel formation region of the second transistor (⁋ [0164], “the region 151a of the semiconductor 151 functions as the channel formation region”),
wherein the second oxide semiconductor (152) comprises a region configured to function as a channel formation region of the first transistor (⁋ [0169], “the semiconductor 152 functions as the channel formation region”),
wherein the fourth insulator (102) comprises a region configured to function as a gate insulator of the second transistor (one skilled in the art would understand that since 102 separates semiconductor 151 and gate 131A that 102 serves as the gate insulating layer),
wherein the fifth insulator (103) comprises a region configured to function as a gate insulator of the first transistor (⁋ [0169], Fig. 18A, 133a+151a+15b serve as the gate electrode, and 152 as the channel of transistor RTr, one skilled in the art would understand that the insulating layer 103 therebetween would serve as the gate insulating layer).
Kimura fails to teach wherein the formation of the fourth insulator comprises: a first step of supplying a gas including silicon and an oxidizing gas into a chamber where the substrate is placed; a second step of stopping the supply of the gas including silicon into the chamber; and a third step of generating plasma including the oxidizing gas in the chamber, forming a second conductor so as not to be positioned in the opening.
Tsai teaches a method of creating an insulating layer which comprises of a first step (⁋[0035], 514+518 or 522, Fig. 7) of supplying a gas including silicon (⁋ [0022], 30, “first gas”) and an oxidizing gas (⁋[0024], 32, second gas) into a chamber where the substrate is placed;
a second step (516 or 526) of stopping the supply of the gas including silicon into the chamber; and
a third step (518 or 528) of generating plasma including the oxidizing gas in the chamber.
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the dielectric layer formation steps as taught by Tsai with the manufacturing method of Kimura to form dielectric films having high density and improved adhesion with adjacent layers (⁋ [0018]).
Additionally, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103."KSR, 550 U.S. at 421, 82 USPQ2d at 1397.
Kimura and Tsai fail to teach forming a second conductor so as not to be positioned in the opening.
Kim teaches a similar device with a trench/opening (⁋ [0065], 150, Fig. 13A) with an insulator (⁋ [0062], 168, Fig. 14A) and conductive layer (⁋ [0096], 170) within the opening and the conductive layer is processed to form gate electrodes/conductor (⁋ [0098], 172, Fig. 15A) truncated/not positioned in the opening.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the truncated conductor teaching of Kim to the method of Kimura and Tsai so the gate electrodes adjacent to each other in the third direction may be physically separated from each other to reduce or prevent a short between the gate electrodes (⁋ [0098]).
Claims 5 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura in view of Tsai and Kim as applied to claims 1 and 2, and further in view of Koyama et al. (US 2011/0248970 A1), hereafter “Koyama”.
As to claim 5, The method for manufacturing a memory device according to claim 1,
Kimura in view of Tsai and Kim fail to disclose wherein He is supplied into the chamber in the first step.
Koyama teaches an insulating layer formation with a plasma treatment utilizing He (⁋ [0272]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the Helium gas of Koyama into the chamber of the manufacturing process of Kimura, Tsai and Kim to generate a plasma with a low electron temperature and high density (⁋ [0272]).
As to claim 24, The method for manufacturing a memory device, according to claim 2,
Kimura in view of Tsai and Kim fail to teach wherein He is supplied into the chamber in the first step.
Koyama teaches an insulating layer formation with a plasma treatment utilizing He (⁋ [0272]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the Helium gas of Koyama into the chamber of the manufacturing process of Kimura, Tsai and Kim to generate a plasma with a low electron temperature and high density (⁋ [0272]).
Claims 9 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura in view of Tsai and Kim as applied to claims 1 and 2, and further in view of Koezuka et al. (US 2017/0104090 A1), hereafter “Koezuka”.
As to claim 9, The method for manufacturing a memory device, according to claim 1,
Kimura in view of Tsai and Kim fail to teach wherein the fifth insulator includes a region with a nitrogen concentration of higher than or equal to 3 x 1019 atoms/cm3 and lower than or equal to 1 x 1021 atoms/cm3.
Koezuka teaches an insulator where the concentration of nitrogen is lower than 6×1020 atoms/cm3 (⁋ [0319]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize the range of Koezuka for the insulator of Kimura, Tsai and Kim because in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art”, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ 2d 1934 (Fed. Cir. 1990). MPEP 2144.05.
As to claim 13, The method for manufacturing a memory device, according to claim 2,
Kimura in view of Tsai and Kim fail to teach wherein the fifth insulator includes a region with a nitrogen concentration of higher than or equal to 3 x 1019 atoms/cm3 and lower than or equal to 1 x 1021 atoms/cm3.
Koezuka teaches an insulator where the concentration of nitrogen is lower than 6×1020 atoms/cm3 (⁋ [0319]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize the range of Koezuka for the insulator of Kimura, Tsai and Kim because in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art”, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ 2d 1934 (Fed. Cir. 1990). MPEP 2144.05.
Claims 10 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura in view of Tsai and Kim as applied to claims 1 and 2, and further in view of Suzawa et al. (US 2019/0181159 A1), hereafter “Suzawa”.
As to claim 10, The method for manufacturing a memory device, according to claim 1,
Kimura in view of Tsai and Kim fail to teach wherein the fifth insulator includes a region with a carbon concentration of higher than or equal to 1 x 1018 atoms/cm3 and lower than or equal to 5 x 1020 atoms/cm3.
Suzawa teaches an insulator where the concentration of carbon is higher than 1×1016 atoms/cm3 and lower than 1×1019 atoms/cm3 (⁋ [0176]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize the range of Suzawa for the insulator of Kimura, Tsai and Kim because in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art”, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ 2d 1934 (Fed. Cir. 1990). MPEP 2144.05.
As to claim 14, The method for manufacturing a memory device, according to claim 2,
Kimura in view of Tsai and Kim fail to teach wherein the fifth insulator includes a region with a carbon concentration of higher than or equal to 1 x 1018 atoms/cm3 and lower than or equal to 5 x 1020 atoms/cm3.
Suzawa teaches an insulator where the concentration of carbon is higher than 1×1016 atoms/cm3 and lower than 1×1019 atoms/cm3 (⁋ [0176]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize the range of Suzawa for the insulator of Kimura, Tsai and Kim because in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art”, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ 2d 1934 (Fed. Cir. 1990). MPEP 2144.05.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kimura in view of Tsai and Kim as applied to claims 1 and 2, and further in view of Yamazaki et al. (US 2020/0381556 A1), hereafter “Yamazaki”.
As to claim 12, The method for manufacturing a memory device, according to claim 2,
Kimura in view of Tsai and Kim fail to teach wherein the oxide semiconductor includes a region where a c-axis is aligned with a direction normal to a side surface of at least one of the first conductor and the third conductor, in the opening.
Yamazaki teaches a memory device (⁋ [0002]) with an oxide semiconductor (⁋ [0084], 12+13, Fig. 1A) formed in an opening, and a conductor (⁋ [0082], 14a+14b) formed on the sides of the semiconductor layer, wherein a c-axis of the oxide semiconductor is aligned with a direction normal to a side surface of the conductor (⁋ [0097], “the oxide 13 includes the region where the c-axis 13b is aligned substantially perpendicularly to the side surface of the conductor 14a and the region where the c-axis 13b is aligned substantially perpendicularly to the side surface of the conductor 14b”).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the c-axis alignment taught by Yamazaki with the method taught by Kimura, Tsai and Kim to ensure the on-state current, the S value, and the frequency characteristic can be prevented from being lower than the design values (⁋ [0097]).
Conclusion
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/CARNELL HUNTER III/Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893