DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on June 10th 2022, September 5th 2024, and October 10th 2024 has been considered by the examiner.
Status of the Claims
Claims 1, 10, and 17 are amended. Claims 1-20 are present for examination.
Specification
The specification objection of May 07, 2025 has been withdrawn.
Claim Rejections - 35 USC § 112
The 25 U.S.C. 112(b) rejections of May 07, 2025 has been withdrawn.
Response to Arguments
Applicant’s arguments, see pages 9-12, filed November 07, 2025, with respect to the rejection(s) of claim(s) 1-9 and 16-20 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection of (I) claims 1-2, 5-8, 16, 17, and 19 is made in view of Im in view of Wu and (II) claim 3-4, 9, 18, and 20 is made in view of Im in view of Wu and further in view of Cho.
Wu discloses a display array further including electrodes (Wu, display array 100L further including electrode pads 130 and electrode layer 160, [0043], Fig. 14; Im, [0103], Fig. 4) and a bank pattern (Wu, insulating layer 120 is a bank pattern, [0051], Fig. 14; Im, bank pattern 305, [0103], Fig. 4) the bank pattern having a bar shape with a length extending along the direction (Wu, bank pattern 120 has a length which extends along a direction having a bar shape (i.e. a rectangular bar shape extends in three directions; into the page, horizontally, and vertically), [0051], Fig. 14; Im, bank pattern 305, [0103], Fig. 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-8, 16, 17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Im (US 2019/0326348 A1) in view of Wu (US 2019/0355785 A1).
Claim 1, Im discloses a display device (Figs. 1 and 3-4) comprising:
a substrate (substrate 301, Fig. 3, para [0076]) including a display area (display panel 111 has a display area, para [0054], Fig. 1) including a plurality of pixel areas PX (111 includes a plurality of pixels PX/LED where each pixel PX/LED has a pixel area PX between first and second driving electrodes 351/352, para [0173], Fig. 3) and a non-display area surrounding the display area PX (each display area PX is surrounded with a non-display area which includes data line DL and scan line SL, Figs. 1 and 2); and
a pixel PX/LED disposed in each of the pixel areas PX (a pixel PX/LED is disposed in each of the pixel areas PX, Fig. 3),
wherein the pixel PX comprises:
at least one transistor (first and second switching elements Tr1/Tr2 are transistors, para [0069], Fig. 2) and a driving voltage line VDL/VSL (driving power line VDL/VSL is connected to Tr2 within PX, Fig. 2, para [0071]) disposed on the substrate 301 (Fig. 2 is a plan view where the substrate 301 is the bottom of the stack as seen in Figs. 3 and 4, para [0076]);
a first electrode and a second electrode (second source electrode SE2 is the first electrode and second drain electrode DE2 is the second electrode, para [0079], Fig. 4) extending in a direction (SE2/DE2 extend parallel to the (I-I’) x-direction, Figs. 3 and 4) on the transistor Tr2 and the driving voltage line VDL and spaced apart from each other (first and second electrodes SE2/DE2 are spaced apart from each other in the x-direction, Fig. 4);
a bank pattern (planarization layer 305 is equivalent to a bank pattern, para [0103]) disposed on the first and second electrodes SE2/DE2, respectively (305 is disposed on SE2 and DE2, respectively, para [0103], Fig. 4);
intermediate layers (insulating layer 366 may include a plurality of insulating layers 306/307, para [0111], Fig. 4) disposed on the bank pattern 305 (306/307 are disposed on 305, para [0112], Fig. 4);
light emitting elements (LED is a light emitting element, para [0003]) disposed between two adjacent intermediate layers of the intermediate layers 306/307 in another direction intersecting the direction (light emitting element LED disposed between two adjacent intermediate layers 306/307 wherein the first adjacent intermediate layer is on the left-hand side and the second adjacent intermediate layer is on the right-hand side, Annotated Fig. 4);
a first contact electrode (first connection electrode 371 is a first contact electrode, para [0129], Fig. 4) disposed on one of the two adjacent intermediate layers 306/307 (371 is disposed on 307 within the second adjacent intermediate layers, para [0129], Annotated Fig. 4) and electrically connected to an end of each of the light emitting elements LED (371 is electrically connected to the first electrode 411 of the light-emitting element LED, para [0129], Figs. 4 and 5); and
a second contact electrode (second connection electrode 372 is a second contact electrode, para [0132], Fig. 4) disposed on another one of the two adjacent intermediate layers 306/307 (372 is disposed on 307 within the first adjacent intermediate layers, para [0131], Annotated Fig. 4) and electrically connected to another end of each of the light emitting elements LED (372 is electrically connected to the second electrode 412 of the light emitting element LED, para [0132], Annotated Fig. 4 and Fig. 5).
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Annotated Fig. 4 (Im) – Illustrates a light emitting element LED disposed between two adjacent intermediate layers 306/307 wherein the first adjacent intermediate layer is on the left-hand side and the second adjacent intermediate layer is on the right-hand side
Im does not explicitly disclose a bank pattern disposed on the first and second electrodes, respectively.
However, Im discloses (Fig. 4) a planarization layer 305 disposed on the first and second electrodes SE2/DE2, respectively. While the planarization layer is not explicitly disclosed as a bank pattern, planarization layer functions as such. Im describes the details of the planarization layer in para [0103-0104] as planarization layer may include a single or multiple-layer structure including either an organic, inorganic, or organic/inorganic composite and serve to improve luminous efficiency of the LED. This function corresponds to that of the bank pattern disclosed by the applicants in the instant application in para [0198] as to change a surface profile so that light emitted from the light emitting elements further travels in a direction normal to the pixel area.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize a planarization layer as a bank pattern. The motivation to do so is that the combination allows for changing a surface profile of the display device so that light emitted from the light emitting elements further travels in a direction normal to the pixel area such that luminous efficiency of the light emitting element is improved.
Im does not explicitly disclose the bank pattern having a bar shape with a length extending along the direction.
However, Wu discloses a display array further including electrodes (Wu, display array 100L further including electrode pads 130 and electrode layer 160, [0043], Fig. 14; Im, [0103], Fig. 4) and a bank pattern (Wu, insulating layer 120 is a bank pattern, [0051], Fig. 14; Im, bank pattern 305, [0103], Fig. 4) the bank pattern having a bar shape with a length extending along the direction (Wu, bank pattern 120 has a length which extends along a direction having a bar shape (i.e. a rectangular bar shape extends in three directions; into the page, horizontally, and vertically), [0051], Fig. 14; Im, bank pattern 305, [0103], Fig. 4). The combination to utilize an additional insulating bank pattern in combination with the electrodes allows for reduced edge light emitting efficiency deterioration (Wu, [0006]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an additional insulating bank pattern in combination with the electrodes allows for reduced edge light emitting efficiency deterioration (Wu, [0006]).
Claim 2, Im/Wu discloses the display device (Im, Fig. 4; Wu, Fig. 14) according to claim 1, wherein each of the intermediate layers 306/307 includes an insulating material (Im, insulating layers 306/307 may be silicon oxide, silicon nitride, or a metal oxide, all of which are insulating materials, para [0086], Fig. 4; Wu, Fig. 14).
Claim 5, Im/Wu discloses the display device (Im, Fig. 4; Wu, Fig. 14) according to claim 1, wherein
one of the first (Im, first connection electrode 371 is a first contact electrode, para [0129], Fig. 4; Wu, Fig. 14) and second contact electrodes (Im, second connection electrode 372 is a second contact electrode, para [0132], Fig. 4; Wu, Fig. 14) is electrically connected to the transistor Tr2 (Im, 371 is electrically connected to the transistor Tr2, para [0071], Fig. 4; Wu, Fig. 14), and
another one of the first 371 and second contact electrodes 372 is electrically connected to the driving voltage line VSL (Im, 372 is electrically connected to VSL, para [0132], Fig. 4; Wu, Fig. 14).
Claim 6, Im/Wu discloses the display device (Im, Fig. 4; Wu, Fig. 14) according to claim 5, wherein the first contact electrode 371 and the second contact electrode 372 are disposed on a same layer (371/371 are disposed on insulating layer 307, Fig. 4).
Claim 7, Im/Wu discloses the display device (Im, Fig. 4; Wu, Fig. 14) according to claim 5, wherein the first contact electrode 371 and the second contact electrode 372 are disposed on different layers (Im, 372 is disposed on extension electrode 340 while 371 is disposed on first alignment electrode 341, para [0105], Fig. 4; Wu, Fig. 14).
Claim 8, Im/Wu discloses the display device (Im, Fig. 3; Wu, Fig. 14) according to claim 1, wherein each of the first SE2 and second electrodes DE2 extends in the direction (Im, SE2/DE2 extend parallel to the (I-I’) x-direction, Figs. 3 and 4; Wu, Fig. 14) and is commonly provided to adjacent pixels LED positioned in a same pixel column PX1/PX2/PX3 as the pixel LED (Im, SE2/DE2 extend in both the x and y-directions, Figs. 3 and 4; Wu, Fig. 14).
Claim 16, Im/Wu discloses the display device (Im, Figs. 3 and 4; Wu, Fig. 14) according to claim 1, wherein the intermediate layers 306/307 overlap the first and second electrodes SE2/DE2 in a plan view (Im, 306/307 are disposed on top of SE2/DE2 and overlap in a plan view, Figs. 3 and 4; Wu, Fig. 14).
Claim 17, Im discloses a method of manufacturing a display device (Figs. 1, 2, 3 and 4), the method comprising:
providing a pixel PX disposed in each pixel area PX (a pixel PX/LED is disposed in each of the pixel areas PX, Fig. 3);
the providing of the pixel PX comprises:
forming at least one transistor (first and second switching elements Tr1/Tr2 are transistors, para [0069], Fig. 2) and a driving voltage line (driving power line VDL/VSL is connected to Tr2 within PX, Fig. 2, para [0071]) on a substrate (substrate 301, para [0076]);
forming an interlayer insulating layer (insulating interlayer 304, para [0167], Fig. 4) on the at least one transistor Tr1/Tr2 and the driving voltage line VSL (304 is formed on Tr1/Tr2 and VSL, para [0160], Fig. 4);
forming a first electrode and a second electrode (second source electrode SE2 is the first electrode and second drain electrode DE2 is the second electrode, para [0079], Fig. 4) extending in a direction (SE2/DE2 extend parallel to the (I-I’) x-direction, Figs. 3 and 4) and spaced apart from each other on the interlayer insulating layer 304 (SE2/DE2 are spaced apart from each other on 304, Fig. 4);
forming a bank pattern (planarization layer 305 is equivalent to a bank pattern, para [0103]) on the first and second electrodes SE2/DE2 (305 is disposed on SE2 and DE2, para [0103], Fig. 4);
forming intermediate layers (insulating layer 366 may include a plurality of insulating layers 306/307, para [0111], Fig. 4) on the bank pattern 305 (306/307 are disposed on 305, para [0112], Fig. 4);
inputting light emitting elements (LED is a light emitting element, para [0003]), and aligning the light emitting elements between two adjacent intermediate layers 306/307 of the intermediate layers adjacent in another direction intersecting the direction (light emitting element LED disposed between two adjacent intermediate layers 306/307 wherein the first adjacent intermediate layer is on the left-hand side and the second adjacent intermediate layer is on the right-hand side, Annotated Fig. 4), by applying an alignment signal corresponding to each of the first electrode and the second electrode (first and second alignment electrodes 341/342 are used to apply an alignment signal Sa1/Sa2 to that which is electrically connected via contact holes 50/60/70, para [0177], Figs. 8A and 8B);
forming an insulating layer (insulating layer 470, para [0142], Figs. 4 and 5) on an upper surface of each of the light emitting elements (LED is oriented with electrodes 411/412 facing horizontally, where 470 is formed on an upper surface, para [0142], Figs. 4 and 5); and
forming a first contact electrode (first connection electrode 371 is a first contact electrode, para [0129], Fig. 4) and a second contact electrode (second connection electrode 372 is a second contact electrode, para [0132], Fig. 4) on the insulating layer 470 (371/372 is formed on 470 of LED, Figs. 4 and 5).
Im does not explicitly disclose a bank pattern disposed on the first and second electrodes.
However, Im discloses (Fig. 4) a planarization layer 305 disposed on the first and second electrodes SE2/DE2, respectively. While the planarization layer is not explicitly disclosed as a bank pattern, planarization layer functions as such. Im describes the details of the planarization layer in para [0103-0104] as planarization layer may include a single or multiple-layer structure including either an organic, inorganic, or organic/inorganic composite and serve to improve luminous efficiency of the LED. This function corresponds to that of the bank pattern disclosed by the applicants in the instant application in para [0198] as to change a surface profile so that light emitted from the light emitting elements further travels in a direction normal to the pixel area.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize a planarization layer as a bank pattern. The motivation to do so is that the combination allows for changing a surface profile of the display device so that light emitted from the light emitting elements further travels in a direction normal to the pixel area such that luminous efficiency of the light emitting element is improved.
Im does not explicitly disclose the bank pattern having a bar shape with a length extending along the direction.
However, Wu discloses a display array further including electrodes (Wu, display array 100L further including electrode pads 130 and electrode layer 160, [0043], Fig. 14; Im, [0103], Fig. 4) and a bank pattern (Wu, insulating layer 120 is a bank pattern, [0051], Fig. 14; Im, bank pattern 305, [0103], Fig. 4) the bank pattern having a bar shape with a length extending along the direction (Wu, bank pattern 120 has a length which extends along a direction having a bar shape (i.e. a rectangular bar shape extends in three directions; into the page, horizontally, and vertically), [0051], Fig. 14; Im, bank pattern 305, [0103], Fig. 4). The combination to utilize an additional insulating bank pattern in combination with the electrodes allows for reduced edge light emitting efficiency deterioration (Wu, [0006]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an additional insulating bank pattern in combination with the electrodes allows for reduced edge light emitting efficiency deterioration (Wu, [0006]).
Claim 19, Im/Wu discloses the method (Im, Fig. 4; Wu, Fig. 14) according to claim 17, wherein each of the intermediate layers 306/307 includes an insulating material (Im, insulating layers 306/307 may be silicon oxide, silicon nitride, or a metal oxide, all of which are insulating materials, para [0086], Fig. 4; Wu, Fig. 14).
Claim 3-4, 9, 18, and 20 is rejected under 35 U.S.C. 103 as being unpatentable over Im in view of Wu and further in view of Cho (WO 2019/208880 A1).
Claim 3, Im/Wu discloses the display device (Im, Figs. 3 and 4; Wu, Fig. 14) according to claim 2.
Im/Wu does not explicitly disclose wherein each of the intermediate layers is a multi-layer including at least three or more double layers formed by stacking a first inorganic insulating layer and a second inorganic insulating layer, and the at least three or more double layers are sequentially stacked.
However, Cho discloses (Cho, Figs. 7 and 8; Im, Figs. 3 and 4; Wu, Fig. 14) wherein each of the intermediate layers (Cho, third insulating layer INS3 is an intermediate layer, para [0118], Fig. 8; Im, Figs. 3 and 4; Wu, Fig. 14) is a multi-layer including at least three or more double layers formed by stacking a first inorganic insulating layer and a second inorganic insulating layer (Cho, INS3 is formed of multiple layers and may have a plurality of inorganic and organic insulating films which alternate, specifically, stacking a first inorganic insulating layer then first organic insulating layer, followed by a second inorganic insulating layer then second organic insulating layer sequentially laminated, para [0118], Fig. 8; Im, Figs. 3 and 4; Wu, Fig. 14), and the at least three or more double layers are sequentially stacked (Cho, plurality of double layers of INS3 are sequentially stacked, para [0118], Fig. 8; Im, Figs. 3 and 4; Wu, Fig. 14). The combination to utilize stacked insulating layers to control reflectivity of the surface of the display device by alternating refractive indices of the surface as well as protect elements that are further encapsulated by the layer (Cho, para [0225]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize stacked insulating layers to control reflectivity of the surface of the display device by alternating refractive indices of the surface as well as protect elements that are further encapsulated by the layer (Cho, para [0225]).
Claim 4, Im/Wu/Cho discloses the display device (Cho, Figs. 7 and 8; Im, Fig. 4; Wu, Fig. 14) according to claim 3.
Im/Wu/Cho discloses (Wu, Figs. 1C to 1E; Cho, Fig. 8; Im, Fig. 4) a refractive index of the first inorganic insulating layer and a refractive index of the second inorganic insulating layer are different from each other (Wu, Fig. 1E, first insulating layer 122 is a light absorbing/reflective insulating material consisting of a plurality of coating films having different refractive indices to render a reflecting effect, para [0032]; Cho, Fig. 8; Im, Fig. 4).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize stacked insulating layers to control reflectivity of the surface of the display device by alternating refractive indices to render a reflecting effect (Wu, Fig. 1E, para [0032]; Cho, Fig. 8; Im, Fig. 4).
Claim 9, Im/Wu/Cho discloses the display device (Cho, Figs. 7 and 8; Im, Fig. 4; Wu, Fig. 14) according to claim 1.
Im/Wu/Cho discloses (Cho, Fig. 8; Im, Fig. 4; Wu, Fig. 14) wherein each of the intermediate layers INS3 includes a conductive material (Cho, INS3 is formed of inorganic and organic insulating films which include conductive materials, para [0118], Fig. 8; Im, Fig. 4; Wu, Fig. 14).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Cho, including the specific conductive material of the intermediate layer, to the teachings of Im. Wherein a conductive metal oxide material is chosen for the intermediate layers. The motivation to do so is that the combination allowing for the selection of a known conductive material based on its suitability for the intended use as a light controlling intermediate layer in a light-emitting display device.
Claim 18, Im/Wu discloses (Im, Fig. 4; Wu, Fig. 14) the method according to claim 17.
Im/Wu does not explicitly disclose wherein each of the intermediate layers includes a conductive material.
However, Cho discloses (Cho, Fig. 8; Im, Fig. 4; Wu, Fig. 14) wherein each of the intermediate layers INS3 includes a conductive material (Cho, INS3 is formed of inorganic and organic insulating films which include conductive materials, para [0118], Fig. 8; Im, Fig. 4; Wu, Fig. 14).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Cho, including the specific conductive material of the intermediate layer, to the teachings of Im. Wherein a conductive metal oxide material is chosen for the intermediate layers. The motivation to do so is that the combination allowing for the selection of a known conductive material based on its suitability for the intended use as a light controlling intermediate layer in a light-emitting display device.
Claim 20, Im/Wu/Cho discloses (Im, Fig. 4; Cho, Fig. 8; Wu, Fig. 14) the method according to claim 19.
Im does not explicitly disclose wherein each of the intermediate layers includes a multi-layer including at least three or more double layers formed by stacking a first inorganic insulating layer and a second inorganic insulating layer, the at least three or more double layers are sequentially stacked, and a refractive index of the first inorganic insulating layer and a refractive index of the second inorganic insulating layer are different from each other.
However, Cho discloses (Cho, Figs. 7 and 8; Im, Fig. 4; Wu, Fig. 14) wherein each of the intermediate layers INS3 (Cho, third insulating layer INS3 is an intermediate layer, para [0118], Fig. 8; Im, Fig. 4; Wu, Fig. 14) is a multi-layer including at least three or more double layers formed by stacking a first inorganic insulating layer and a second inorganic insulating layer (Cho, INS3 is formed of multiple layers and may have a plurality of inorganic and organic insulating films which alternate, specifically, stacking a first inorganic insulating layer then first organic insulating layer, followed by a second inorganic insulating layer then second organic insulating layer sequentially laminated, para [0118], Fig. 8; Im, Fig. 4; Wu, Fig. 14), and
the at least three or more double layers are sequentially stacked (Cho, plurality of double layers of INS3 are sequentially stacked, para [0118], Fig. 8; Im, Fig. 4; Wu, Fig. 14).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize stacked insulating layers to control reflectivity of the surface of the display device by alternating refractive indices of the surface as well as protect elements that are further encapsulated by the layer (Cho, para [0225]).
Im/Wu/Cho discloses (Wu, Figs. 1C to 1E; Cho, Fig. 8; Im, Fig. 4) a refractive index of the first inorganic insulating layer and a refractive index of the second inorganic insulating layer are different from each other (Wu, Fig. 1E, first insulating layer 122 is a light absorbing/reflective insulating material consisting of a plurality of coating films having different refractive indices to render a reflecting effect, para [0032]; Cho, Fig. 8; Im, Fig. 4).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Wu, including the specific refractive indices of the insulating layers, to the teachings of Im/Cho. Depending upon intended use of each individual insulating layer, either as a light absorptive insulating material or as a reflective insulating material and the resultant stacking of each of the respective individual insulating layers allows for the ability to control the behavior of the emitted light (Wu, para [0032]). The motivation to do so is that the combination of alternating refractive indices of stacked insulating layers to allow for the intended use as a light controlling insulating layer stack in a light-emitting display device.
Allowable Subject Matter
Claims 10-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 10, the closest prior art of record, Im (US 2019/0326348 A1), Cho (WO 2019/208880 A1), and Wu (US 2019/0355785 A1) fails to disclose the another one of the intermediate layers is commonly provided to the pixel and adjacent pixels in a same column as the pixel, in view of the rest of the limitations of claim 10.
Regarding claim 11 (from which claims 12-15 depend) the closest prior art of record, Im (US 2019/0326348 A1), Cho (WO 2019/208880 A1), and Wu (US 2019/0355785 A1) fails to disclose wherein the pixel further includes an insulating layer disposed between the first and second electrodes and the bank pattern in view of the rest of the limitations of claim 11.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEVY J BOEGEL whose telephone number is (703)756-1299. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM.
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/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812