DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
RE: the rejection of claim 9 under 35 USC 103, Applicant’s amendments have resulted in claim 9 including allowable subject matter. Accordingly, claim 9 is objected to as depending from a rejected base claim but would be allowable if rewritten in independent form as further discussed below. Accordingly, the rejection of claim 9 under 35 USC 103 is withdrawn.
RE: the rejection of claims 1, 4-6, and 20-22 under 35 USC 102 or 35 USC 103, Applicant’s arguments and/or amendments have been fully considered but are not persuasive for the reasons provided below.
RE: Claim 1, Applicant argues Cheng is from a non-analogous art field of art, and that Cheng is directed to fabricating phase change memory devices - specifically forming annular heaters and annular phase change layers in a memory cell context. The conductive material 115 in Cheng is deposited to form a lower electrode and annular heater (elements 110 and 120) within deep openings of a dielectric layer for a phase change memory device ([0071]). This is fundamentally different from the field of Schoenborn, which is directed to self-aligned gate fabrication in logic transistors. Cheng and Schoenborn are not in the same field of endeavor.
However, the word “logic” is not found in Schoenborn. Instead, Schoenborn discloses The invention relates generally to the field of integrated circuit fabrication and, in particular, to improved methods for fabricating self aligned transistor gates, [0001]. Accordingly, the field of Schoenborn is broadly directed to the field of integrated circuits containing transistor gates. Cheng is directed to phase change memory where in FIG. 9B, an active device 180 is shown containing a gate 184. Cheng discloses 180 is a transistor including a gate 184, [0043]. Accordingly, Cheng is a specific integrated circuit containing a transistor gate, and thus Cheng and Schoenborn are directed to the same field.
Applicant argues that the motivation to combine is improperly derived from hindsight. Applicant argues The Office Action's stated motivation for combining Cheng with Schoenborn is to achieve "good step coverage property to uniformly cover the sidewalls of the opening of 38." However, this rationale presupposes that covering the sidewalls of the opening is an objective in Schoenborn's process - but it is not. In Schoenborn, the refractory metal layer 48 is deposited broadly over the substrate surface (FIG. 7), and it contacts the exposed gate material 46 at the gate area opening 44. The silicidation reaction then occurs where 48 contacts the polysilicon gate material 46 below. There is no requirement in Schoenborn for conformal sidewall coverage of the opening, because the alloy (silicide 50) forms at the bottom of the gate area where 48 contacts the polysilicon - not on sidewalls. Schoenborn's blocking layer 38 acts as a planar mask, not a deep trench. The Office Action importing a concern about sidewall coverage simply does not arise in Schoenborn's process.
However as shown in Schoenborn FIG. 7, the silicidation reaction occurs not only below the opening of 38; the silicidation reaction occurs above the opening of 38, below the opening of 38, and within the opening of 38 along its sidewalls, as shown in Schoenborn FIG. 8 where the silicide 50 extends above, below, and within the opening of 38 and along its sidewalls. Accordingly, depositing the metal layer 48 by atomic layer deposition would ensure a uniform sidewall coverage as taught by Cheng, [0071], preventing gaps in the opening 38 after the metal layer 48 is deposited.
Applicant argues Cheng’s conductive material 115 serves a fundamentally different purpose than Schoenborn’s metal layer 48.
However, the proposed modification does not change the purpose of Schoenborn’s metal layer 48. Further, Cheng discloses the conductive material 115, such as titanium, titanium nitride, tantalum nitride, titanium aluminum nitride, tantalum aluminum nitride, or a combination thereof, is deposited by using physical vapor deposition, chemical vapor deposition, atomic layer deposition, [0071]. Schoenborn discloses 48 is formed of titanium, [0029]. Both Schoenborn and Cheng disclose titanium deposited within an opening with Cheng providing an advantage / motivation to use atomic layer deposition as discussed above. Accordingly, one skilled in the art would understand that various deposition techniques for titanium would have different benefits and in the instant case, they would be motivated to use atomic layer deposition in order to provide a uniform sidewall coverage of titanium preventing gaps in the opening of 38.
Applicant argues Chen does not teach ALD specifically for the purpose of a metal that will undergo silicidation.
However, there is no requirement for the deposition technique to relate to the same purpose of a metal that will undergo silicidation.
Applicant argues the obvious to try rationale is insufficient. Applicant argues The Office Action invokes an "obvious to try" rationale, noting that ALD is one of
several deposition options identified by Cheng. However, the "obvious to try" doctrine requires that there be a finite number of identified, predictable solutions. Schoenborn explicitly identifies sputtering and CVD as deposition methods for its metal layer 48 ([0029]). Selecting ALD from the broader universe of deposition techniques - where sputtering and CVD are already identified as suitable - is not obvious to try simply because ALD exists as a known technique in a different technological context. There must be a specific reason, grounded in the problem being solved, to choose ALD over the methods Schoenborn already identifies, and the Office Action did not provide one.
However, as provided in MPEP 2143, the requirements of an obvious to try rationale include: 1) a finding that there had been a recognized problem or need in the art (In the previous Office Action, the need of selecting a deposition technique for titanium was identified); 2) a finding that there had been a finite number of identified, predictable potential solutions to the recognized need (In the previous Office Action, the finite number of predictable solutions to depositing titanium were identified, including using physical vapor deposition, chemical vapor deposition, atomic layer deposition as taught by Cheng, [0071]); a finding that one of ordinary skill in the art could have pursued the known potential solutions with a reasonable expectation of success (which was provided in the previous Office Action).
RE: Claim 4, Applicant argues Aminpur does not teach etching a substrate using the alloy layer as a hardmask.
However, in the previous Office Action, element / insulating layer 34 of Schoenborn is mapped to the claimed substrate, and in the proposed modification as taught by Aminpur, the insulating layer 34 is etched using the silicide 50 as a hardmask.
RE: the rejection of claim 5, Applicant argues Aminpur's thickness range for the silicide mask is 10-30 nm - it does not overlap with or teach the claimed range of being between 0.5-10 nm.
However, a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close, see MPEP 2144.05. Further, under a broad reasonable interpretation, the range between 0.5-10nm is considered to be inclusive of endpoints. US 20150170965 A1 which was filed by Applicant, has a claim 9 including “wherein the number of cycles ranges between 2 to 5 cycles, inclusive.” As another example, US 20220351940 A1 which was filed by Applicant, discloses For the examples of highest and lowest RF power settings, “between” is inclusive of the end points of each range, [0041]. As another example, US 20080048247 A1 discloses the silicon nitride film containing carbon has a thickness in a range between 5 nm and 100 nm, both inclusive, [0032]. Accordingly, as the instant specification does not disclose that the range is exclusive, under a broad reasonable interpretation, the range between 0.5-10nm is considered to be inclusive of endpoints, and therefore the ranges overlap.
Allowable Subject Matter
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Further search identified US5334545A, US6562724, US20130273727A1, US6465362, and the prior art of record including these cited references fails to disclose or suggest the limitation “wherein the first material comprises silicon oxide and the second material comprises at least one of tin, tungsten, and platinum, wherein the second material and the silicon oxide contact each at the at least one opening, and wherein the alloy is formed from the silicon oxide and the second material” in claim 9 in combination with the limitations of the base claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 20-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20020177280A1 (“Schoenborn”), further in view of US 20200303638 A1 (“Cheng”).
RE: Claim 1, Schoenborn discloses A method for forming etched features in a layer of a first material (In FIG. 6: 36 or alternatively, the combination of 36 and 34, [0022]-[0025]), comprising:
a) forming patterned mask (38 in FIG. 6) over the layer of the first material, wherein the patterned mask comprises at least one mask layer (38) and at least one opening (FIG. 6 shows an opening in 38, [0026]-[0028]);
b) depositing a layer of a second material (48 in FIG. 7, [0029]) over the patterned mask and the layer of the first material, wherein the second material only contacts the layer of the first material at the at least one opening (FIG. 7 shows 48 only contacts 36 at the opening of 38);
c) forming an alloy layer (50, [0029]-[0030]) of the first material and the second material between the layer of the first material and the layer of the second material (FIG. 8 shows 50 is formed between 36 and 48, and between 48 and the combination of 36, 34; After depositing the refractory metal layer 48 on the substrate 30, the layer 48 is annealed to react the metal layer 48 with the exposed gate material 46 in the gate layer 36 to form a metal silicide 50 in the gate area 44, as depicted in FIG. 8, [0029]), wherein the alloy layer is formed in the at least one opening where the second material contacts the layer of the first material and not below the at least one mask layer (FIG.8 shows 50 is formed in the opening of 38 where 48 contacts 36 and not completely below 38);
d) removing the layer of the second material that is not alloyed to expose the patterned mask (FIG. 9 shows the portion of 48 that is not alloyed is removed to expose 38; After forming the metal silicide 50 in the gate area 44, the unreacted refractory metal in refractory metal layer 48 is stripped from the surface of the blocking layer 38, such as by an acid strip process, [0030]);
e) after d, removing the patterned mask to expose at least part of the layer of the first material (FIG. 10 shows 38 is removed to expose at least part of 36, [0031]); and
f) selectively etching the layer of the first material with respect to the alloy layer, using the alloy layer as a hardmask (FIG. 11 shows 36 is selectively etched with respect to the alloy layer 50, using the alloy layer 50 as a hardmask; During the etching process, the metal silicide 50 is preferably substantially unaffected by the etching chemicals and thus provides a hard mask for the gate layer 36, [0032]).
Note the word “material” is broad terminology and is not defined in the instant specification. The word “material” has been defined as “the elements, constituents, or substances of which something is composed or can be made,” see definition 1a(1) provided by Merriam-Webster’s dictionary.
Accordingly, under a broad reasonable interpretation, either 1) the gate layer 36 or 2) the combination of the gate layer 36 and the insulating layer 34 can be considered “a first material” as claimed. A material does not necessarily consist of a single constituent.
This is consistent with [0022] of Schoenborn which discloses a substrate 30 includes the gate layer 36 and the insulating layer 34. Accordingly, the combination of the gate layer 36 and the insulating layer 34 is a composite material of the substrate 30.
Accordingly, either the gate layer 36 or the insulating layer 34, or both, may be performed upon to meet the claimed limitations involving the first material.
Further, the word “layer” is also broad, and defined as “a thickness of some material laid on or spread over a surface,” see definition 1 by Collins Dictionary. Accordingly, under a broad reasonable interpretation, the combination of the gate layer 36 and the insulating layer 34 is a layer of a composite material.
Schoenborn does not explicitly disclose: wherein the depositing the layer of the second material is by atomic layer deposition.
However, Schoenborn discloses The metal layer 48 is formed of titanium, [0029].
FIG. 7 shows the metal layer 48 is formed in the opening of 38.
In the same field of endeavor, Cheng discloses the conductive material 115, such as titanium, titanium nitride, tantalum nitride, titanium aluminum nitride, tantalum aluminum nitride, or a combination thereof, is deposited by using physical vapor deposition, chemical vapor deposition, atomic layer deposition, or the like, so that the formed conductive material 115 has good step coverage property to uniformly cover the sidewalls of the opening 210a, [0071]. Accordingly, before the effective filing date of the claimed invention, there was a need to determine the deposition method for depositing the titanium of the metal layer 48.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to deposit the metal layer 48 of titanium by atomic layer deposition as taught by Cheng so that the metal layer 48 has good step coverage property in order to uniformly cover the sidewalls of the opening of 38, which would prevent gaps in the opening of 38 after 48 is deposited.
Further, it would have been obvious to try depositing the titanium layer 48 by atomic layer deposition since atomic layer deposition is one solution for depositing titanium identified by Cheng and this would have had a reasonable expectation of success, see MPEP 2143.
RE: Claim 20, Schoenborn in view of Cheng discloses The method, as recited in claim 1, wherein the forming an alloy layer of the first material and the second material between the layer of the first material and the layer of the second material comprises heating the layer of the first material and the layer of the second material to form the alloy (Schoenborn discloses After depositing the refractory metal layer 48 on the substrate 30, the layer 48 is annealed to react the metal layer 48 with the exposed gate material 46 in the gate layer 36 to form a metal silicide 50 in the gate area 44, as depicted in FIG. 8, [0029]; Accordingly, as 48 is in direct contact with 36, annealing 48 would heat 48 and 36 to form the alloy 50).
RE: Claim 21, Schoenborn in view of Cheng discloses The method, as recited in claim 1, wherein the second material only physically contacts the first material at the at least one opening and wherein the alloy layer is formed in the at least one opening where the second material physically contacts the first material and not below the at least one mask layer (Schoenborn FIG. 7 shows the second material 48 only physically contacts the first material 36 at the opening of 38 and FIG. 8 shows the alloy layer 50 is formed in the opening of 38 where the second material 48 physically contacts the first material 36 and not completely below the mask layer 38).
RE: Claim 22, Schoenborn in view of Cheng discloses The method, as recited in claim 1, wherein forming an alloy layer of the first material and the second material between the layer of the first material and the layer of the second material forms the alloy from the first material of the layer of the first material and the second material of the layer of the second material (Schoenborn discloses After depositing the refractory metal layer 48 on the substrate 30, the layer 48 is annealed to react the metal layer 48 with the exposed gate material 46 in the gate layer 36 to form a metal silicide 50 in the gate area 44, as depicted in FIG. 8, [0029]; The metal layer 48 is preferably formed of a metal selected from the group consisting of titanium, tungsten, nickel, cobalt, [0029]; Metal silicides which may be formed according to the invention when the gate layer 36 is polysilicon include, but are not limited to tungsten silicide, titanium silicide, nickel silicide and cobalt silicide, [0029]; Accordingly, as 48 is reacted with 36 to form the alloy layer 50, the alloy layer 50 is formed from 48 and 36).
Claim(s) 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schoenborn in view of Cheng as applied to claim 1, further in view of US 20050118801 A1 (“Aminpur”).
RE: Claim 4, Schoenborn in view of Cheng discloses The method, as recited in claim 1, wherein the layer of the first material (From Schoenborn: 36) is over a substrate (From Schoenborn: 34).
Schoenborn in view of Cheng does not explicitly disclose the method further comprising etching the substrate using the alloy layer as a hardmask.
However, Schoenborn discloses substrate 30 includes support material 32 and insulating layer 34, [0022].
Schoenborn discloses 34 is an insulating gate oxide layer, [0022].
Schoenborn discloses 36 is a polysilicon gate layer, [0022].
FIG. 12 shows the left and right portions of the insulating layer 34 were removed after FIG. 11.
In the same field of endeavor, Aminpur discloses in FIGs. 2a-2g:
A layer stack 202 is formed above the substrate 201, wherein the layer stack 202 may comprise, in one particular embodiment, a gate insulation layer 203 and a layer 204 of a gate electrode material such as polysilicon, [0025].
Aminpur further discloses the substrate 201 is subjected to an anisotropic etch process, on the basis of a chlorine/bromine-containing plasma etch atmosphere so as to pattern the layer stack 202, [0038].
FIG. 2g schematically shows the device 200 after completion of the anisotropic etch process, thereby forming a circuit feature 214 including the metal silicide etch mask 212 and the residuals of the layer 204 and 203, [0039].
FIG. 2g shows the gate insulation layer 203 was etched using the silicide mask 212 as a mask.
Aminpur further discloses Since the lateral dimension 209b of the metal silicide etch mask 212 substantially determines the lateral dimension of the circuit element to be formed from the layer stack 202, it may be advantageous to measure the cross-sectional profile of the metal silicide etch mask 212 by appropriate measurement methods, such as scanning electron microscopy, [0036].
Aminpur further discloses the present invention enables the formation of circuit features having critical dimensions well beyond the resolution of presently available lithography techniques. Since complex and difficult resist trim processes are replaced by forming a stable hard mask for the patterning of the circuit feature, a significant improvement in production yield and cost reduction may be achieved, [0046].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to etch the gate insulation layer 34 using the silicide 50 as a mask as taught by Aminpur in order to achieve a significant improvement in production yield and cost reduction.
RE: Claim 5, Schoenborn in view of Cheng does not explicitly disclose The method, as recited in claim 1, wherein the alloy layer has a thickness between 0.5 nm and 10 nm.
However, in the same field of endeavor, Aminpur discloses the thickness 213 of the metal silicide etch mask 212 may be selected so as to provide the required masking effect during a subsequent anisotropic etch process in patterning the layer stack 202. Hence, the thickness 213 may significantly depend on the etch selectivity provided by the metal silicide etch mask 212 compared to the material of the layer stack 202. Thus, in some cases, a relatively moderate thickness 213 in the range of approximately 10-30 nm may be sufficient for the patterning process. Hence, the modification of the lateral dimension 209b compared to the dimension 209a may be considered negligible, [0036].
Accordingly, before the effective filing date of the claimed invention, there was a need to select or determine the thickness of the silicide layer 50 in Schoenborn.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the thickness of the silicide layer 50 which is used as a mask to be 10nm as taught by Aminpur as this would have been obvious to try since 10nm is one solution for the thickness of a silicide mask layer identified by Aminpur, and this would have had a reasonable expectation of success, see MPEP 2143. Note In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. Similarly, a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close, see MPEP 2144.05.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schoenborn in view of Cheng as applied to claim 1 above, further in view of Aminpur, further in view of US5677217A (“Tseng”), and further in view of US 20120258556 A1 (“Matsumoto”).
RE: Claim 6, Schoenborn in view of Cheng does not explicitly disclose The method, as recited in claim 1, wherein the layer of the second material has a thickness between 0.5 nm and 20 nm.
However, in the same field of endeavor, Aminpur discloses the thickness 213 of the metal silicide etch mask 212 may be selected so as to provide the required masking effect during a subsequent anisotropic etch process in patterning the layer stack 202. Hence, the thickness 213 may significantly depend on the etch selectivity provided by the metal silicide etch mask 212 compared to the material of the layer stack 202. Thus, in some cases, a relatively moderate thickness 213 in the range of approximately 10-30 nm may be sufficient for the patterning process. Hence, the modification of the lateral dimension 209b compared to the dimension 209a may be considered negligible, [0036].
Aminpur further discloses the amount of silicon consumed may be determined by the initially deposited layer thickness and the anneal parameters by which the ratio of cobalt disilicide to cobalt monosilicide may be adjusted, [0034].
Accordingly, before the effective filing date of the claimed invention, there was a need to select or determine the thickness of the silicide layer 50 in Schoenborn.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the thickness of the silicide layer 50 which is used as a mask to be 10nm as taught by Aminpur as this would have been obvious to try since 10nm is one solution for the thickness of a silicide mask layer identified by Aminpur, and this would have had a reasonable expectation of success, see MPEP 2143.
In the same field of endeavor, Tseng discloses:
a layer of titanium, 8, is deposited on the exposed top surface of polysilicon layer, 3a, and on the top surface of insulator layer, 4, via r.f. sputtering procedures, to a thickness between about 300 to 1000 Angstroms. FIG. 3, schematically shows the result of this deposition. A rapid thermal anneal, (RTA), procedure is next performed at a temperature between about 750° to 950° C., for a time between about 20 to 60 sec. This procedure is used to convert a top portion of polysilicon layer, 3a, to a titanium silicide structure, 9, Col. 4, lines 10-25.
300 Angstroms is equal to 30 nm.
Tseng further discloses A RIE procedure, using HBr and SF6 as an etchant, and titanium silicide structure, 9, as a mask, is used to remove polysilicon layer, 3a, from areas not covered by titanium silicide structure, Col. 4, lines 40-50.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use routine optimization and/or routine experimentation to discover smaller thicknesses than 30nm for the metal layer 48 to arrive at the thickness of 19nm or 20nm for the metal layer 48; because a silicide mask layer 50 thickness of 10nm is used, a thickness of 19nm or 20nm of the metal layer 48 used to form the silicide mask layer 50 would be more than sufficient to react with polysilicon and form a resulting thickness of 10nm for the silicide mask layer 50, and using smaller thicknesses would save in material costs, see MPEP 2144. Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955. Also see In re Geisler, 116 F.3d 1465, 1470, 43 USPQ2d 1362, 1366 (Fed. Cir. 1997)(Claims were unpatentable because appellants failed to submit evidence of criticality to demonstrate that that the wear resistance of the protective layer in the claimed thickness range of 50-100 Angstroms was "unexpectedly good,”) see MPEP 2144.
Alternatively or additionally, in the same field of endeavor, Matsumoto discloses the metal film 17 whose surface is subjected to silicidation is formed on the flow path forming substrate wafer 110. Specifically, nickel (nickel) is formed into a film with a thickness of about 10 to 100 nm as the metal film 17 by a sputtering method, [0057].
Accordingly, before the effective filing date of the claimed invention, there was a need to select or determine the thickness of the metal layer 48 in Schoenborn.
Matsumoto further discloses nickel is diffused for silicidation, a nickel silicide film (silicide film 16), [0059], and silicide 16 is used as a mask, [0060].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the thickness of the metal layer 48 to be 10nm as this would have been obvious to try since 10nm is one solution for the thickness of a metal layer used during silicidation to form a silicide mask identified by Matsumoto, and this would have had a reasonable expectation of success given that the resulting thickness of the silicide mask 50 is to be 10nm, see MPEP 2143.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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