DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 7, 2026 has been entered.
Information Disclosure Statement(s)
The Information Disclosure Statement(s) filed on April 30, 2026 was considered by the Examiner.
Response to Arguments
RE: the rejection of claims under 35 USC 102 and 35 USC 103, Applicant’s arguments and/or amendments have been fully considered but are largely moot in view of the new grounds of rejection presented herein.
However, the Examiner will comment on Applicant’s remarks as Examiner’s present interpretations are similar to the interpretations provided in the Office Action dated February 10, 2026, and these comments are believed to advance prosecution as they will provide Applicant with a better understanding of the Examiner’s interpretations.
Applicant argues So, the Office Action refers to 110 as the layer of the first material for step a and then refers to 130 as the layer of the first material for step b. The Office Action failed to point out anything in Lee that teaches that layer 110 is the same layer as 130.
However, in the Office Action dated February 10, 2026, the combination of 130a and the upper surface of 110 was considered as corresponding to the claimed first material (see the second line of the rejection of claim 1).
Similarly, in the present Office Action, layer 36 or alternatively the combination of the layers 36 and 34 in the reference Schoenborn is considered as corresponding to the claimed first material. This is because the word “material” is broad terminology not defined in the instant specification. The word “material” has been defined as “the elements, constituents, or substances of which something is composed or can be made,” see definition 1a(1) provided by Merriam-Webster’s dictionary.
Accordingly, under a broad reasonable interpretation, either 1) the gate layer 36 or 2) the combination of the gate layer 36 and the insulating layer 34 can be considered “a first material” as claimed. A material does not necessarily consist of a single constituent and may be a composite material. Accordingly, either the gate layer 36 or the insulating layer 34, or both may be performed upon to meet the claimed limitations involving the first material.
RE: Claim 9, Applicant argues Since claim 9 states that the first material comprises silicon oxide and the second material comprises at least one of tin, tungsten, and platinum, rephrasing claim 1 with the limitations of claim 9 would recite a method for forming etched features in a layer of silicon oxide, comprising:
c) forming an alloy layer of the silicon oxide and the at least one of tin, tungsten,
and platinum between the layer of the silicon oxide and the layer of the at least one of tin, tungsten, and platinum.
Applicant appears to interpret the word “comprises” to mean “is.” The word “comprises” is open-ended not closed-ended, as one definition for comprise is “to include or contain,” see definition 1 by Dictionary.com. Accordingly, under a broad reasonable interpretation since claim 9 requires the first material to comprise silicon oxide, it does not necessarily require the silicon oxide to be performed upon in the method of claim 1. Rather it simply requires some unspecified part (layer 34 in Schoenborn) of the first material to include silicon oxide, while another part (layer 36) of the first material may be performed upon to meet the limitations of claim 1, as the first material is a composite material in the interpretation of claim 9, corresponding to the combination of the layers 34 and 36.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 20-22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US20020177280A1 (“Schoenborn”).
RE: Claim 1, Schoenborn discloses A method for forming etched features in a layer of a first material (In FIG. 6: 36 or alternatively, the combination of 36 and 34, [0022]-[0025]), comprising:
a) forming patterned mask (38 in FIG. 6) over the layer of the first material, wherein the patterned mask comprises at least one mask layer (38) and at least one opening (FIG. 6 shows an opening in 38, [0026]-[0028]);
b) depositing a layer of a second material (48 in FIG. 7, [0029]) over the patterned mask and the layer of the first material, wherein the second material only contacts the layer of the first material at the at least one opening (FIG. 7 shows 48 only contacts 36 at the opening of 38);
c) forming an alloy layer (50, [0029]-[0030]) of the first material and the second material between the layer of the first material and the layer of the second material (FIG. 8 shows 50 is formed between 36 and 48, and between 48 and the combination of 36, 34; After depositing the refractory metal layer 48 on the substrate 30, the layer 48 is annealed to react the metal layer 48 with the exposed gate material 46 in the gate layer 36 to form a metal silicide 50 in the gate area 44, as depicted in FIG. 8, [0029]), wherein the alloy layer is formed in the at least one opening where the second material contacts the layer of the first material and not below the at least one mask layer (FIG.8 shows 50 is formed in the opening of 38 where 48 contacts 36 and not completely below 38);
d) removing the layer of the second material that is not alloyed to expose the patterned mask (FIG. 9 shows the portion of 48 that is not alloyed is removed to expose 38; After forming the metal silicide 50 in the gate area 44, the unreacted refractory metal in refractory metal layer 48 is stripped from the surface of the blocking layer 38, such as by an acid strip process, [0030]);
e) after d, removing the patterned mask to expose at least part of the layer of the first material (FIG. 10 shows 38 is removed to expose at least part of 36, [0031]); and
f) selectively etching the layer of the first material with respect to the alloy layer, using the alloy layer as a hardmask (FIG. 11 shows 36 is selectively etched with respect to the alloy layer 50, using the alloy layer 50 as a hardmask; During the etching process, the metal silicide 50 is preferably substantially unaffected by the etching chemicals and thus provides a hard mask for the gate layer 36, [0032]).
Note the word “material” is broad terminology and is not defined in the instant specification. The word “material” has been defined as “the elements, constituents, or substances of which something is composed or can be made,” see definition 1a(1) provided by Merriam-Webster’s dictionary.
Accordingly, under a broad reasonable interpretation, either 1) the gate layer 36 or 2) the combination of the gate layer 36 and the insulating layer 34 can be considered “a first material” as claimed. A material does not necessarily consist of a single constituent.
This is consistent with [0022] of Schoenborn which discloses a substrate 30 includes the gate layer 36 and the insulating layer 34. Accordingly, the combination of the gate layer 36 and the insulating layer 34 is a composite material of the substrate 30.
Accordingly, either the gate layer 36 or the insulating layer 34, or both, may be performed upon to meet the claimed limitations involving the first material.
Further, the word “layer” is also broad, and defined as “a thickness of some material laid on or spread over a surface,” see definition 1 by Collins Dictionary. Accordingly, under a broad reasonable interpretation, the combination of the gate layer 36 and the insulating layer 34 is a layer of a composite material.
RE: Claim 20, Schoenborn discloses The method, as recited in claim 1, wherein the forming an alloy layer of the first material and the second material between the layer of the first material and the layer of the second material comprises heating the layer of the first material and the layer of the second material to form the alloy (After depositing the refractory metal layer 48 on the substrate 30, the layer 48 is annealed to react the metal layer 48 with the exposed gate material 46 in the gate layer 36 to form a metal silicide 50 in the gate area 44, as depicted in FIG. 8, [0029]; Accordingly, as 48 is in direct contact with 36, annealing 48 would heat 48 and 36 to form the alloy 50).
RE: Claim 21, Schoenborn discloses The method, as recited in claim 1, wherein the second material only physically contacts the first material at the at least one opening and wherein the alloy layer is formed in the at least one opening where the second material physically contacts the first material and not below the at least one mask layer (FIG. 7 shows the second material 48 only physically contacts the first material 36 at the opening of 38 and FIG. 8 shows the alloy layer 50 is formed in the opening of 38 where the second material 48 physically contacts the first material 36 and not completely below the mask layer 38).
RE: Claim 22, Schoenborn discloses The method, as recited in claim 1, wherein forming an alloy layer of the first material and the second material between the layer of the first material and the layer of the second material forms the alloy from the first material of the layer of the first material and the second material of the layer of the second material (After depositing the refractory metal layer 48 on the substrate 30, the layer 48 is annealed to react the metal layer 48 with the exposed gate material 46 in the gate layer 36 to form a metal silicide 50 in the gate area 44, as depicted in FIG. 8, [0029]; The metal layer 48 is preferably formed of a metal selected from the group consisting of titanium, tungsten, nickel, cobalt, [0029]; Metal silicides which may be formed according to the invention when the gate layer 36 is polysilicon include, but are not limited to tungsten silicide, titanium silicide, nickel silicide and cobalt silicide, [0029]; Accordingly, as 48 is reacted with 36 to form the alloy layer 50, the alloy layer 50 is formed from 48 and 36).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schoenborn as applied to claim 1, further in view of US 20200303638 A1 (“Cheng”).
RE: Claim 2, Schoenborn does not explicitly disclose The method, as recited in claim 1, wherein the depositing the layer of the second material is by atomic layer deposition.
However, Schoenborn discloses The metal layer 48 is formed of titanium, [0029].
FIG. 7 shows the metal layer 48 is formed in the opening of 38.
In the same field of endeavor, Cheng discloses the conductive material 115, such as titanium, titanium nitride, tantalum nitride, titanium aluminum nitride, tantalum aluminum nitride, or a combination thereof, is deposited by using physical vapor deposition, chemical vapor deposition, atomic layer deposition, or the like, so that the formed conductive material 115 has good step coverage property to uniformly cover the sidewalls of the opening 210a, [0071]. Accordingly, before the effective filing date of the claimed invention, there was a need to determine the deposition method for depositing the titanium of the metal layer 48.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to deposit the metal layer 48 of titanium by atomic layer deposition as taught by Cheng so that the metal layer 48 has good step coverage property in order to uniformly cover the sidewalls of the opening of 38, which would prevent gaps in the opening of 38 after 48 is deposited.
Further, it would have been obvious to try depositing the titanium layer 48 by atomic layer deposition since atomic layer deposition is one solution for depositing titanium identified by Cheng and this would have had a reasonable expectation of success, see MPEP 2143.
Claim(s) 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schoenborn as applied to claim 1, further in view of US 20050118801 A1 (“Aminpur”).
RE: Claim 4, Schoenborn discloses The method, as recited in claim 1, wherein the layer of the first material (36) is over a substrate (34).
Schoenborn does not explicitly disclose the method further comprising etching the substrate using the alloy layer as a hardmask.
However, Schoenborn discloses substrate 30 includes support material 32 and insulating layer 34, [0022].
Schoenborn discloses 34 is an insulating gate oxide layer, [0022].
Schoenborn discloses 36 is a polysilicon gate layer, [0022].
FIG. 12 shows the left and right portions of the insulating layer 34 were removed after FIG. 11.
In the same field of endeavor, Aminpur discloses in FIGs. 2a-2g:
A layer stack 202 is formed above the substrate 201, wherein the layer stack 202 may comprise, in one particular embodiment, a gate insulation layer 203 and a layer 204 of a gate electrode material such as polysilicon, [0025].
Aminpur further discloses the substrate 201 is subjected to an anisotropic etch process, on the basis of a chlorine/bromine-containing plasma etch atmosphere so as to pattern the layer stack 202, [0038].
FIG. 2g schematically shows the device 200 after completion of the anisotropic etch process, thereby forming a circuit feature 214 including the metal silicide etch mask 212 and the residuals of the layer 204 and 203, [0039].
FIG. 2g shows the gate insulation layer 203 was etched using the silicide mask 212 as a mask.
Aminpur further discloses Since the lateral dimension 209b of the metal silicide etch mask 212 substantially determines the lateral dimension of the circuit element to be formed from the layer stack 202, it may be advantageous to measure the cross-sectional profile of the metal silicide etch mask 212 by appropriate measurement methods, such as scanning electron microscopy, [0036].
Aminpur further discloses the present invention enables the formation of circuit features having critical dimensions well beyond the resolution of presently available lithography techniques. Since complex and difficult resist trim processes are replaced by forming a stable hard mask for the patterning of the circuit feature, a significant improvement in production yield and cost reduction may be achieved, [0046].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to etch the gate insulation layer 34 using the silicide 50 as a mask as taught by Aminpur in order to achieve a significant improvement in production yield and cost reduction.
RE: Claim 5, Schoenborn does not explicitly disclose The method, as recited in claim 1, wherein the alloy layer has a thickness between 0.5 nm and 10 nm.
However, in the same field of endeavor, Aminpur discloses the thickness 213 of the metal silicide etch mask 212 may be selected so as to provide the required masking effect during a subsequent anisotropic etch process in patterning the layer stack 202. Hence, the thickness 213 may significantly depend on the etch selectivity provided by the metal silicide etch mask 212 compared to the material of the layer stack 202. Thus, in some cases, a relatively moderate thickness 213 in the range of approximately 10-30 nm may be sufficient for the patterning process. Hence, the modification of the lateral dimension 209b compared to the dimension 209a may be considered negligible, [0036].
Accordingly, before the effective filing date of the claimed invention, there was a need to select or determine the thickness of the silicide layer 50 in Schoenborn.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the thickness of the silicide layer 50 which is used as a mask to be 10nm as taught by Aminpur as this would have been obvious to try since 10nm is one solution for the thickness of a silicide mask layer identified by Aminpur, and this would have had a reasonable expectation of success, see MPEP 2143. Note In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. Similarly, a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close, see MPEP 2144.05.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schoenborn as applied to claim 1 above, further in view of Aminpur, further in view of US5677217A (“Tseng”), and further in view of US 20120258556 A1 (“Matsumoto”).
RE: Claim 6, Schoenborn does not explicitly disclose The method, as recited in claim 1, wherein the layer of the second material has a thickness between 0.5 nm and 20 nm.
However, in the same field of endeavor, Aminpur discloses the thickness 213 of the metal silicide etch mask 212 may be selected so as to provide the required masking effect during a subsequent anisotropic etch process in patterning the layer stack 202. Hence, the thickness 213 may significantly depend on the etch selectivity provided by the metal silicide etch mask 212 compared to the material of the layer stack 202. Thus, in some cases, a relatively moderate thickness 213 in the range of approximately 10-30 nm may be sufficient for the patterning process. Hence, the modification of the lateral dimension 209b compared to the dimension 209a may be considered negligible, [0036].
Aminpur further discloses the amount of silicon consumed may be determined by the initially deposited layer thickness and the anneal parameters by which the ratio of cobalt disilicide to cobalt monosilicide may be adjusted, [0034].
Accordingly, before the effective filing date of the claimed invention, there was a need to select or determine the thickness of the silicide layer 50 in Schoenborn.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the thickness of the silicide layer 50 which is used as a mask to be 10nm as taught by Aminpur as this would have been obvious to try since 10nm is one solution for the thickness of a silicide mask layer identified by Aminpur, and this would have had a reasonable expectation of success, see MPEP 2143.
In the same field of endeavor, Tseng discloses:
a layer of titanium, 8, is deposited on the exposed top surface of polysilicon layer, 3a, and on the top surface of insulator layer, 4, via r.f. sputtering procedures, to a thickness between about 300 to 1000 Angstroms. FIG. 3, schematically shows the result of this deposition. A rapid thermal anneal, (RTA), procedure is next performed at a temperature between about 750° to 950° C., for a time between about 20 to 60 sec. This procedure is used to convert a top portion of polysilicon layer, 3a, to a titanium silicide structure, 9, Col. 4, lines 10-25.
300 Angstroms is equal to 30 nm.
Tseng further discloses A RIE procedure, using HBr and SF6 as an etchant, and titanium silicide structure, 9, as a mask, is used to remove polysilicon layer, 3a, from areas not covered by titanium silicide structure, Col. 4, lines 40-50.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use routine optimization and/or routine experimentation to discover smaller thicknesses than 30nm for the metal layer 48 to arrive at the thickness of 19nm or 20nm for the metal layer 48; because a silicide mask layer 50 thickness of 10nm is used, a thickness of 19nm or 20nm of the metal layer 48 used to form the silicide mask layer 50 would be more than sufficient to react with polysilicon and form a resulting thickness of 10nm for the silicide mask layer 50, and using smaller thicknesses would save in material costs, see MPEP 2144. Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955. Also see In re Geisler, 116 F.3d 1465, 1470, 43 USPQ2d 1362, 1366 (Fed. Cir. 1997)(Claims were unpatentable because appellants failed to submit evidence of criticality to demonstrate that that the wear resistance of the protective layer in the claimed thickness range of 50-100 Angstroms was "unexpectedly good,”) see MPEP 2144.
Alternatively or additionally, in the same field of endeavor, Matsumoto discloses the metal film 17 whose surface is subjected to silicidation is formed on the flow path forming substrate wafer 110. Specifically, nickel (nickel) is formed into a film with a thickness of about 10 to 100 nm as the metal film 17 by a sputtering method, [0057].
Accordingly, before the effective filing date of the claimed invention, there was a need to select or determine the thickness of the metal layer 48 in Schoenborn.
Matsumoto further discloses nickel is diffused for silicidation, a nickel silicide film (silicide film 16), [0059], and silicide 16 is used as a mask, [0060].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the thickness of the metal layer 48 to be 10nm as this would have been obvious to try since 10nm is one solution for the thickness of a metal layer used during silicidation to form a silicide mask identified by Matsumoto, and this would have had a reasonable expectation of success given that the resulting thickness of the silicide mask 50 is to be 10nm, see MPEP 2143.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schoenborn as applied to claim 1, further in view of Aminpur.
RE: Claim 9, Schoenborn discloses The method, as recited in claim 1, wherein the second material comprises at least one of tin, tungsten, and platinum (The metal layer is tungsten, [0029]).
Schoenborn does not explicitly disclose:
wherein the first material comprises silicon oxide.
However, Schoenborn discloses The insulating layer 34 is preferably a gate oxide layer, [0022].
In the same field of endeavor, Aminpur discloses:
layer stack 202 is configured to enable the formation of a specified circuit element, wherein, in advanced silicon-based CMOS technologies, the gate insulation layer 203 may be comprised of nitrogen-enriched silicon dioxide, silicon nitride, or may include a high-k dielectric material with a thickness in accordance with device requirements. For instance, a silicon dioxide based gate insulation layer of highly advanced field effect transistors may have a thickness in the range of approximately 1.5-3 nm, [0025].
Silicon dioxide is an oxide layer.
Before the effective filing date of the claimed invention, there was a need to select a material for the insulating layer 34 in Schoenborn.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use nitrogen-enriched silicon dioxide as the material of the insulating layer 34 as this would have been obvious to try since nitrogen-enriched silicon dioxide is one solution for the material in a gate insulating layer identified by Aminpur and this would have had a reasonable expectation of success, see MPEP 2143. As a result, the combination of the 36 and 34 would comprise silicon oxide.
Conclusion
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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