DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claims
Claims 1-8 10-15 and 17-22 are pending in this application. Claims 9 and 16 were cancelled as set forth in the applicant’s response filed on 6/19/2025.
Prior rejection of Claims 1-17 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, is withdrawn in view of applicant’s amendments to claims 1, 10 and 15 and cancelled claims 9 and 16.
Information Disclosure Statement
Acknowledgement is made of Applicant's Information Disclosure Statement (IDS) from PTO-1449, filed on 6/19/2025. The IDS has been considered.
Drawings
Prior objection to drawing is withdrawn in view of cancelled claims 9 and 16.
Specification
The title of the invention is not accurate. The title mentions “non-plasma enhanced deposition” but during the ALD growth cycles plasma power is used. Particularly, in para [0051] of the specification of the present application, the ALD deposition requires the RF power to be on for 0.5 s, which creates plasma. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Atomic layer deposition for recess etch matching.”
In the reply filed 6/19/2025, applicant mentions that “the title has been replaced as suggested by the examiner”. However, the replacement specification filed 6/19/2025 still has the old title and does not contain a new title.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 22 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 22 recites “The method of claim 15, wherein of claim 1, wherein”. It is not clear if the claim depends from the independent claim 15 or independent claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2017/0287929 A1, of record), and further in view of Tang et al. (US 2015/0243545 A1, of record) and Funayama et al. (US 10224240 B1, of record).
Re Claim 1, Kim teaches a method of fabricating a semiconductor device, the method comprising:
etching high-aspect-ratio channels (103, Fig. 2B, para [0053]) in a multi-layer stack (110/120, up to 120h, Figs. 2A-B, para [0052]) disposed on a semiconductor substrate (101, Figs. 2A-B, para [0052]), the multi-layer stack (110/120, up to 120h) comprising sets of oxide and non- oxide layers (stack is composed of silicon oxide layers 110 and silicon nitride layer 120, Figs. 2A-B, para [0052]);
depositing an oxide (191 can be silicon oxide, Fig. 2L, para [0068]) in each of the high-aspect-ratio channels (103);
recess etching the oxide (191) to form recess-etched channels (recessed 191, Fig. 2P, para [0074]) that have a depth variation of less than about 5% from an average etch depth across the channels (Fig. 2P shows that the depth of the recess of the recessed-channels 191 is constant) and a substantially constant cross-sectional area across each channel (Fig. 2P shows that the cross-sectional area across each channel 191 is substantially constant); and
capping the recess-etched channels (recessed 191) to refill an etched portion of the recess-etched channels with a conductive material (104d, silicon is used to fill the recess, para [0074]).
Kim does not explicitly disclose that the high-aspect-ratio channels (191) is filled using an atomic layer deposition (ALD) process. One of ordinary skill will look into related art to find an effective process to fill the channels.
In a related semiconductor art, Tang teaches a deposition of silicon oxide film to fill a channel gap using ALD process (paras [0030] - [0034]), since ALD provides precise and controlled deposition of thin films with atomic scale thickness and uniformity.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to deposit the silicon oxide into the channels of the semiconductor stack of Kim using the process of ALD as disclosed by Tang, since ALD provides precise and controlled deposition of thin films with atomic scale thickness and uniformity. Moreover, the selection of a known process based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Kim also does not explicitly state that the recess etching the oxide (191) was done using a wet chemical etch. One of ordinary skill will look into related art to find an effective process to etch the oxide layer to form the recess.
In a related semiconductor art, Funayama teaches that silicon oxide layer can be wet-etched using dilute hydrofluoric acid (Col. 12, lines [20 - 36]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to etch the silicon oxide layer of Kim using a known wet-etching process as disclosed by Funayama, which will yield predictable result. The use of a known process for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Additionally, the selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Kim also does not explicitly disclose that the depth variation of the recess and the uniformity of cross-sectional area across each channel are based on a composition of the oxide formed by the ALD process, the composition controlled at least in part on a temperature of a pedestal on which the semiconductor substrate is disposed and a pressure in a chamber containing the substrate is maintained.
However, in the related semiconductor art, Tang discloses a high quality ALD deposition technique of oxide films without any voids, as the voids cause problems during subsequent processing (paras [0004] – [0008] and [0030] - [0034]). The substrate is supported on a pedestal within a processing chamber (para [0017]), which also provides heating to control the temperature (para [0037]). The processing chamber also has a vacuum pump to maintain the pressure within the system (para [0037]). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, that the recess-depth and the cross-sectional area across each channel of Kim will be substantially constant (as shown in Fig. 2P of Kim), based on the high quality ALD deposition process of Tang which deposits a high quality of oxide films without any voids, as the voids cause problems during subsequent processing, like etching (paras [0004] – [0008] and [0030] - [0034]).
Re Claim 5, Kim modified by Tang and Funayama teaches the method of claim 1, wherein recess etching the oxide (191) includes etching the oxide using a dilute HF (DHF) etch of about 100:1 HF: H2O (100:1 diluted hydrofluoric acid, Col. 12, lines [20 - 36], Funayama), the oxide having a relatively constant etch rate along a width and depth of each of the high-aspect-ratio channels.
Funayama doesn’t disclose that the oxide having a relatively constant etch rate along a width and depth of each of the high-aspect-ratio channels. However, the claimed etch-rate characteristic is a result of the etching process performed by the same material as disclosed by Funayama. Where applicant claims a composition in terms of a function, property or characteristic and the composition of the prior art is the same as that of the claim but the function is not explicitly disclosed by the reference, the examiner may make a rejection under both 35 U.S.C. 102 and 103. “There is nothing inconsistent in concurrent rejections for obviousness under 35 U.S.C. 103 and for anticipation under 35 U.S.C. 102.” In re Best, 562 F.2d 1252, 1255 n.4, 195 USPQ 430, 433 n.4 (CCPA 1977). This same rationale should also apply to product, apparatus, and process claims claimed in terms of function, property or characteristic (see MPEP 2112-III).
Re Claim 11, Kim modified by Tang and Funayama teaches the method of claim 1, further comprising depositing alternating SiO2 (110, Fig. 2B, para [0052], Kim) and SiN (120, Fig. 2B, para [0052], Kim) layers as the multi-layer stack (110/120, up to 120h, Kim).
Claims 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2017/0287929 A1, of record), Tang et al. (US 2015/0243545 A1, of record) and Funayama et al. (US 10224240 B1, of record), and further in view of Chen et al. (US 2019/0123054 A1, of record).
Re Claim 12, Kim modified by Tang and Funayama teaches the method of claim 1, further comprising depositing Si (104d is made of Si, para [0074], Kim) in the recess-etched channels (recessed channel 191, Fig. 2P).
Kim is silent about the Si being a polycrystalline material and is deposited using plasma-enhanced chemical vapor deposition.
However, in a related art, Chen teaches a caping layer 11 made of polycrystalline Si which can be formed using plasma-enhanced chemical vapor deposition (para [0071]), which will provide a suitable electrical contact for the optimal performance of the device. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to make the cap out of polycrystalline Si using the PECVD process as disclosed by Chen, into the device of Kim, so that it will provide a suitable electrical contact for the optimal performance of the device. The use of a known material/process for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Additionally, the selection of a known material/process based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Re Claim 13, Kim modified by Tang, Funayama and Chen teaches the method of claim 12, further comprising:
growing a field oxide (110i, silicon oxide, para [0052], Fig. 2A, Kim) on the multi-layer stack (110/120, up to 120h, Kim) prior to forming the high- aspect-ratio channels (103, Kim); and
planarizing the poly-Si (104d, Fig. 2P, Kim) to expose the field oxide (110i, top layer of 110 in Fig. 2P, Kim), a top surface of the field oxide and a top surface of the poly-Si in each of the high-aspect-ratio channels lying in a plane after planarization of the poly-Si (see Fig. 2P, Kim).
Re Claim 14, Kim modified by Tang Funayama and Chen teaches the method of claim 13, further comprising:
depositing an amount of the oxide (191, Fig. 2L, Kim) sufficient to cover the field oxide (191 is formed both on the channel 103 and also on the layer 145 which is on top of the field oxide layer 110i, para [0068], see Figs. 2A, 2J and 2L, Kim); and
planarizing the oxide prior to recess etching the oxide such that a top surface of the field oxide and a top surface of the oxide in each of the high-aspect-ratio-channels lie in a plane after planarization of the oxide (see para [0068], Fig. 2L, Kim).
Claims 15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2017/0287929 A1, of record), and further in view of Tang et al. (US 2015/0243545 A1, of record) and Wang et al. (US 2013/0056702 A1, of record).
Re Claim 15, Kim teaches a method of fabricating a semiconductor device, the method comprising:
etching high-aspect-ratio channels (103, Fig. 2B, para [0053]) in a multi -layer stack (110/120, up to 120h, Figs. 2A-B, para [0052]) disposed on a semiconductor substrate (101, Figs. 2A-B, para [0052])), the multi-layer stack comprising sets of silicon (Si) oxide (110, Fig. 2B, para [0052], Kim) and non-Si oxide layers (120, Fig. 2B, para [0052], Kim);
depositing, in the high-aspect-ratio channels (103), a channel oxide (191 can be silicon oxide, Fig. 2L, para [0068]),
recess etching the channel oxide (191) to form recess-etched channels (recessed 191, Fig. 2P, para [0074]) that have a depth variation of less than about 5% from an average etch depth across the channels (Fig. 2P shows that the depth of the recess of the recessed-channels 191 is constant) and a substantially constant cross-sectional area across each channel (Fig. 2P shows that the cross-sectional area across each channel 191 is substantially constant); and
capping each of the recess-etched channels (recessed 191) with a cap (104d, Fig. 2P para [0074]) to refill an etched portion of the recess-etched channels with a conductive material (104d, silicon is used to fill the recess, para [0074]).
Kim does not explicitly disclose the process of filling the high-aspect-ratio channels with the oxide. One of ordinary skill will look into related art to find an effective process to fill the channels.
In a related semiconductor art, Tang teaches a deposition of silicon oxide film to fill a channel gap using ALD process (paras [0030] - [0034]), since ALD provides precise and controlled deposition of thin films with atomic scale thickness and uniformity. Tang teaches (Fig. 6) the filling of each of the high-aspect-ratio channels with an oxide which includes:
depositing a channel oxide in multiple blocks (multiple cycles of processes 610 to 626, Fig. 6, para [0042], Tang) that each contains multiple growth cycles (multiple cycles of 614 and 618, Fig. 6, para [0042], Tang) followed by a passivation operation (step 622, Fig. 6, para [0042], Tang, see discussion below), each of the growth cycles comprising:
introducing an inhibitor into a chamber in which the semiconductor substrate is disposed during an inhibition operation (step 618, Fig. 6, para [0042], Tang), and
multiple atomic layer deposition (ALD) deposition cycles (multiple cycles of step 614, Fig. 6, para [0042], Tang);
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to deposit the silicon oxide into the channels of the semiconductor stack of Kim using the process of ALD as disclosed by Tang, since ALD provides precise and controlled deposition of thin films with atomic scale thickness and uniformity. Moreover, the selection of a known process based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Tang discloses a purge step at 622 but is silent regarding the details of the pump/purge. One of ordinary skill would look into related art for purge operation.
In a related art, Wang discloses that in a purging step, excess source gas and reactants are removed from the reaction space, for example with the aid of a purge gas (e.g., N2, He, Ar) (para [0086]), which is understood to meet the claimed passivation, as that would dilute and remove any residual activity.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to use the purging step as disclosed by Wang, into the ALD process of Tang, which is understood to meet the claimed passivation, as that would dilute and remove any residual activity (para [0086], Wang). The selection of a known material/process based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Kim also does not explicitly disclose that the depth variation of the recess and the uniformity of cross-sectional area across each channel are based on a composition of the oxide formed by the ALD process, the composition controlled at least in part on a temperature of a pedestal on which the semiconductor substrate is disposed and a pressure in a chamber containing the substrate is maintained.
However, in the related semiconductor art, Tang discloses a high quality ALD deposition technique of oxide films without any voids, as the voids cause problems during subsequent processing (paras [0004] – [0008] and [0030] - [0034]). The substrate is supported on a pedestal within a processing chamber (para [0017]), which also provides heating to control the temperature (para [0037]). The processing chamber also has a vacuum pump to maintain the pressure within the system (para [0037]). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, that the recess-depth and the cross-sectional area across each channel of Kim will be substantially constant (as shown in Fig. 2P of Kim), based on the high quality ALD deposition process of Tang which deposits a high quality of oxide films without any voids, as the voids cause problems during subsequent processing, like etching (paras [0004] – [0008] and [0030] - [0034]).
Re Claim 17, Kim modified by Tang and Wang teaches the method of claim 15, further comprising:
growing a field oxide (110i, silicon oxide, para [0052], Fig. 2A, Kim) on the multi-layer stack (110/120, up to 120h, Kim) prior to forming the high- aspect-ratio channels (103, Kim); and
planarizing the cap (104d, Fig. 2P, Kim) to expose the field oxide (110i, top layer of 110 in Fig. 2P, Kim), a top surface of the field oxide and a top surface of the cap in each of the high-aspect-ratio channels lying in a plane after the planarization (see Fig. 2P, Kim).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2017/0287929 A1, of record), Tang et al. (US 2015/0243545 A1, of record) and Wang et al. (US 2013/0056702 A1, of record), and further in view of Funayama et al. (US 10224240 B1, of record) and McDougall et al. (US 2007/0065578 A1, of record).
Re Claim 21, Kim modified by Tang and Wang teaches the method of claim 15, but does not disclose that during the deposition of the oxide the temperature of the pedestal on which the semiconductor substrate is disposed is maintained at about 550-650°C and the pressure in the chamber containing the substrate is maintained at about 10-20 Torr to provide the composition.
However, in a related semiconductor art, Funayama teaches that an atomic layer deposition process can be employed to deposit silicon oxide material where the temperature can be less than 650°C (Col. 10, lines 45 -49), which encompasses the claimed temperature range. It would have been obvious to one of ordinary skill in the art, at the time of invention, to use the temperature range as disclosed by Funayama for effective control during the ALD growth process. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990), see MPEP 2144.05(I).
In another related art, McDougall teaches that during an ALD growth process, the chamber is placed preferable between 10 mTorr and to about 50 Torr (see paras [0022] and [0060]), encompassing the claimed pressure range. It would have been obvious to one of ordinary skill in the art, at the time of invention, to use the pressure range as disclosed by McDougall for effective control during the ALD growth process. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990), see MPEP 2144.05(I).
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2017/0287929 A1, of record) and further in view of Tang et al. (US 2015/0243545 A1, of record) and Chen et al. (US 2019/0123054 A1, of record).
Re Claim 18, Kim teaches a NAND device comprising:
a multi-layer stack (110/120, up to 120h, Figs. 2A-B, para [0052]) disposed on a semiconductor substrate (101, Figs. 2A-B, para [0052]), the multi-layer stack (110/120, up to 120h) comprising pairs of layers of alternating materials (alternating layers of 110 and 120, Figs. 2A-B, para [0052]), the multi-layer stack (110/120, up to 120h) comprising a plurality of high-aspect-ratio channels disposed therein (103, Fig. 2B, para [0053]);
a field oxide (110i, silicon oxide, para [0052], Fig. 2A, Kim) disposed on the multi-layer stack (110/120, up to 120h);
a Silicon (Si) oxide disposed within each of the high-aspect-ratio channels (191 can be silicon oxide, Fig. 2L, para [0068]), the Si oxide etched such that a surface of the Si oxide is beneath the field oxide (recessed 191, Fig. 2P, top surface of recessed 191 is lower than the top surface of 110i, see also Fig. 2A), the channels (recessed 191) having a depth variation of less than about 5% from an average etch depth across the channels (Fig. 2P shows that the depth of the recess of the recessed-channels 191 is constant) and a substantially constant cross-sectional area across each channel (Fig. 2P shows that the cross-sectional area across each channel 191 is substantially constant); and
a Si cap (104d, silicon is used to fill the recess, para [0074]) disposed within each of the high-aspect-ratio channels on the Si oxide (see Fig. 2P).
Kim is silent about the oxide film being formed by an atomic layer deposition (ALD) process and also does not explicitly disclose that the depth variation of the recess and the uniformity of cross-sectional area across each channel are based on a composition of the oxide formed by the ALD process.
However, in the related semiconductor art, Tang discloses a high quality ALD deposition technique of oxide films without any voids, as the voids cause problems during subsequent processing (paras [0004] – [0008] and [0030] - [0034]). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, that the recess-depth and the cross-sectional area across each channel of Kim will be substantially constant (as shown in Fig. 2P of Kim), based on the high quality ALD deposition process of Tang which deposits a high quality of oxide films without any voids, as the voids cause problems during subsequent processing, like etching (paras [0004] – [0008] and [0030] - [0034]).
Kim is also silent about the Si being a polycrystalline material.
However, in a related art, Chen teaches a caping layer 11 made of polycrystalline Si (para [0071]), which will provide a suitable electrical contact for the optimal performance of the device. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to make the cap out of polycrystalline Si as disclosed by Chen, into the device of Kim, so that it will provide a suitable electrical contact for the optimal performance of the device. The selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Re Claim 19, Kim modified by Chen teaches the NAND device of claim18, wherein the pairs of layers of the multi- layer stack (110/120, up to 120h) includes a SiO2 layer (110 is SiO2, para [0052], Kim) and a SiN layer (120 is SiN, para [0052], Kim).
Re Claim 20, Kim modified by Chen teaches the NAND device of claim 18, wherein at least one of:
a depth of each of the high-aspect-ratio channels (103, Kim) is between about 4 and about 8 microns (Chen teaches that the alternating oxide/nitride layers can each have a width of 100 nm, para [0046] and a total number of such pairs to be 32, para [0048], resulting in a depth of 100 × 32 × 2 = 6400 nm = 6.4 microns, which is within the claimed range) and a width of each of the high-aspect-ratio channels is between about 50 nm and 100 nm (Chen teaches that the channel 604, Fig. 2E can be between 50 nm and 100 nm, para [0055]), or
a depth of the poly-Si cap in each of the high-aspect-ratio channels is about 1-4% of a depth of the high-aspect-ratio channels.
Allowable Subject Matter
Claims 2-4, 6-8 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Claim 2 is allowable for at least the reasons of, “depositing the oxide includes depositing a silicon (Si) oxide in multiple blocks that each contains multiple growth cycles followed by a passivation operation, each of the growth cycles includes introduction of an inhibitor into a chamber in which the semiconductor substrate is disposed during an inhibition operation, followed by multiple ALD deposition cycles, a number of cycles is dependent on channel width and variation, and each individual pinch point at which a corresponding channel varies is targeted by a different block”. Prior art Tang (of record) teaches most of the above limitations as detailed in the office action mailed 3/21/2025. Tang also discloses that the “number of cycles is dependent on channel width and variation” as shown in Fig. 5A-5D and para [0041], but fails to teach that “each individual pinch point at which a corresponding channel varies is targeted by a different block”. The prior art of record taken either single or in combination fails to teach or reasonably suggest the above limitation when taken in context of the independent claim 1, as a whole.
Claims 3-4, 6-8 and 10 depend from claim 2 and are allowable for at least the reasons above
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 15 and 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant stated in the “Remarks” section that he/she would like to have a formal interview if the next office action does not result in allowance. Normally, examiner expects a formal request for interview with a proposed agenda and then the examiner would discuss the proposed amendments during the interview. MPEP 703.01 states that examiner can have an interview if the application is in a condition for allowance. The application is not in a condition for allowance. Examiner respectfully requests that the applicant should request a formal interview through the automated interview request and submit an agenda with proposed amendments based on the Final Office Action.
Applicant remarks that Funayama et al. (US 10224240 B1, of record) and McDougall et al. (US 2007/0065578 A1, of record), teach a broad range of temperature and pressure ranges respectively, and do not teach the exact range recited in the limitations. Examiner respectfully disagrees with the applicant. Examiner agrees that both Funayama and McDougall teach a broader range but both encompasses the claimed limitation. Funayama teaches that the temperature can be less than 650°C (Col. 10, lines 45 -49), which encompasses the recited limitation of 550-650°C. Similarly, McDougall teaches that the pressure can be between 10 mTorr and to about 50 Torr (see paras [0022] and [0060]), which encompasses the recited limitation of 10-20 Torr. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990), see MPEP 2144.05(I). Additionally, applicant argued that Funayama does not disclose “a temperature range that enables the oxide composition or depth variation recited”. Examiner respectfully disagrees with the applicant. Funayama was relied upon to teach the temperature range while the oxide composition and the depth variation are taught by Tang (of record) and Kim (of record). “The test for obviousness is what the combined teachings of the references would have suggested to [a PHOSITA].” In re Mouttet, 686 F.3d 1322, 1333, 103 USPQ2d 1219, 1226 (Fed. Cir. 2012).
Applicant also argued that “Tang focuses on PEALD processes with inhibitor plasma treatments, which is fundamentally different from the ALD process described in the claims”. Examiner respectfully disagrees with the applicant because Tang explicitly states an ALD process (para [0042], Fig. 6, Tang) which has an inhibition stage that uses plasma (step 618, para [0042], Fig. 6, Tang). This is not a PEALD process. Tang also mentions that a similar approach can be used if PEALD is used (para [0043], Tang), clearly distinguishing from the ALD process discussed in para [0042] (of Tang). Additionally, claim 1 does not require the ALD process to be in a non-plasma environment.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PINAKI DAS whose telephone number is (703)756-5641. The examiner can normally be reached M-F 8-5 EST.
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898