Detailed Action
This office action is in response to the amendment filed May 28th, 2025. Claims 1-10 and 21-30 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed May 28th, 2025 have been fully considered but they are not persuasive.
Applicant argues (pgs. 6-11, “Remarks”) that Hu and the other cited references fail to teach the limitations presented in amended Claims 1, 9, 21, and 26.
However, as seen below, Claim 1 is rejected by the combination of Hu and Yu-830. Claim 9 is now rejected by the combination of Hu, Yu-830, and Yeo. Claim 21 is now rejected by the combination of Yu and Yu-830. Claim 26 is now rejected by a new interpretation of Hu.
Therefore, applicant’s arguments are not persuasive and are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 26 and 29 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hu et al. (2023/0154878 A1; hereinafter Hu).
Regarding Claim 26, Hu (fig. 15) teaches a method comprising:
forming a package component ([0066], 1500) comprising:
forming a bottom dielectric layer ([0048], 208); and
forming a metal pillar ([0044], 120) comprising:
a first portion ([0066], 1526) lower than a bottom surface (note that fig. 15 is rotated 180 degrees when compared to the claimed invention and therefore a bottom surface may be interpreted as a top surface) of the bottom dielectric layer (top surface of 208); and
a second portion ([0044], 124) underlying (note that fig. 15 is rotated 180 degrees when compared to the claimed invention and therefore underlying may be interpreted as overlying) and joining to the first portion (1526), wherein the first portion (1526) and the second portion (124) are formed in a same formation process ([0067], both 124 and 1526 are both formed using a photoresist material filled with conductive material) , wherein the second portion (124) is wider (224 is wider than 1528, see fig. 15) than the first portion (1526), and wherein
a first sidewall (sidewall of 1526) of the first portion (1526) and a second sidewall (sidewall of 124) of the second portion (124) form a first step (step where 1526 and 124 meet, see fig. 15).
Regarding Claim 29, Hu (fig. 15) teaches the method of claim 26, wherein the first sidewall (sidewall of 1526) and the second sidewall (sidewall of 124) are discontinuous from each other (see fig. 15).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-7, 10, and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Hu in view of Yu et al. (2013/0277830 A1; hereinafter Yu-830)
Regarding Claim 1, Hu (figs. 3-14) teaches a method comprising:
forming a first package component ([0042], 100) comprising a conductive feature ([0043], 102), and
a dielectric layer ([0048], 208) covering the conductive feature (102);
forming a first opening ([0048], 210, see fig. 4) in the dielectric layer (208), wherein the conductive feature (102) is exposed to the first opening (210);
forming a metal seed layer ([0056], 502, 504) on the dielectric layer (208), wherein the metal seed layer (502, 504) extends into the first opening (210) to contact the conductive feature (102);
forming a plating mask ([0057], 602, see fig. 6, [0060], 902, see fig. 9) over the metal seed layer (502, 504), with a second opening ([0058], 702, see fig. 7, [0061], 1002, see fig. 10) formed in the plating mask (602, 902), wherein the first opening (210) is joined to the second opening (702, 1002);
plating a conductive material ([0044], 122, 124) into the first opening (210) and the second opening (702, 1002);
removing (see fig. 12) the plating mask (602, 902) to expose portions of the metal seed layer (502, 504); and
etching ([0064], see fig. 13) the portions of the metal seed layer (502, 504), wherein the conductive material (122, 124) and a remaining portion of the metal seed layer (502, 504) collectively form a metal pillar ([0044], 120) over the dielectric layer (208).
Hu doesn’t teach the metal pillar has a top width and a bottom width smaller than the top width, with the bottom width being measured at a surface level of the dielectric layer, and wherein the top width is measured from a first exposed sidewall of the metal pillar to a second exposed sidewall opposing the first exposed sidewall, and the bottom width is measured from a third exposed sidewall of the metal pillar to a fourth exposed sidewall opposing the first exposed sidewall.
However, Yu-830 (fig. 5B) teaches the metal pillar ([0036], 122) has a top width ([0036], 312) and a bottom width ([0036], 410) smaller than the top width (312), with the bottom width (410) being measured at a surface level of the dielectric layer ([0017], surface level of 112, see fig. 2 for labeled features), and wherein the top width (312) is measured from a first exposed sidewall (left sidewall at width 312, see fig. 5B) of the metal pillar (122) to a second exposed sidewall (right sidewall at width 312, see fig. 5B) opposing the first exposed sidewall, and the bottom width (410) is measured from a third exposed sidewall (left sidewall at width 410, see fig. 5B) of the metal pillar (122) to a fourth exposed sidewall (right sidewall at width 312, see fig. 5B) opposing the first exposed sidewall. Yu-830 also teaches that this shape allows the solder to wet the sidewalls of the pillar and further strengthen the attachment of the solder ([0036]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Hu to include the pillar of Yu-830 to strengthen attachment of solder.
Regarding Claim 2, Hu (figs. 3-14) teaches the method of claim 1 further comprising bonding a second package component ([0077], 2102, see fig. 21) to the first package component (100), with the second package component (2102) being underlying the first package component (100), wherein a solder region ([0044], 126) joins the metal pillar (120) to the second package component (2102), and wherein an entirety of the solder region (126) is underlying the metal pillar (all of 126 is below 120, see fig. 21).
Regarding Claim 4, Hu (figs. 3-14) teaches the method of claim 1, wherein the forming the plating mask (602, 902) comprises: performing a first light-exposure process ([0057], 606) on the plating mask (602) using a first lithography mask ([0057], 604), wherein a first portion ([0058], 602’) of the plating mask (602) is light-exposed (see fig. 6); and performing a second light-exposure process ([0060], 906) on the plating mask (902) using a second lithography mask ([0060], 904), wherein a second portion ([0061], 902’) of the plating mask (902) is light-exposed (see fig. 9); and performing a development process ([0058], [0061]) on the plating mask (602, 902).
Regarding Claim 5, Hu (figs. 3-14) teaches method of claim 4, wherein the first portion (602’) and the second portion (902’) of the plating mask (602, 902) have different widths (see figs. 6 and 9).
Regarding Claim 6, Hu (figs. 3-14) teaches method of claim 5, wherein the first portion (602’) is wider (see figs. 6 and 9) than the second portion (902’), and wherein the second portion (902’) is deeper (see figs. 6 and 9) than the first portion (602’).
Regarding Claim 7, Hu (figs. 3-14) teaches method of claim 4, wherein the first portion (602’) and the second portion (902’) of the plating mask (602’, 902’) have different depths (see figs. 6 and 9).
Regarding Claim 10, Hu (figs. 3-14) teaches method of claim 1, wherein the metal pillar (120) comprises a sidewall (angled sidewall of 122 in between 502, see fig. 12) forming a tilt angle with a top surface of the dielectric layer (top of 208), and wherein the tilt angle is smaller than about 85 degrees (about 85 degrees is interpreted to include 90 degrees, angled sidewall of 122 and 208 form an angle below 90 degrees).
Regarding Claim 30, the combination of Hu (fig. 15) and Yu-830 (fig. 5B) teaches the method of claim 1 further comprising forming an underfill (Hu, [0078], 2110) physically contacting the first exposed sidewall (Yu-830, left sidewall at width 312), the second exposed sidewall (Yu-830, right sidewall at width 312), the third exposed sidewall (Yu-830, left sidewall at width 410), and the fourth exposed sidewall (Yu-830, right sidewall at width 410).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Hu and Yu-830 as applied to Claim 1, and further in view of Yu et al. (2018/0033771 A1; hereinafter Yu).
Regarding Claim 3, Hu doesn’t teach forming a micro-bump on the first package component, wherein the micro-bump has a first height smaller than a second height of the metal pillar; and bonding a passive device die to the first package component through the micro-bump.
However, Yu (fig. 20B) teaches the method of claim 1 further comprising: forming a micro-bump ([0047], 176) on the first package component ([0027], 160), wherein the micro-bump (176) has a first height (height of 176) smaller (see fig. 20B) than a second height (height of 162) of the metal pillar ([0038], 162); and bonding a passive device die ([0041], 170) to the first package component (160) through the micro-bump (176). Yu also teaches an integrated passive device (IPD) may boost system performance ([0011]) while the use of micro bumps enables high-density connections ([0048]) and enlarges the process window for package structures to include an IPD component ([0045]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Hu to include passive device die and micro-bumps of Yu to enable high-density connections and boost system performance.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Hu and Yu-830 as applied to Claim 4, and further in view of Yeo (2005/0224991 A1; hereinafter Yeo).
Regarding Claim 8, Hu doesn’t teach the first portion and the second portion of the plating mask include a common portion of the plating mask.
However, Yeo (annotated fig. 5D) teaches the method of claim 4, wherein the first portion (first portion, this is the portion above 210 and wherein an opening is later formed, see fig. 5E) and the second portion (second portion, this is the portion exposed through MK1) of the plating mask ([0059], PR1, [0060], PR2) include a common portion (see annotated fig. 5D) of the plating mask (PR1, PR2). Yeo then performs a single development process ([0061]) to form the opening for the metal pillar ([0062]). Yeo simplifies the process of manufacture by reducing the number of development processes required to form a metal pillar with two different widths.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Hu to utilize the single development process of Yeo to simplify the manufacturing process.
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Annotated Figure 5D
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Hu and Yu-830 as applied to Claim 4, and further in view of a second embodiment of Hu and Yeo.
Regarding Claim 9, Hu doesn’t teach the method of claim 4, wherein the second opening comprises an upper portion and a lower portion, wherein the lower portion is narrower than the upper portion, and wherein the upper portion and the lower portion form a step.
In a second embodiment, Hu (fig. 15) teaches wherein the lower portion (opening where 1526 is formed) is narrower ([0066]) than the upper portion (opening where 124 is formed) while still maintaining the function of a conductive pillar. One of ordinary skill in the art could have substituted the conductive pillar of Hu for the alternative conductive pillar of Hu’s second embodiment and yielded the predictable results of electrical connection through a conductive pillar.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the conductive pillar of Hu for the alternative conductive pillar of Hu’s second embodiment, since simple substitution of conductive pillars for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Furthermore, Yeo (fig. 5E) teaches the second opening (openings in PR2 and PR1, see fig. 5E) comprises an upper portion ([0061], opening positioned between portions of PR2) and a lower portion ([0061], opening positioned between portions of PR1), wherein the upper portion and the lower portion form a step (see fig. 5E). Yeo then performs a single development process ([0061]) to form the opening for the metal pillar ([0062]). Yeo simplifies the process of manufacture by reducing the number of development processes required to form a metal pillar with two different widths.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Hu to utilize the single development process of Yeo to simplify the manufacturing process.
Claims 21-23 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Yu-830.
Regarding Claim 21, Yu (fig. 26) teaches a method comprising:
forming a first package component ([0027], 160) comprising:
forming a bottom dielectric layer ([0027], 156);
forming a micro-bump ([0047], 176, see fig. 22C) protruding below the bottom dielectric layer (156); and
forming a metal pillar ([0038], 162) protruding below the bottom dielectric layer (156), wherein the metal pillar (162) has a top width (width of 162 between 156) and a bottom width (width of 162 below 156) greater than the top width (see fig. 26), []
bonding a die ([0041], 170) to the micro-bump (176), wherein the die (170) is underlying the micro-bump (176);
bonding a second package component ([0045], 400) to the first package component (160), wherein the second package component (400) is underlying the first package component (160), and
the second package component (400) comprises a conductive feature ([0075], 402) bonding to the metal pillar (162) through a solder region ([0050], 166) in between.
Yu doesn’t teach both of the top width and the bottom width are measured at levels lower than a bottom surface of the bottom dielectric layer.
However, Yu-830 (fig. 5B) teaches forming a metal pillar ([0036], 122) protruding below the bottom dielectric layer ([0017], 112), wherein the metal pillar (122) has a top width ([0036], 410) and a bottom width ([0036], 312) greater than the top width (410) and wherein both of the top width (410) and the bottom width (312) are measured at levels lower than a bottom surface of the bottom dielectric layer (bottom of 112, see fig. 2). Yu-830 also teaches that this shape allows the solder to wet the sidewalls of the pillar and further strengthen the attachment of the solder ([0036]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Yu to include the pillar of Yu-830 to strengthen attachment of solder.
Regarding Claim 22, Yu (fig. 26) teaches the method of claim 21, wherein a topmost end of the solder region (top of 166) is at substantially a same level as a bottom surface of the metal pillar (bottom of 162).
Regarding Claim 23, Yu (fig. 26) teaches the method of claim 21, wherein the metal pillar is formed as comprising an upper portion (portion of 162 between 156), and a lower portion (portion of 162 below 156) wider than the upper portion (see fig. 26), and wherein a first sidewall of the upper portion (sidewall of 162 in contact with sidewall of 156) and a second sidewall of the lower portion (sidewall of 162 below 156) form a step.
Regarding Claim 25, Yu (fig. 26) teaches the method of claim 23, wherein the solder region (166) is spaced apart from the first sidewall of the upper portion (sidewall of 162 in contact with sidewall 156).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Yu and Yu-830 as applied to Claim 23, and further in view of Seo et al. (2017/0084561 A1; hereinafter Seo).
Regarding Claim 24, Yu doesn’t teach the solder region extends to a topmost end of the second sidewall of the lower portion.
However, Seo (fig. 2) teaches the method of claim 23, wherein the solder region ([0036], 160) extends to a topmost end of the second sidewall ([0048], bottommost end of 156S) of the lower portion ([0042], 156). Seo also teaches that this increases the contact area and allows for a larger amount of solder to be disposed without collapsing ([0049]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Yu to include the solder placement of Seo to increase the contact area of the solder.
Claim 27-28 is rejected under 35 U.S.C. 103 as being unpatentable over Hu and Yu-830 as applied to Claim 26, and further in view of Seo.
Regarding Claim 27, Hu (fig. 15) teaches the method of claim 26, wherein forming a solder region ([0044], 126), wherein the solder region (126) is underlying and joining to an additional bottom surface of the metal pillar (top surface of 120). Hu doesn’t teach the solder region extends to a top end of the second portion of the metal pillar.
However, Seo (fig. 2) teaches the solder region ([0036], 160) extends to a top end of the second portion ([0048], bottommost end of 156S) of the metal pillar ([0036], 150). Seo also teaches that this increases the contact area and allows for a larger amount of solder to be disposed without collapsing ([0049]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Hu to include the solder placement of Seo to increase the contact area of the solder.
Regarding Claim 28, Hu (fig. 15) teaches the method of claim 27, wherein the metal pillar (120) further comprises a third portion ([0044], 122) over the first portion (1526), wherein the third portion (122) forms a second step (step where 1526 and 122 meet, see fig. 15) with the first portion (1526) of the metal pillar (120).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADIN HRNJIC whose telephone number is (571)270-1794. The examiner can normally be reached Monday-Friday 8:00 AM - 4:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/A.H./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 September 13, 2025
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