DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 35 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/03/2026 has been entered.
Remarks
The 03/19/2026 amendments of claims 1, 15, 17 and 25 have been noted and entered.
Response to Arguments
Applicant’s arguments, see Remarks pages 10-12, filed 03/19/2026, with respect to the rejection(s) of claim(s) 1,3-10,15-20 and 25-28 under 35 U.S.C. 103 have been fully considered and are persuasive in light of the newly added amendments. However, upon further consideration, a new ground(s) of rejection is made in view of Ching et al, US 20220148979 A1 (Ching), Suzuki et al, US 20200198193 A1 (Suzuki), Beatty et al, US 20190006293 A1 (Beatty) and Sugiyama et al, US 20170243854 A1 (Sugiyama).
New Grounds of Rejection
New grounds of rejection, prior art references Ching et al, US 20220148979 A1 (Ching), Suzuki et al, US 20200198193 A1 (Suzuki), Beatty et al, US 20190006293 A1 (Beatty) and Sugiyama et al, US 20170243854 A1 (Sugiyama) appear below.
Claim Objections
Claim 27 is objected to because of the following informalities:
Regarding claim 27; the claim contains, in line 3, the following limitations: “wherein the first length is a greater than the second length.” (emphasis added). A suggestion for correcting the language is to change the phrasing to: “wherein the first length is greater than the second length.”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 27 recites the limitation "… wherein the portion of the interconnect access structure is a first length…" (emphasis added) in line 2 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-4, 7-9, 15-17 and 25-28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ching et al, US 20220148979 A1 (Ching).
Regarding claim 1; Ching teaches a semiconductor package (Ching: Annotated Fig (24) shared in this OA: 30a), comprising:
an interposer (Interposer);
one or more integrated circuit dies (110), wherein the one or more integrated circuit dies (110) are electrically connected to a top surface of the interposer (Interposer);
a substrate (Top Layer + 500 + Bottom Layer) comprising a top layer (Top layer), a bottom layer (Bottom Layer), and a reinforcement structure (500) between the top layer (Top Layer) and the bottom layer (Bottom Layer),
wherein an interconnect access structure (510 + 520 + 530) electrically connects electrically-conductive traces (510) of the top layer (Top Layer) to electrically conductive traces (520) of the bottom layer (Bottom Layer, [0050]: “… In some embodiments, some of the bonding pads 510 are electrically connected to the bonding pads 520 through the metallization layers 530 and vias. In some embodiments, some of the bonding pads 510 are electrically connected to some other of the bonding pads 510 through the metallization layers 530 and vias. In some embodiments, some of the bonding pads 520 are electrically connected to some other of the bonding pads 520 through the metallization layers 530 and vias. The disclosure is not limited thereto.”),
wherein an aspect ratio of a width of the reinforcement structure (500) to a thickness of the reinforcement structure (500) is greater relative to an aspect ratio of a width of the interconnect access structure (510 + 520 + 530) to a length of the interconnect access structure (510 + 520 + 530),
the width of the interconnect access structure (510 + 520 + 530) being perpendicular to the thickness of the interconnect access structure (510 + 520 + 530) wherein the reinforcement structure (500) is configured to improve a rigidity of the semiconductor package (30a) to reduce a warpage of the substrate (Top Layer + 500 + Bottom Layer);
a stiffener structure (600C, claim 13 of Ching recites a “stiffener ring”, [0091]: “… the ring structure 600C…”) mounted to the substrate (Top Layer + Interposer + 500 + Bottom Layer), wherein the reinforcement structure (500) comprises a first portion underlapping the interposer (Interposer) and a second portion underlapping the stiffener structure (600C, claim 13 of Ching recites a “stiffener ring”, [0091]: “… the ring structure 600C…”) , and wherein the interposer (Interposer) comprises a top surface (Top Surface of Interposer) and a bottom surface (Bottom Surface of Interposer), wherein the top surface of the interposer (Top Surface of Interposer) is below a top surface (600t) of the stiffener structure (600C, claim 13 of Ching recites a “stiffener ring”, [0091]: “… the ring structure 600C…”) and above a bottom surface (600b) of the stiffener structure (600C, claim 13 of Ching recites a “stiffener ring”, [0091]: “… the ring structure 600C…”) , and wherein the bottom surface of the interposer (Bottom Surface of Interposer) is above the bottom surface (600b) of the stiffener structure (600C, claim 13 of Ching recites a “stiffener ring”, [0091]: “… the ring structure 600C…”) and below the top surface (600t) of the stiffener structure (600C, claim 13 of Ching recites a “stiffener ring”, [0091]: “… the ring structure 600C…”) ; and
a plurality of connection structures (140) that electrically connect the substrate (Top Layer + 500 + Bottom Layer) and the interposer (Interposer).
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Regarding claim 3; Ching teaches all the limitations of the semiconductor package of claim 1.
Further, Ching teaches wherein the at least one reinforcement structure (Ching: Annotated Fig (24) shared in this OA: 530) comprises: one or more thermally-conductive structures (510 + 520 + 530) to conduct heat through the substrate (Top Layer + 500 + Bottom Layer, [0050]: “… In some embodiments, some of the bonding pads 510 are electrically connected to the bonding pads 520 through the metallization layers 530 and vias. In some embodiments, some of the bonding pads 510 are electrically connected to some other of the bonding pads 510 through the metallization layers 530 and vias. In some embodiments, some of the bonding pads 520 are electrically connected to some other of the bonding pads 520 through the metallization layers 530 and vias. The disclosure is not limited thereto.”, given that these interconnection structures are made out of metallic materials they are bound to conduct thermal energy as well).
Regarding claim 4; Ching teaches all the limitations of the semiconductor package of claim 1.
Further, Ching teaches wherein the at least one reinforcement structure (Ching: Annotated Fig (24) shared in this OA: 500) comprises: a location below at least one of the one or more integrated circuit dies (110) to shield an electromagnetic field originating from the at least one of the one or more integrated circuit dies (110, [0050], given that the reinforcement structure 500 contains the metallic conductive structures 510 + 520 + 530 then they are bound due to their metallic nature to shield some the electromagnetic fields produced by the dies 110).
Regarding claim 7; Ching teaches all the limitations of the semiconductor package of claim 1.
Further, Ching teaches wherein the reinforcement structure (Ching: Annotated Fig (24) shared in this OA: 500) comprises: a material having a Young's modulus that is greater than approximately 50 gigapascals ([0047]: “The substrate 500 may be made of a semiconductor material such as silicon, germanium, diamond, or the like. In some embodiments, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these, and the like, may also be used.”, several of these material, for example, silicon and germanium have Young’s modulus that is greater than approximately 50 gigapascals).
Regarding claim 8; Ching teaches all the limitations of the semiconductor package of claim 1.
Further, Ching teaches wherein substrate (Top layer + 500 + Bottom Layer): a layout pattern comprising reinforcement structures (500) located near approximate corners of the substrate (Top layer + 500 + Bottom Layer).
Regarding claim 9; ; Ching teaches all the limitations of the semiconductor package of claim 1.
Further, Yi teaches wherein the substrate (Top layer + 500 + Bottom Layer) comprises: a layout pattern comprising reinforcement structures (500) located near approximate corners and approximate edges of the substrate (Top layer + 500 + Bottom Layer).
Regarding claim 15; Ching teaches a semiconductor package (Ching: Annotated Fig (24) shared in this OA: 30a), comprising:
an interposer (Interposer);
a substrate (Top Layer + 500 + Bottom Layer) comprising:
a bottom core layer (Bottom Layer);
a top core layer (Top Layer);
a binding material layer ([0047]: “… The substrate 500 may be made of a semiconductor material such as silicon, germanium, diamond,… One example core material is fiberglass resin such as flame-retardant class 4 (FR4). Alternatives for the core material may include bismaleimide triazine (BT) resin, or alternatively, other printed circuit board (PCB) materials or films”) between the top core layer (Top Layer) and the bottom core layer (Bottom Layer); and
a reinforcement structure (500) embedded within the binding material layer (500) to reduce a warpage of the substrate (Top Layer + 500 + Bottom Layer),
wherein the reinforcement structure (500) is contiguous; and
a stiffener structure(600C, claim 13 of Ching recites a “stiffener ring”, [0091]: “… the ring structure 600C…”) over the substrate (Top Layer + 500 + Bottom Layer), wherein a portion of the stiffener structure (600C, claim 13 of Ching recites a “stiffener ring”, [0091]: “… the ring structure 600C…”) overlaps a portion of the reinforcement structure (500),
wherein the interposer (Interposer) and the stiffener structure (600C, claim 13 of Ching recites a “stiffener ring”, [0091]: “… the ring structure 600C…”) extend entirely above a top most surface of the substrate (Top Layer + 500 + Bottom layer), and
wherein the interposer (Interposer) comprises a top surface (Top Surface of Interposer) and a bottom surface (bottom Surface of Interposer), wherein the top surface of the interposer (Top Surface of Interposer) is below a top surface (600t) of the stiffener structure(600C, claim 13 of Ching recites a “stiffener ring”, [0091]: “… the ring structure 600C…”) and above a bottom surface (600b) of the stiffener structure (600C, claim 13 of Ching recites a “stiffener ring”, [0091]: “… the ring structure 600C…”), and wherein the bottom surface of the interposer (Bottom Surface of Interposer) is above the bottom surface (600b) of the stiffener structure (600C, claim 13 of Ching recites a “stiffener ring”, [0091]: “… the ring structure 600C…”) and below the top surface (600t) of the stiffener structure (600C, claim 13 of Ching recites a “stiffener ring”, [0091]: “… the ring structure 600C…”).
Regarding claim 16; Ching teaches all the limitations of the semiconductor package of claim 15.
Further, Ching teaches wherein the reinforcement structure (Ching: Annotated Fig (24) shared in this OA: 500) comprises a silicon material, a silicon-oxide material, a stainless-steel material, or a copper material ([0047]: “The substrate 500 may be made of a semiconductor material such as silicon, germanium, diamond, or the like.).
Regarding claim 17; Ching teaches all the limitations of the semiconductor package of claim 15.
Further, Ching teaches wherein the binding material (Ching: Annotated Fig (24) shared in this OA: 500) layer comprises a fabric material pre-impregnated with a resin material, and wherein top core layer comprises a fiberglass-epoxy laminate material or a buildup film material, and wherein the bottom core layer comprises a fiberglass-epoxy laminate material or a buildup film material ([0047]: “… In further alternative embodiments, the substrate 500 is based on an insulating core, such as a fiberglass reinforced resin core. One example core material is fiberglass resin such as flame-retardant class 4 (FR4). Alternatives for the core material may include bismaleimide triazine (BT) resin, or alternatively, other printed circuit board (PCB) materials or films. In yet further alternative embodiments, the substrate 500 is a build-up film such as Ajinomoto build-up film (ABF) or other suitable laminates.”).
Regarding claim 25; Ching teaches a semiconductor package (Ching: Annotated Fig (24) shared in this OA: 30a), comprising:
an interposer (Interposer);
a substrate (Top Layer + 500 + Bottom Layer), comprising: a bottom core layer (Bottom Layer), a top core layer (Top Layer), a reinforcement structure (500) between the top core layer (Top Layer) and the bottom core layer (Bottom Layer), and
an interconnect access structure (510 + 520 + 530), extending through the reinforcement structure (500), electrically connecting electrically-conductive traces (510) of the top core layer (Top Layer) to electrically- conductive traces (520) of the bottom core layer (Bottom Layer, [0050]: “… In some embodiments, some of the bonding pads 510 are electrically connected to the bonding pads 520 through the metallization layers 530 and vias. In some embodiments, some of the bonding pads 510 are electrically connected to some other of the bonding pads 510 through the metallization layers 530 and vias. In some embodiments, some of the bonding pads 520 are electrically connected to some other of the bonding pads 520 through the metallization layers 530 and vias. The disclosure is not limited thereto.”); and
a stiffener structure (600C, claim 13 of Ching recites a “stiffener ring”, [0091]: “… the ring structure 600C…”) mounted to the top core layer (Top Layer) of the substrate (Top Layer + 500 + Bottom Layer),
wherein the reinforcement structure (500) comprises a first portion underlapping the interposer (Interposer) and a second portion underlapping the stiffener structure (600C, claim 13 of Ching recites a “stiffener ring”, [0091]: “… the ring structure 600C…”), and
wherein the interposer (Interposer) comprises a top surface (Top Surface of Interposer) and a bottom surface (Bottom Surface of Interposer),
wherein the top surface of the interposer (Top Surface of Interposer) is below a top surface (600t) of the stiffener structure (600C, claim 13 of Ching recites a “stiffener ring”, [0091]: “… the ring structure 600C…”) and above a bottom surface (600b) of the stiffener structure (600C, claim 13 of Ching recites a “stiffener ring”, [0091]: “… the ring structure 600C…”), and
wherein the bottom surface of the interposer (Bottom Surface of Interposer) is above the bottom surface (600b) of the stiffener structure (600C, claim 13 of Ching recites a “stiffener ring”, [0091]: “… the ring structure 600C…”) and below the top surface (600t) of the stiffener structure (600C, claim 13 of Ching recites a “stiffener ring”, [0091]: “… the ring structure 600C…”).
Regarding claim 26; Ching teaches all the limitations of the semiconductor package of claim 25.
Further, Ching teaches wherein the stiffener structure (Ching: Annotated Fig (24) shared in this OA: 600C, claim 13 of Ching recites a “stiffener ring”, [0091]: “… the ring structure 600C…”) overlaps a portion of the reinforcement structure (500).
Regarding claim 27; Ching teaches all the limitations of the semiconductor package of claim 26.
Ching teaches wherein the portion (Ching: Annotated Fig 24) shared in this OA: L1 of a portion of 530) of the interconnect access structure (510 + 520 + 530) is a first length, wherein the portion (L2 of a portion of 500) of the reinforcement structure (500) is a second length, wherein the first length is a greater than the second length (comparing the two lengths shown in annotated Fig (24) shows that the first length is greater than the second length).
Regarding claim 28; Ching teaches all the limitations of the semiconductor package of claim 25.
Further, Ching teaches wherein the interconnect access structure (Ching: Annotated Fig (24) shared in this OA: 510 + 520 + 530) extends into the top core layer (Top Layer) and the bottom core layer (Bottom Layer) to electrically connect the electrically-conductive traces (510) of the top core layer (Top Layer) to the electrically-conductive traces (520) of the bottom core layer (Bottom Layer, [0050]: “… In some embodiments, some of the bonding pads 510 are electrically connected to the bonding pads 520 through the metallization layers 530 and vias. In some embodiments, some of the bonding pads 510 are electrically connected to some other of the bonding pads 510 through the metallization layers 530 and vias. In some embodiments, some of the bonding pads 520 are electrically connected to some other of the bonding pads 520 through the metallization layers 530 and vias. The disclosure is not limited thereto.”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Ching et al, US 20220148979 A1 (Ching) in view of Wang et al, CN 114284220 A (Wang).
Regarding claim 5; Ching teaches all the limitations of the semiconductor package of claim 1.
Further Ching teaches wherein the reinforcement structure (Ching: Annotated Fig (24) shared in this OA: 500) comprises: a region that underlaps with the interposer (Interposer), wherein a length of the region is included in a range of approximately 0.3 millimeters to approximately 1.5 millimeters.
Ching does not teach wherein a length of the region is included in a range of approximately 0.3 millimeters to approximately 1.5 millimeters.
Wang teaches wherein a length of the region (Wang: Fig (8): overlapping region between the reinforcement structure 140 and the interposer) is included in a range of approximately 0.3 millimeters to approximately 1.5 millimeters (Page: 6 Lines: 19-20 of the translated version of the specification of Wang recite the following: “… the width W140 of the bottom reinforcement 140 may be less than 1 mm (mm) and may be similar to the diameter of the conductor terminal 130”, by examining annotated Fir (9) it appears that the overlap falls in the range recited in the instant claim.).
Ching and Wang are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Ching by making the underlapping length within the range disclosed in Wang to make the reinforcement structure effective in preventing the undesirable warping of the package in case of high temperature exposure during processing.
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Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Ching et al, US 20220148979 A1 (Ching) in view of Suzuki et al, US 20200198193 A1 (Suzuki)
Regarding claim 18; Ching teaches all the limitations of the semiconductor package of claim 15.
However, Ching does not teach wherein an area of the reinforcement structure is included in a range of approximately 1% of an area of the substrate to approximately 30% of the area of the substrate.
Suzuki teaches wherein an area of the reinforcement structure (Suzuki: Fig (5): 3) is included in a range of approximately 1% of an area of the substrate to approximately 30% ([0041]: “FIG. 5 is a schematic diagram of an integrally molded body obtained in Example 27, and an embodiment in which an area of a substrate for reinforcement is 30% of a projected area of the integrally molded body on a surface where the substrate for reinforcement is integrated.”) of the area of the substrate (4).
Ching and Suzuki are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Ching by making the size of the reinforcement structure within the range disclosed in Suzuki to ensure the effectiveness of the treatment against warpage due to thermal processing of the package leading to a more reliable device.
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Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Ching et al, US 20220148979 A1 (Ching) in view of Beatty et al, US 20190006293 A1 (Beatty).
Regarding claim 6; Ching teaches all the limitations of the semiconductor package of claim 1.
Ching does not teach wherein the reinforcement structure comprises: a region that underlaps with the stiffener structure, wherein a length of the region is included in a range of approximately 1.0 millimeter to approximately 10.0 millimeters.
Beatty teaches wherein the reinforcement structure (Beatty: Fig (1A): 102) comprises: a region that underlaps with the stiffener structure (103), wherein a length of the region is included in a range of approximately 1.0 millimeter to approximately 10.0 millimeters ([0026]: “… A maximal lateral length (in a second lateral direction perpendicular to the first lateral direction) of the stiffener structure 103 may be between 1 mm and 10 mm (or e.g. between 1 mm and 8 mm, or e.g. between 1 mm and 5 mm).”, the stiffener structure 103 and the reinforcement structure 102 seem to underlap for the entirety of the length of the stiffener structure 103 and thus the limitation recited in the instant claim is met).
Ching and Beatty are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Ching by making the underlapping length between the reinforcement structure and the stiffener structure in the range disclosed in Beatty to improve the effectiveness of the structure resisting warpage leading to a more reliable device.
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Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Ching et al, US 20220148979 A1 (Ching) in view of Sugiyama et al, US 20170243854 A1 (Sugiyama).
Regarding claim 19; Ching teaches all the limitations of the semiconductor package of claim 15.
Ching does not teach wherein the reinforcement structure comprises: a width that is included in a range of approximately 5.0 millimeters to approximately 10.0 millimeters; and a length that is included in a range of approximately 5.0 millimeters to approximately 10.0 millimeters.
Sugiyama teaches wherein the reinforcement structure (Sugiyama: Fig (7D): 23) comprises: a width that is included in a range of approximately 5.0 millimeters to approximately 10.0 millimeters; and a length that is included in a range of approximately 5.0 millimeters to approximately 10.0 millimeters ([0046]: “… for example. The size of the reinforcement member 23 has no particular limitations, and the length of each side is 5 to 20 mm”).
Ching and Sugiyama are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Ching by making the length and width of the reinforcement structure in the range disclosed in Sugiyama to improve the stiffness of the structure and increase its ability to resist warpage leading to a more reliable device.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Ching et al, US 20220148979 A1 (Ching) in view of Sinha et al, US 20220077076 A1 (Sinha).
Regarding claim 10; Ching teaches all the limitations of the semiconductor package of claim 1.
However, Ching does not teach wherein the substrate comprises: a layout pattern comprising one or more ring-shaped reinforcement structures around a periphery of the substrate.
Sinha teaches wherein the substrate (Sinha: Fig (3G): 310g) comprises: a layout pattern comprising one or more ring-shaped reinforcement structures (330g) around a periphery of the substrate (310g).
Ching and Sinha are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Ching by using the shape and structure of the reinforcement structure disclosed in Sinha to improve the resilience of the device layers to warpage leading to a more reliable device.
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Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Ching et al, US 20220148979 A1 (Ching) in view of Bacha et al, US 20230299013 A1 (Bacha).
Regarding claim 20; Ching teaches all the limitations of the semiconductor package of claim 15.
However, Ching does not teach wherein the reinforcement structure comprises: a thickness that is included in a range of approximately 0.5 millimeters to approximately 1.5 millimeters.
Bacha teaches wherein the reinforcement structure comprises: a thickness that is included in a range of approximately 0.5 millimeters to approximately 1.5 millimeters (Bacha: [0053]: “… The core 101 may have any suitable dimensions, including a thickness 198 between 0.1 millimeters and 1.4 millimeters.”).
Ching and Bacha are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Ching by making the thickness of the reinforcement structure in the range disclosed by Bacha to ensure its effectiveness against warpage of the package induced by thermal treatment of the package during installation of processing.
Conclusion
Prior art made of record but not relied upon is considered pertinent to applicant’s disclosure:
Wang et al, US 20230378042 A1 (Wang); discloses a stiffener structure mounted on a substrate and an interposer.
Lai et al, US 20230064277 A1 (Lai); discloses a stiffener structure and an interposer along with interconnect access structures.
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/M.K./Examiner, Art Unit 2817 /NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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