DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/13/2026 has been considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9-14, 21, 22, 24-34 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (US Pub. 2011/0254160) in view of Jeng et al. ((US Pat. 11,810,830 – provided on IDS) – using US Pub. 2021/0074600 for citations) and Chen et al. (US Pub. 2017/0194226).
Regarding independent claim 9, Tsai teaches a method (Figs. 1A-1K; para. 0013+), comprising:
forming a cavity (29) within a surface of an interposer (100) having interspersed layers of electrically-conductive traces (Fig. 1I; para. 0022);
attaching an integrated circuit device (40) to the interposer within the cavity (Fig. 1; para. 0022); and
attaching, after attaching the integrated circuit device, a substrate (50) to the surface of the interposer (Fig. 1K; para. 0024),
wherein the substrate is entirely above or below the integrated circuit device (Fig. 1K).
Tsai does not teach wherein an entirety of the integrated circuit device resides above the interposer.
Jeng teaches a similar method wherein the depth of the cavity is variable depending on the routing requirements of the connected devices (Fig. 1D; para. 0039).
Chen teaches a similar method (Figs. 8-9) including attaching an integrated circuit device (203) to an interposer within a cavity (829) (Fig. 1; para. 0022); and wherein an entirety of the integrated circuit device resides above the interposer (Fig. 9; para. 0096).
It would have been obvious to one of ordinary skill in the art at the time of filing to optimize the depth of the cavity of Tsai as taught by Jeng such that an entirety of the integrated circuit device resides above the interposer as shown possible by Chen to arrive at the claimed invention for the purpose of providing appropriate routing of the connected devices (Jeng para. 0039).
Re claim 10, Tsai teaches wherein attaching the integrated circuit device to the interposer within the cavity comprises:
attaching the integrated circuit device to the interposer within the cavity using connection structures (36) between the integrated circuit device and a layer of electrically-conductive traces, of the interspersed layers of electrically-conductive traces, that are exposed at a bottom surface of the cavity (Fig. 1H; para. 0021).
Re claim 11, Tsai teaches wherein attaching the integrated circuit device to the interposer within the cavity comprises:
attaching the integrated circuit device to the interposer within the cavity using connection structures (36) between the integrated circuit device and land structures extending through a bottom surface to a layer of electrically-conductive traces, of the interspersed layers of electrically- conductive traces, below the bottom surface ((Fig. 1I, 1H; para. 0021).
Re claim 12, Tsai is silent with respect to attaching a second integrated circuit device to the interposer within the cavity and adjacent to the first integrated circuit device.
Tsai teaches wherein the integrated circuit device is a memory die (para. 0022).
It would have been obvious to one of ordinary skill in the art at the time of filing to provide a second integrated circuit device as claimed for the purpose of providing additional memory. Attaching a second integrated circuit device to the interposer within the cavity and adjacent to the first integrated circuit device amounts to a mere duplication of parts which is not considered to have patentable significance unless a new and unexpected result is produced (MPEP 2144.04, VI, B).
Re claim 13, Tsai teaches wherein forming the cavity within the first surface of the interposer comprises: forming the cavity using a patterning and etching process (Fig. 1C; para. 0018).
Re claim 14, Tsai teaches wherein forming the cavity within the first surface of the interposer comprises forming the cavity using an etching process (para. 0018) as opposed to a laser ablation process.
Jeng teaches a similar method wherein the analogous cavity (Fig. 1D: 118) can be formed using an etching process or a laser ablation process (para. 0040).
It would have been obvious to one of ordinary skill in the art at the time of filing to predictably substitute the etching method of Tsai with the laser ablation method as taught by Jeng for forming the cavity with a reasonable expectation of success. It is considered obvious to substitute one known method for another to obtain predictable results (MPEP 2143, I, B).
Regarding independent claim 21, Tsai teaches a method (Figs. 1A-1K; para. 0013+), comprising:
attaching an integrated circuit die (22) to a first surface of an interposer (100) (Fig. 1B; para. 0017);
forming, after attaching the integrated circuit die, a cavity (29) in a second surface of the interposer to expose one or more lands or traces of the interposer, wherein the second surface is opposite from the first surface (Fig. 1C; para. 0018);
forming one or more first portions (36) of one or more first connection structures on each of the one or more lands or traces of the interposer (Fig. 1H; para. 0021); and
attaching one or more second portions (solder bumps of IC 40) of the one or more first connection structures, of an integrated circuit device (40), to the one or more first portions of connection structures to complete the one or more first connection structures, and wherein the integrated circuit device is different from the integrated circuit die (Fig. 1I; para. 0022).
Tsai does not teach wherein an entirety of the integrated circuit device resides above the interposer.
Jeng teaches a similar method wherein the depth of the cavity is variable depending on the routing requirements of the connected devices (Fig. 1D; para. 0039).
Chen teaches a similar method (Figs. 8-9) including attaching an integrated circuit device (203) to an interposer within a cavity (829) (Fig. 1; para. 0022); and wherein an entirety of the integrated circuit device resides above the interposer (Fig. 9; para. 0096).
It would have been obvious to one of ordinary skill in the art at the time of filing to optimize the depth of the cavity of Tsai as taught by Jeng such that an entirety of the integrated circuit device resides above the interposer as shown possible by Chen to arrive at the claimed invention for the purpose of providing appropriate routing of the connected devices (Jeng para. 0039).
Re claim 22, Tsai teaches dispensing an underfill material (42) around the one or more first connection structures and between the integrated circuit device and the cavity (Fig. 1I; para. 0022).
Re claim 24, Tsai teaches wherein an etch is performed to etch a portion of the substrate to form the cavity (para. 0018).
Tsai is silent with respect to dispensing a photoresist material on the interposer, wherein the cavity is formed using the photoresist material.
Tsai does disclose other etch steps (Fig. 1G) that use include dispensing a photoresist material (31) on the interposer, followed by etching away unwanted portions of the interposer using the photoresist material (para. 0020).
It would have been obvious to one of ordinary skill in the art at the time of filing to dispense photoresist material on the interposer wherein the cavity was formed using the photoresist material for the purpose of protecting the portions of the interposer that were not desired to be etched during the etching of the cavity.
Re claim 25, Tsai teaches joining a first surface of the interposer to a temporary carrier (26), wherein the cavity is formed in a second surface of the interposer and after joining the first surface (Fig. 1C; para. 0018); and removing the temporary carrier after attaching the one or more second portions of the connection structures (Fig. 1K; para. 0024).
Re claim 26, Tsai teaches encapsulating the integrated circuit device in a mold compound (28), wherein the cavity is formed in the second surface of the interposer after encapsulating the integrated circuit device (para. 0018).
Re claim 27, Tsai teaches attaching the interposer to a substrate (50) using one or more second connection structures (44) connecting the one or more lands or traces of the interposer to one or more lands or traces of the substrate (Fig. 1J, IK; para. 0023).
Re claim 28, Tsai teaches wherein the cavity provides a clearance between the integrated circuit device and the substrate (Fig. 1J; para. 0023).
Regarding independent claim 29, Tsai teaches a method (Figs. 1A-1K; para. 0013+), comprising:
attaching an integrated circuit die (22) to a first surface of an interposer (100) (Fig. 1B; para. 0017);
forming, after attaching the integrated circuit die, a cavity (29) in a second surface of the interposer, wherein the second surface is opposite from the first surface (Fig. 1C; para. 0018);
attaching an integrated circuit device (40) to the interposer within the cavity, wherein the integrated circuit device is different from the integrated circuit die (Fig. 1I; para. 0022); and
attaching a substrate (50) to the second surface of the interposer (Fig. 1K; para. 0024).
Tsai does not teach wherein an entirety of the integrated circuit device resides above the interposer.
Jeng teaches a similar method wherein the depth of the cavity is variable depending on the routing requirements of the connected devices (Fig. 1D; para. 0039).
Chen teaches a similar method (Figs. 8-9) including attaching an integrated circuit device (203) to an interposer within a cavity (829) (Fig. 1; para. 0022); and wherein an entirety of the integrated circuit device resides above the interposer (Fig. 9; para. 0096).
It would have been obvious to one of ordinary skill in the art at the time of filing to optimize the depth of the cavity of Tsai as taught by Jeng such that an entirety of the integrated circuit device resides above the interposer as shown possible by Chen to arrive at the claimed invention for the purpose of providing appropriate routing of the connected devices (Jeng para. 0039).
Re claim 30, Tsai teaches wherein the integrated circuit device is attached to the interposer within the cavity via one or more connection structures (36) (para. 0021).
Re claim 31, Tsai teaches wherein the one or more connection structures are surrounded by an underfill material (42) (para. 0022).
Re claim 32, Tsai teaches wherein the integrated circuit device is attached to one or more layers of electrically- conductive traces of the interposer (Fig. 1I; para. 0022).
Re claim 33, Tsai teaches wherein the integrated circuit device is attached to the one or more layers of electrically- conductive traces via one or more land structures (36) that extend through a bottom surface of the cavity (Fig. 1H, 1I; para. 0021-0022).
Re claim 34, Tsai teaches wherein the integrated circuit device is attached to at least one, of the one or more layers of electrically-conductive traces, exposed at a bottom surface of the cavity (Fig. 1H, 1I; para. 0021-0022).
Claim(s) 23 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (US Pub. 2011/0254160) in view of Jeng et al. ((US Pat. 11,810,830 – provided on IDS) – using US Pub. 2021/0074600 for citations) and Chen et al. (US Pub. 2017/0194226) and further in view of Pan (US Pat. 6,423,939).
Re claim 23, Tsai teaches wherein the one or more first portions of connection structures comprises one or more underbump metallization (UBM) structures (para. 0021).
Tsai is silent with respect to solder plating structures; however, Fig. 1l does show what appears to be solder bumps between the UBM and the integrated circuit device.
Pan teaches a similar device (Figs. 1, 2) wherein the analogous connection structures include one or more underbump metallization (UBM) structures (134) and one or more solder plating structures (136) (Col. 4 lines (1-16)).
It would have been obvious to one of ordinary skill in the art at the time of filing to predictably substitute the apparent solder balls of Tsai with solder plating structures disclosed by Pan for the purpose of attaching the integrated circuit device to the interposer. It is considered obvious to substitute one known element for another to obtain predictable results (MPEP 2143, I, B).
Response to Arguments
Applicant’s arguments filed 05/15/2026 have been fully considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment (with respect to claims 9-14) necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Applicant's submission of an information disclosure statement under 37 CFR 1.97(c) with the timing fee set forth in 37 CFR 1.17(p) on 07/13/2026 prompted the new ground(s) of rejection (with respect to claims 21-34) presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 609.04(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOLLY KAY REIDA whose telephone number is (571)272-4237. The examiner can normally be reached M-F 8:30-5:00PM.
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/MOLLY K REIDA/ Examiner, Art Unit 2899
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