DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Continued Examination Under 37 CFR 1.114 3
III. Claim Rejections - 35 USC § 103 3
A. Claims 21, 22, 26, and 27 are rejected under 35 U.S.C. 103 and being unpatentable over US 2021/0366863 (“Wu-863”) in view of US 2021/0375785 (“Wu-785”). 3
B. Claims 1-5, 7-10, 21-26, 28, 29, and 31 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0335726 (“Wu-726”) in view of Wu-785 and Wu-863. 11
C. Claims 1-4, 6, 7, 9, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Wu-863 in view of US 2021/0225780 (“Wu-780”) and Wu-785. 22
IV. Response to Arguments 29
Conclusion 30
[The rest of this page is intentionally left blank.]
I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant’s submission filed on 12/08/2025 has been entered.
III. Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 21, 22, 26, and 27 are rejected under 35 U.S.C. 103 and being unpatentable over US 2021/0366863 (“Wu-863”) in view of US 2021/0375785 (“Wu-785”).
Each of the applied references, Wu-863 and Wu-785 has a common Assignee with the Instant Application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
In addition to including any one of the statements pursuant to 35 U.S.C. 102(b)(2)(A) through (C), (supra), to overcome each of Wu-863 and Wu-785 as prior art available under 35 USC 102(a)(2), each is still applicable as prior art under 35 U.S.C. 102(a)(1) that cannot be excepted under 35 U.S.C. 102(b)(2)(C). In this instance, Applicant may rely on the exception under 35 U.S.C. 102(b)(1)(A) to overcome this rejection under 35 U.S.C. 102(a)(1) by a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application, and is therefore not prior art under 35 U.S.C. 102(a)(1). Alternatively, applicant may rely on the exception under 35 U.S.C. 102(b)(1)(B) by providing evidence of a prior public disclosure via an affidavit or declaration under 37 CFR 1.130(b).
Turning now to the rejection …
Claim 21 reads,
21. (Currently amended) A method comprising:
[1a] forming a build-up package substrate that comprises:
[1b] a first plurality of redistribution lines (RDLs);
[1c] an interconnect die bonded to the first plurality of RDLs;
[1d] a first encapsulant encapsulating the interconnect die therein; and
[1e] a second plurality of RDLs on an opposite side of the first encapsulant than the first plurality of RDLs;
[2a] bonding a first package component and a second package component to the build-up package substrate,
[2b] wherein the first package component and the second package component are electrically interconnected through the interconnect die, and
[3a] wherein the first plurality of RDLs comprise:
[3b] a first plurality of vias over the interconnect die, wherein the first plurality of vias are tapered and have upper widths smaller than respective lower widths; and
[3c] a second plurality of vias over and electrically coupled to the first plurality of vias,
[3d] wherein the second plurality of vias are tapered and have upper widths greater than respective lower widths;
[4] bonding an organic package substrate to the build-up package substrate; and
[5] attaching a stiffener ring to the first encapsulant through an adhesive film.
With regard to claim 21, Wu-863 discloses,
21. (Currently amended) A method comprising:
[1a] forming a build-up package substrate [i.e. “redistribution structure 200” (¶ 17; Figs. 1, 23)] that comprises:
[1b] a first plurality of redistribution lines (RDLs) 110, 116 [¶¶ 22, 31-35; Figs. 4-6];
[1c] an interconnect die 120 bonded to the first plurality of RDLs 110, 116 [¶¶ 36-37, 47-48; Figs. 7-8];
[1d] a first encapsulant 140 encapsulating the interconnect die 120 therein [¶¶ 50-51; Fig. 10]; and
[1e] a second plurality of RDLs 150/154/158/162 on an opposite side of the first encapsulant 140 than the first plurality of RDLs 110, 116 [¶¶ 56-64; Figs. 12-14];
[2a] bonding a first package component 512 and a second package component 514 to the build-up package substrate 200 [¶ 71; Fig. 19],
[2b] wherein the first package component 512 and the second package component 514 are electrically interconnected through the interconnect die [¶ 23: “The local interconnect components 120 provide electrical routing and connection between the integrated circuit dies 512 and 514 of the integrated circuit package 500 and may be referred to as interconnecting dies 120.”]; and
[3a] wherein the first plurality of RDLs 110, 116 comprise:
[3b] a first plurality of vias 112 [labeled in Figs. 2A-2B and 6 and shown, but not labeled, in Figs. 1 and 23] over the interconnect die 120, wherein the first plurality of vias 112 are tapered and have upper widths smaller than respective lower widths [see explanation below]; and
[3c] a second plurality of vias 106 over and electrically coupled to the first plurality of vias 112 [as shown in Figs. 1, 2A-2B, and 23],
[3d] wherein the second plurality of vias 106 are tapered and have upper widths greater than respective lower widths [see explanation below];
[4] bonding an organic package substrate 300 to the build-up package substrate 200 [¶¶ 75-77; Figs. 22-23]; and.
[5] … [not taught] …
With regard to features [3b] and [3d] of claim 21, Wu-863 does not show in Figs. 1, 2A-2B, and 23 that the first 112 and second 106 pluralities of via are tapered. However, Wu-states that they can be:
[0061] Although the conductive vias in the redistribution layers 150, 154, 158, and 162 are shown with tapered sidewalls and the conductive vias in the redistribution layers 90, 92, and 94 are shown with non-tapered sidewalls, the sidewalls of the conductive vias of each of the redistribution layers 90, 92, 94, 95, 150, 154, 158, and 162 may be tapered, non-tapered, or a combination thereof. In some embodiments, the sidewall profiles of the conductive vias is controlled to be tapered or non-tapered by controlling the lithography and etching processes that form the openings in which the conductive vias are formed.
(Wu-863: ¶ 61; emphasis added)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to taper the sidewalls of the vias 106 and 112 of the RDL layers 90 and 92 because Wu-863 explicitly suggests that they can be.
As to the claimed opposing direction of the taper or widths for the first and second pluralities of vias, such as shown by the first 26 and second 68 pluralities of vias in, e.g., Fig. 8 of the Instant Application, that results in the first plurality of vias 26 having “upper widths smaller than respective lower widths” and the second plurality of vias 68 having “upper widths greater than respective lower widths”, this limitation is an obvious matter of design choice because Wu-863 states that the taper can be “controlled … by controlling the lithography and etching processes that form the openings in which the conductive vias are formed” (id.).
Moreover, it has been held that changes in configuration are “obvious absent persuasive evidence that the particular configuration of the claimed …[element]… was significant”. See In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.) Here, the Instant Specification does not even mention the word “taper” much less discuss any significance to the first plurality of vias 26 having “upper widths smaller than respective lower widths” and the second plurality of vias 68 having “upper widths greater than respective lower widths”. As such, it is clear that Applicant has merely pulled this feature from, e.g., Fig. 8 of the Instant Application.
Even if, arguendo, there were discussion in the specification, this is still obvious in view of the discussion in Wu-863. In this regard, the first plurality of vias 112 in Wu-863 are (manufactured as shown in Figs. 4-6), it is typical in the art to form the upper portion of a via opening wider than at the bottom in order to aid filling of the via with good step coverage by preventing pinch-off at the upper portion of the via opening, such as shown in the formation of other tapered vias in Figs. 13 and 14 of Wu-863. Therefore, when the first plurality of vias 112 manufactured in Fig. 6 are formed to have a tapered opening in a manner such as shown in Figs. 13-14 of Wu-863, will having the wider opening at the top and, consequently, when inverted as shown in Figs. 1, 2A-2B and 23 of Wu-863, will have “upper widths smaller than respective lower widths” as required by feature [3b].
In addition, with regard to the claimed the second plurality of vias, these may also be taken to be, instead of vias 106, the “under-bump metallizations (UBMs) 186” (infra) shown in Figs. 1, 2A-2B, and 23, connected to the vias 106. With regard to the UBMs 186, Wu-863 states,
[0067] In FIG. 16, under-bump metallizations (UBMs) 186 (sometimes referred to as pads 186) are formed for external connection to conductive vias 106. The UBMs 186 have bump portions on and extending along the major surface of the dielectric layer 108, and may have via portions extending into the dielectric layer 108 to physically and electrically couple the conductive via 106. …
(Wu-863: ¶ 67; emphasis added)
Because the “via portions” of the UBMs 186 are formed after the package is inverted a tapered opening for said “via portions”, when tapered, as consistent with paragraph [0061] of Wu-863 (supra) would result in the upper portion wider than the lower portion contacting the vias 106. As in Wu-863, the via configuration in Fig. 8 of the Instant Application shows that the equivalent of the claimed “second plurality of vias 68” are the via portions of “UBMs 68” (Instant Specification: ¶ 33; emphasis added).
Based on all of the foregoing, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the first plurality of vias 112 tapered to have “upper widths smaller than respective lower widths” and the second plurality of vias, 106 or 186, tapered to have “upper widths greater than respective lower widths”, in the package shown in Figs. 1 and 23 because Wu-863 suggests making the vias tapered and that the taper can be controlled, and because it is an obvious matter of design choice (supra).
This is all of the limitations of features [3b] and [3d].
With regard to feature [5] of claim 21, Wu-863 does not disclose at stiffener attached by an adhesive and does not therefore teach the limitations of features [5].
Wu-785 and Wu-863 share common inventors and assignee. Wu-785, like Wu-863, teaches a semiconductor device package 300 including package components 352A-C mounted on a redistribution structure 100 that is, in turn, electrically bonded by solder connections 220 to a interconnect substrate 200A, 200B (Wu-785: Fig. 18; ¶¶ 51-53, 61). Wu-785 further teaches attaching a stiffening ring 320 to the redistribution structure 100 by an adhesive layer (not shown) to reduce warpage of the package structure (Wu-785: ¶ 66).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, make the width of the redistribution structure 200 of Wu-863 sufficiently wide to accommodate a stiffening ring and to attach the stiffening ring using adhesive to the surface of the redistribution structure 200 adjacent to the package components 512, 514 of Wu-863, as taught in Wu-785, in order to prevent warpage of the package. As such, Wu-785 may be seen as an improvement to Wu-863 in this aspect. (See MPEP 2143.)
So modified, Wu-863/Wu785 teaches,
[4a] attaching a stiffener ring [320 of Wu-785] to the first encapsulant 140 [of Wu-863] through an adhesive film [as taught by Wu-785],
[4b] wherein the adhesive film physically contacts the … the stiffener ring [in order to attach it to the redistribution structure 200, as explained in Wu-785]
Although Wu-863/Wu-785 does not teach that the adhesive film contacts the first encapsulant, as explained under the rejection of claim 21 under 35 USC 112(a), the Instant Application does not teach this either.
This is all of the features of claim 21.
With regard to claims 22, 26, and 27, Wu-863 further discloses,
22. (Previously presented) The method of claim 21, wherein the organic package substrate 300 is bonded to the build-up package substrate 200 through solder regions 365 [¶ 76; Fig. 23].
26. (Previously presented) The method of claim 21, wherein the interconnect die 120 [Fig. 7] comprises:
[1] a low-k dielectric layer; and
[2] a metal line in the low-k dielectric layer [¶ 39: “The interconnect structure 130 interconnects the devices 124 and/or provides electrical routing and connection between die connectors 133. The interconnect structure 130 may be formed by, for example, metallization patterns in dielectric layers on the ILD 126 using for example a damascene process. The metallization patterns include metal lines and vias formed in one or more low-k dielectric layers.”],
[3] wherein the metal line electrically connects the first package component 512 to the second package component 514 [¶¶ 23, supra and ¶ 29: “because the local interconnect component 120 is being used for electrical connection between the dies of the integrated circuit package 500, the interconnect structure 130 of the local interconnect component 120 will often have many more interconnect layers to accommodate this electrical connection.”].
27. (Previously presented) The method of claim 21, wherein the interconnect die 120 comprises
[1] through-semiconductor vias 123 therein [¶ 23; Fig. 7], and
[2] wherein the first plurality of RDLs 110, 116 are electrically connected to the second plurality of RDLs 150/154/158/162 through the through-semiconductor vias 123 [as shown in Figs. 13 and 14].
B. Claims 1-5, 7-10, 21-26, 28, 29, and 31 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0335726 (“Wu-726”) in view of Wu-785 and Wu-863.
The applied reference has a common Assignee with the Instant Application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
In addition to including any one of the statements pursuant to 35 U.S.C. 102(b)(2)(A) through (C), (supra), to overcome Wu-726 as prior art available under 35 USC 102(a)(2), it is still applicable as prior art under 35 U.S.C. 102(a)(1) that cannot be excepted under 35 U.S.C. 102(b)(2)(C). In this instance, Applicant may rely on the exception under 35 U.S.C. 102(b)(1)(A) to overcome this rejection under 35 U.S.C. 102(a)(1) by a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application, and is therefore not prior art under 35 U.S.C. 102(a)(1). Alternatively, applicant may rely on the exception under 35 U.S.C. 102(b)(1)(B) by providing evidence of a prior public disclosure via an affidavit or declaration under 37 CFR 1.130(b).
Turning now to the rejection …
Claim 1 reads,
1. (Currently amended) A method comprising:
[1a] forming a build-up package substrate comprising:
[1b-1] forming a first plurality of redistribution lines (RDLs) and a second plurality of RDLs over a carrier,
[1b-2] wherein the first plurality of RDLs comprise a first plurality of vias and a second plurality of vias;
[1c] forming a first plurality of through-vias on the first plurality of RDLs;
[1d] bonding an interconnect die to the second plurality of RDLs;
[1e] encapsulating the interconnect die and the first plurality of through-vias in a first encapsulant; and
[1f] forming a third plurality of RDLs over the first encapsulant,
[1g] wherein the third plurality of RDLs are electrically connected to the first plurality of through-vias;
[2a] bonding an organic package substrate to the build-up package substrate,
[2b] wherein the build-up package substrate and the organic package substrate in combination form a compound organic package substrate; and
[3a] bonding a first package component and a second package component to the compound organic package substrate,
[3b] wherein the first package component and the second package component are electrically interconnected through the interconnect die; and
[4] attaching a stiffener ring to the first encapsulant,
[5a] wherein at a time of the attaching:
[5b] the first plurality of vias are over the interconnect die and are tapered with upper widths smaller than respective lower widths, and
[5c] the second plurality of vias are over the first plurality of vias and are tapered with upper widths greater than respective lower widths.
With regard to claim 1, Wu-726 discloses,
1. (Currently amended) A method comprising:
[1a] forming a build-up package substrate 200 [Figs. 1, 2, 4-16] comprising:
[1b-1] forming a first plurality of redistribution lines (RDLs) 110, 116 and a second plurality of RDLs 110, 116 over a carrier 102 [¶¶ 29-36; Figs. 4-6],
[1b-2] wherein the first plurality of RDLs comprise a first plurality of vias 112 and a second plurality of vias 106 or 186 [¶¶ 29-36; Figs. 4-6; ¶ 64; Fig. 15];
[1c] forming a first plurality of through-vias 118 on the first plurality of RDLs 110, 116 [¶ 36; Fig. 6];
[1d] bonding an interconnect die 120 [¶¶ 24, 37-45; Fig. 7] to the second plurality of RDLs 110, 116 [¶ 46; Fig. 8];
[1e] encapsulating the interconnect die and the first plurality of through-vias in a first encapsulant 140 [¶¶ 51-53; Fig. 9]; and
[1f] forming a third plurality of RDLs 150/154/158/162/166/170 over the first encapsulant 140 [¶¶ 55-58; Figs. 10-13],
[1g] wherein the third plurality of RDLs 150/154/158/162/166/170 are electrically connected to the first plurality of through-vias 118 [as shown in Figs. 10-13];
[2a] bonding an organic [¶ 69] package substrate 300A, 300B to the build-up package substrate 200 [¶¶ 68-76; Figs. 17-18],
[2b] wherein the build-up package substrate 200 and the organic package substrate 300A, 300B in combination form a compound organic package substrate 200/(300A, 300B) [Figs. 18-23]; and
[3a] bonding a first package component and a second package component [512 and 514 or 514 and 516] to the compound organic package substrate 200/(300A, 300B) [¶¶ 81-84; Figs. 1, 23],
[3b] wherein the first package component and the second package component [512 and 514 or 514 and 516] are electrically interconnected through the interconnect die [¶ 24: “The local interconnect components 120 provide electrical routing and connection between the integrated circuit dies 512, 514, and 516 of the integrated circuit package 500 and may be referred to as interconnecting dies 120.”]; and
[4] … [not taught] …
[5a] wherein at a time of the attaching [the stiffener ring]:
[5b] the first plurality of vias are over the interconnect die and are tapered with upper widths smaller than respective lower widths, and
[5c] the second plurality of vias are over the first plurality of vias and are tapered with upper widths greater than respective lower widths.
With regard to feature [4] of claim 1, Wu-726 does not disclose at stiffener attached by an adhesive and does not therefore teach the limitations of feature [4].
Wu-726 and Wu-785 share common inventors and assignee. Wu-785, like Wu-726, teaches a semiconductor device package 300 including package components 352A-C mounted on a redistribution structure 100 that is, in turn, electrically bonded by solder connections 220 to a interconnect substrate 200A, 200B (Wu-785: Fig. 18; ¶¶ 51-53, 61). Wu-785 further teaches attaching a stiffening ring 320 to the redistribution structure 100 by an adhesive layer (not shown) to reduce warpage of the package structure (Wu-785: ¶ 66).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to attach a stiffening ring to the surface of the redistribution structure 200 adjacent to the package components 510, 512, 514 of Wu-726, as taught in Wu-785, in order to prevent warpage of the package. As such, Wu-785 may be seen as an improvement to Wu-726 in this aspect. (See MPEP 2143.)
So modified, Wu-726/Wu-785 teaches,
[4] attaching a stiffener ring [320 of Wu-785] to the first encapsulant 140 [of Wu-726].
The attachment of the stiffener ring 320 of Wu-785 to the first encapsulant 140 of Wu-726 is indirect, just as in the Instant Application.
With regard to features [5a]-[5c] of claim 1,
[5a] wherein at a time of the attaching [the stiffener ring]:
[5b] the first plurality of vias are over the interconnect die and are tapered with upper widths smaller than respective lower widths, and
[5c] the second plurality of vias are over the first plurality of vias and are tapered with upper widths greater than respective lower widths.
Wu-726 does not disclose that the first 112 and second 106 pluralities of vias are tapered.
As shown in Figs. 4-6 of each of Wu-726 and Wu-863, the first 112 and second 106 pluralities of vias are manufactured by the same processes. In addition, as shown in Fig. 15 of Wu-726 (¶ 64) and Fig. 16 of Wu-863 (¶ 67), the alternative second plurality of vias, i.e. the “via portions” of UBMs 186, are formed in the same processes. As explained above, Wu-863 renders the claimed configuration of tapered vias in features [5b]-[5c] obvious. That explanation is incorporated here.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the first plurality of vias 112 tapered to have “upper widths smaller than respective lower widths” and the second plurality of vias, 106 or 186, tapered to have “upper widths greater than respective lower widths”, in the package shown in Figs. 1 and 23 because Wu-863 suggests making the vias tapered and that the taper can be controlled, and because it is an obvious matter of design choice (supra).
Because the stiffener ring 320 of Wu-785 is attached to the upper surface of the redistribution structure 100 around the mounted, integrated circuit package 350 (Wu-726: Fig. 1), the stiffener ring 320 would be attached around the mounted packages 510, 512, 514 shown in Fig. 1 of Wu-726 (Fig. 1), which is after the structure shown in Fig. 23 of Wu-726 is completed. And, as shown in Figs. 1 and 23 of Wu-726, the orientation of the first 112 and second 106 or 186 pluralities of vias would have the claimed configuration suggested by Wu-863 “at a time of the attaching” the stiffener ring 320, as required by feature [5a].
This is all of the limitations of features [5a]-[5c], as well as all of the features of claim 1.
With regard to claims 2-5 and 7-10, Wu-726 further discloses,
2. (Previously presented) The method of claim 1, wherein the organic package substrate 300A, 300B and the first package component 512 or 514 are on opposite sides of the build-up package substrate 200 [as shown in Figs. 1 and 23].
3. (Original) The method of claim 1, wherein the interconnect die 120 [Fig. 7] comprises:
[1] a low-k dielectric layer [of 130]; and
[2] a metal line [of 130] in the low-k dielectric layer [¶ 40: “The interconnect structure 130 may be formed by, for example, metallization patterns in dielectric layers on the ILD 126 using for example a damascene process. The metallization patterns include metal lines and vias formed in one or more low-k dielectric layers.”],
[3] wherein the metal line electrically connects the first package component 512 or 514 to the second package component 514 or 516 [¶ 24, supra].
4. (Original) The method of claim 1 further comprising: after the organic package substrate 300A, 300B is bonded to the build-up package substrate 200, encapsulating the organic package substrate 300A, 300B in a second encapsulant 380 [¶¶ 79; Fig. 21].
5. (Original) The method of claim 4 further comprising, before the first package component and the second package component [512 and 514 or 514 and 516] are bonded to the compound organic package substrate 200/(300A, 300B), sawing through the second encapsulant 380 to separate the compound organic package substrate 101A from other compound organic package substrates 100B in the second encapsulant [¶ 82; Figs. 19, 20, 23].
7. (Original) The method of claim 1, wherein the first package component and the second package component [512 and 514 or 514 and 516] are bonded directly to the build-up package substrate 200 [as shown in Fig. 1].
8. (Original) The method of claim 1 further comprising,
[1] before the organic package substrate 300A, 300B is bonded to the build-up package substrate 200, bonding a passive device die 192 to the build-up package substrate 200 [¶ 67; Fig. 16],
[2] wherein the passive device die 192 is between the organic package substrate 300A, 300B and the build-up package substrate 200 [as shown in Figs. 1, 18, and 21-23].
9. (Original) The method of claim 1, wherein the interconnect die 120 is free from active device therein [¶ 39: “In some embodiments, the local interconnect component 120 may be free of active or passive devices and may only be used for routing of electrical signals.”].
10. (Original) The method of claim 1, wherein the organic package substrate 300A, 300-B is a cored substrate comprising a dielectric core 310 [¶¶ 68-70] and conductive pipes 320 in the dielectric core 310 [¶ 70: “In some embodiments, the conductive vias 320 are hollow conductive through vias having centers that are filled with an insulating material.”].
With regard to claim 21, Wu-726 discloses,
21. (Currently Amended) A method comprising:
[1a] forming a build-up package substrate 200 [Figs. 1, 2, 4-16] that comprises:
[1b] a first plurality of redistribution lines (RDLs) 110, 116 [¶¶ 29-36; Figs. 4-6];
[1c] an interconnect die 120 bonded to the first plurality of RDLs 110, 116 [¶ 46; Fig. 8]
[1d] a first encapsulant 140 encapsulating the interconnect die 120 therein [¶¶ 51-53; Fig. 9]; and
[1e] a second plurality of RDLs 150/154/158/162/166/170 on an opposite side of the first encapsulant 140 than the first plurality of RDLs 110, 116 [¶¶ 55-58; Figs. 10-13];
[2a] bonding a first package component and a second package component [512 and 514 or 514 and 516] to the build-up package substrate 200 [¶¶ 81-84; Figs. 1, 23],
[2b] wherein the first package component and the second package component [512 and 514 or 514 and 516] are electrically interconnected through the interconnect die 120 [¶ 24: “The local interconnect components 120 provide electrical routing and connection between the integrated circuit dies 512, 514, and 516 of the integrated circuit package 500 and may be referred to as interconnecting dies 120.”], and
[3a] wherein the first plurality of RDLs 110, 116 comprise:
[3b] a first plurality of vias 112 [labeled in Figs. 2 and 6 and shown, but not labeled, in Figs. 1 and 23] over the interconnect die 120, …
[3c] a second plurality of vias 106 or 186 over and electrically coupled to the first plurality of vias 112 [as shown in Figs. 1, 2, and 23],
[3d] … [not taught] …
[4] bonding an organic package substrate 300A, 300B to the build-up package substrate 300 [¶¶ 68-76; Figs. 17-18]
[5] … [not taught] …
With regard to features [3b] and [3d] of claim 21, Wu-726 does not teach that the first 112 and second 106 or 186 pluralities of vias are tapered. However, the tapering and relative configuration of the first 112 and second 106 or 186 pluralities of vias is obvious for the same reasons explained under claim 1, which is applied here.
With regard to features [5] of claim 21, as stated above, Wu-726 does not disclose the stiffener.
Again, Wu-785 teaches attaching a stiffening ring 320 to the redistribution structure 100 by an adhesive layer (not shown) to reduce warpage of the package structure (Wu-785: ¶ 66).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to attach the stiffening ring using adhesive to the surface of the redistribution structure 200 adjacent to the package components 510, 512, 514 of Wu-726, as taught in Wu-785, in order to prevent warpage of the package. As such, Wu-785 may be seen as an improvement to Wu-726 in this aspect. (See MPEP 2143.)
So modified, Wu-726/Wu-785 teaches,
[4] attaching a stiffener ring [320 of Wu-785] to the first encapsulant 140 [of Wu-726] through an adhesive film [as taught by Wu-785].
Although Wu-726/Wu-785 does not teach that the adhesive film contacts the first encapsulant, the Instant Application does not teach this either.
This is all of the features of claim 21.
With regard to claims 22-26, Wu-726 further discloses,
22. (Previously presented) The method of claim 21, wherein the organic package substrate 300A, 300B is bonded to the build-up package substrate 200 through solder regions 365 [¶ 69; Fig. 18].
23. (Previously presented) The method of claim 21 further comprising
[1] bonding a passive device die 192 to the build-up package substrate 200 [¶ 67; Fig. 16],
[2] wherein the passive device die 192 is between the build-up package substrate 200 and the organic package substrate 300A, 300B [as shown in Figs. 1, 18, and 21-23].
24. (Previously presented) The method of claim 21 further comprising encapsulating the organic package substrate 300A, 300B in a second encapsulant 380 [¶¶ 79; Fig. 21].
25. (Previously presented) The method of claim 24 further comprising
[1] performing a sawing process to saw-through the second encapsulant 380 [¶ 82; Figs. 19, 20, 23],
[2] wherein after the sawing process, a portion of the second encapsulant 380 is attached to the build-up package substrate 200 [as shown in Fig. 23].
26. (Previously presented) The method of claim 21, wherein the interconnect die 120 [Fig. 7] comprises:
[1] a low-k dielectric layer [of 130]; and
[2] a metal line [of 130] in the low-k dielectric layer [¶ 40: “The interconnect structure 130 may be formed by, for example, metallization patterns in dielectric layers on the ILD 126 using for example a damascene process. The metallization patterns include metal lines and vias formed in one or more low-k dielectric layers.”],
[3] wherein the metal line electrically connects the first package component 512 or 514 to the second package component 514 or 516 [¶ 24, supra].
With regard to claims 28, 29, and 31, Wu-726 modified to include the stiffener ring 320 of Wu-785, and to taper the first 112 and second 106 or 186 pluralities of vias as taught by Wu-863, as explained above, teaches,
28. (Currently amended) A method comprising:
[1a] forming a build-up package substrate 200 [Wu-726: Figs. 1, 2, 4-16] comprising:
[1b] an interconnect die 120 [Wu-726: ¶¶ 24, 37-46; Figs. 7-8]
[1c] a plurality of redistribution lines 110, 116 over the interconnect die 120, wherein the plurality of redistribution lines 110, 116 comprise a first plurality of vias 112; and
[1d] a first encapsulant 140 encapsulating the interconnect die 120 therein [Wu-726: ¶¶ 51-53; Fig. 9];
[2] bonding an organic package substrate 300A, 300B to the build-up package substrate 200 [Wu-726: ¶¶ 68-76; Figs. 17-18];
[3a] encapsulating the organic package substrate 300A, 300B in a second encapsulant 380 [Wu-726: ¶¶ 79; Fig. 21],
[3b] wherein first sidewalls of the build-up package substrate 200 are flush with second sidewalls of the second encapsulant 380 [as shown in Fig. 23 of Wu-726]; and
[4a] bonding the build-up package substrate 200 to the organic package substrate 300A, 300B through solder regions 365 [Wu-726: ¶ 69; Fig. 18],
[4b] wherein the solder regions 365 are in physical contact with both of the build-up package substrate 200 and the organic package substrate 300A, 300B [as shown in Fig. 18 of Wu-726]; and
[5] attaching a stiffener ring [320 of Wu-785] to the first encapsulant 140 [of Wu-726] [as explained under claim 1],
[6a] wherein the build-up package substrate 200 [of Wu-726] is underlying the stiffener ring 320 [of Wu-785 because the stiffener ring it attached on top surface of 200 shown in Fig. 1 of Wu-726 around the package 500, as shown in Fig. 18 of Wu-785], and
[6b] the first plurality of vias 112 are over the interconnect die 120 [as shown in Figs. 1 and 2 of Wu-726], and
[7] wherein the first plurality of vias 112 are tapered with upper widths smaller than respective lower widths [as taught by Wu-863 (supra)].
29. (Previously presented) The method of claim 28 further comprising:
[1a] bonding a first package component and a second package component [512 and 514 or 514 and 516] to the build-up package substrate 200 [Wu-726: ¶¶ 81-84; Figs. 1, 23],
[1b] wherein the first package component and the second package component [512 and 514 or 514 and 516] are electrically interconnected through the interconnect die 120 [Wu-726, ¶ 24: “The local interconnect components 120 provide electrical routing and connection between the integrated circuit dies 512, 514, and 516 of the integrated circuit package 500 and may be referred to as interconnecting dies 120.”]; and
[2a] dispensing a underfill 610 [Wu-726: ¶ 84; Figs. 1, 2],
[2b] wherein the underfill 610 is in physical contact with each of the first package component 512 or 514, the second package component 514 or 516, and the build-up package substrate 200 [as shown in Figs. 1 and 2 of Wu-726].
31. (New) The method of claim 28, wherein
[1] the plurality of redistribution lines 110, 116 [of Wu-726] further comprise a second plurality of vias 106 or 186 [of Wu-726] over and electrically coupled to the first plurality of vias 112 [of Wu-726],
[2] with the organic package substrate 300A, 300B [of Wu-726] being under the build-up package substrate 200 [as shown in Figs. 1 and 2 of Wu-726], and
[3] wherein the second plurality of vias 106 or 186 [of Wu-726] are tapered with upper widths greater than respective lower widths [as taught by Wu-863 (supra)].
C. Claims 1-4, 6, 7, 9, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Wu-863 in view of US 2021/0225780 (“Wu-780”) and Wu-785.
The applied reference, Wu-780, has a common Assignee with the Instant Application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
In addition to including any one of the statements pursuant to 35 U.S.C. 102(b)(2)(A) through (C), (supra), to overcome Wu-780 as prior art available under 35 USC 102(a)(2), it is still applicable as prior art under 35 U.S.C. 102(a)(1) that cannot be excepted under 35 U.S.C. 102(b)(2)(C). In this instance, Applicant may rely on the exception under 35 U.S.C. 102(b)(1)(A) to overcome this rejection under 35 U.S.C. 102(a)(1) by a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application, and is therefore not prior art under 35 U.S.C. 102(a)(1). Alternatively, applicant may rely on the exception under 35 U.S.C. 102(b)(1)(B) by providing evidence of a prior public disclosure via an affidavit or declaration under 37 CFR 1.130(b).
Turning now to the rejection …
Claim 1 reads,
1. (Currently amended) A method comprising:
[1a] forming a build-up package substrate comprising:
[1b-1] forming a first plurality of redistribution lines (RDLs) and a second plurality of RDLs over a carrier,
[1b-2] wherein the first plurality of RDLs comprise a first plurality of vias and a second plurality of vias;
[1c] forming a first plurality of through-vias on the first plurality of RDLs;
[1d] bonding an interconnect die to the second plurality of RDLs;
[1e] encapsulating the interconnect die and the first plurality of through-vias in a first encapsulant; and
[1f] forming a third plurality of RDLs over the first encapsulant,
[1g] wherein the third plurality of RDLs are electrically connected to the first plurality of through-vias;
[2a] bonding an organic package substrate to the build-up package substrate,
[2b] wherein the build-up package substrate and the organic package substrate in combination form a compound organic package substrate; and
[3a] bonding a first package component and a second package component to the compound organic package substrate,
[3b] wherein the first package component and the second package component are electrically interconnected through the interconnect die; and
[4] attaching a stiffener ring to the first encapsulant,
[5a] wherein at a time of the attaching:
[5b] the first plurality of vias are over the interconnect die and are tapered with upper widths smaller than respective lower widths, and
[5c] the second plurality of vias are over the first plurality of vias and are tapered with upper widths greater than respective lower widths.
With regard to claim 1, Wu-863 discloses,
1. (Original) A method comprising:
[1a] forming a build-up package substrate [i.e. “redistribution structure 200” (¶ 17; Figs. 1, 23)] comprising:
[1b-1] forming a first plurality of redistribution lines (RDLs) 110, 116 [¶¶ 22, 31-35; Figs. 4-6] and a second plurality of RDLs 110, 116 over a carrier 102 [¶ 29] ,
[1b-2] wherein the first plurality of RDLs 110, 116 comprise a first plurality of vias 112 and a second plurality of vias 106 or 186;
[1c] forming a first plurality of through-vias 118 [¶ 35; Fig. 8] on the first plurality of RDLs 110, 116;
[1d] bonding an interconnect die 120 to the second plurality of RDLs [¶¶ 36-37, 47-48; Figs. 7-8];
[1e] encapsulating the interconnect die 120 and the first plurality of through-vias 118 in a first encapsulant 140 [¶¶ 50-51; Fig. 10]; and
[1f] forming a third plurality of RDLs 150/154/158/162 over the first encapsulant 140 [¶¶ 56-64; Figs. 12-14],
[1g] wherein the third plurality of RDLs 150/154/158/162 are electrically connected to the first plurality of through-vias 118 [as shown in Figs. 12-14];
[2a] bonding an organic package substrate 300 to the build-up package substrate 200 [¶ 75; Figs. 22-23],
[2b] wherein the build-up package substrate 200 and the organic package substrate 300 [¶¶ 76-77] in combination form a compound organic package substrate 200/300 [¶¶ 26, 75-84; Figs. 22-23]; and
[3a] bonding a first package component 512 and a second package component 514 to the … organic package substrate 200/300 [¶ 71; Fig. 19],
[3b] wherein the first package component 512 and the second package component 514 are electrically interconnected through the interconnect die 120 [¶ 23: “The local interconnect components 120 provide electrical routing and connection between the integrated circuit dies 512 and 514 of the integrated circuit package 500 and may be referred to as interconnecting dies 120.”]; and
[4] … [not taught] …
[5a] … [not taught] …
[5b] the first plurality of vias 112 are over the interconnect die 120 and are tapered with upper widths smaller than respective lower widths [infra], and
[5c] the second plurality of vias 106 or 186 are over the first plurality of vias 112 and are tapered with upper widths greater than respective lower widths [infra].
With regard to feature [3a] of claim 1, Wu-863 does not bond the package components 512 and 514 to the “compound” organic package substrate 200/300. Instead, Wu-863 bonds the package components 512 and 514 to the build-up substrate 200 (Figs. 19-21) and then bonds the build-up substrate 200 to the organic package substrate 300 (Figs. 22-23).
Wu-780 shares a common assignee and common inventors and teaches the same package structure as that in Wu-863 including, from top to bottom, plural package components 320A-320C bonded to a build-up substrate 100, bonded, in turn, to an organic package substrate 200, the build-up substrate including an interconnect die 110 that electrically connects at least two of the plural package components 320A-320C (Wu-780: Fig. 13). Wu-780 further teaches that the build-up substrate 100 is bonded to the organic package substrate 200 (Wu-780: Figs. 7A-7B) before the plurality package components 320A-320C (Wu-780: Figs. 8-12). As such, Wu-780 teaches feature [3a] of claim 1, i.e. “bonding a first package component 320A and a second package component 320B to the compound organic package substrate 100/200”.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to bond together the build-up substrate 200 to the organic package substrate 300 in Wu-863, thereby forming the claimed “compound organic package substrate” 200/300, before bonding the first and second package components 512, 514 to the “compound organic package substrate” 200/300 in Wu-863 because Wu-780 teaches that this sequence is suitable for assembling the same kind of package including the same general components, i.e. package components on a build-up substrate, on an organic package substrate. (See MPEP 2143.) Moreover, it has been held that the selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. See In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946). Because the same package is made, there does not appear to be any evidence of unexpected results, especially given that the same claimed sequence as to these steps is taught in the prior art.
With regard to feature [4] of claim 1,
[4] attaching a stiffener ring to the first encapsulant,
This feature is obvious in view of Wu-785 for the reasons explained under the rejection of claim 21 over Wu-863 in view of Wu-785, which is incorporated here.
With regard to features [5a]-[5c] of claim 1, features [5b] and [5c] are obvious for the reasons explained under of claim 21 under the rejection of features [3a]-[3d] of claim 21 over Wu-863 in view of Wu-785, which is incorporated here.
Because the stiffener ring 320 of Wu-785 is attached to the upper surface of the redistribution structure 200 around the mounted, package structure 500 (Wu-863: Figs. 1, 23), the stiffener ring 320 would be attached around the mounted packages 512, 514 shown in Figs. 1 and 23 of Wu-863 (Fig. 1), which is after the structure shown in Fig. 23 of Wu-863 is completed. And, as shown in Figs. 1 and 23 of Wu-863, the orientation of the first 112 and second 106 or 186 pluralities of vias would have the claimed configuration suggested by Wu-863 “at a time of the attaching” the stiffener ring 320, as required by feature [5a].
This is all of the limitations of features [5a]-[5c], as well as all of the features of claim 1.
With regard to claims 2 and 3, Wu-863 further discloses,
2. (Previously presented) The method of claim 1, wherein the organic package substrate 300 and the first package component 512 are on opposite sides of the build-up package substrate 200 [as shown in Figs. 1 and 23].
3. (Original) The method of claim 1, wherein the interconnect die 120 [Fig. 7] comprises:
[1] a low-k dielectric layer [of 130]; and
[2] a metal line in the low-k dielectric layer [of 130] [¶ 39: “The interconnect structure 130 interconnects the devices 124 and/or provides electrical routing and connection between die connectors 133. The interconnect structure 130 may be formed by, for example, metallization patterns in dielectric layers on the ILD 126 using for example a damascene process. The metallization patterns include metal lines and vias formed in one or more low-k dielectric layers.”],
[3] wherein the metal line electrically connects the first package component 512 to the second package component 514 [¶ 23, supra and ¶ 29: “because the local interconnect component 120 is being used for electrical connection between the dies of the integrated circuit package 500, the interconnect structure 130 of the local interconnect component 120 will often have many more interconnect layers to accommodate this electrical connection.”].
Claim 4 reads,
4. (Original) The method of claim 1 further comprising: after the organic package substrate is bonded to the build-up package substrate, encapsulating the organic package substrate in a second encapsulant.
Wu-863 does not teach encapsulating the organic package substrate 300.
Wu-780 further teaches encapsulating the organic package substrate in a second encapsulant 340 (as distinct from the first encapsulant 108 shown in Figs. 3, 4 of Wu-780) after the organic package substrate 200 is bonded to the build-up package substrate 100 (Wu-780: Figs. 7-8; ¶ 45).
In addition, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, after the organic package substrate 300 is bonded to the build-up package substrate 200 in Wu-863, encapsulating the organic package substrate 300 in a second encapsulant, in order to protect the organic package substrate and the associated electrical connections structures, as taught in Wu-780 (Wu-780: Figs. 7-8; ¶ 45).
With regard to claims 6, 7, 9, and 10, Wu-863 further discloses,
6. (Original) The method of claim 1,
[1] wherein the interconnect die 120 comprises a second plurality of through-vias 123 therein [¶¶ 40, 54, 55; Figs. 7 and 10], and
[2] the method further comprises planarizing the first encapsulant 140 to reveal the second plurality of through-vias 123 [¶ 51; Fig. 10],
[3] wherein the second plurality of through-vias 123 electrically connect the first plurality of RDLs 110, 116 to the third plurality of RDLs 150/154/158/162 [as shown in Figs. 12-14 of Wu-863].
7. (Original) The method of claim 1, wherein the first package component 512 and the second package component 514 are bonded directly to the build-up package substrate 100 [as shown in Figs. 16, 19, and 23].
9. (Original) The method of claim 1, wherein the interconnect die is free from active device therein [¶ 38: “In some embodiments, the local interconnect component 120 may be free of active or passive devices and may only be used for routing of electrical signals.”].
10. (Original) The method of claim 1, wherein the organic package substrate 300 is a cored substrate comprising a dielectric core 310 and conductive pipes 320A in the dielectric core 310 [¶¶ 75-77; Fig. 22].
IV. Response to Arguments
Applicant’s arguments filed 12/08/2025 have been fully considered but they are persuasive.
Applicant argues that the newly claimed features directed to the relative tapering of the first and second pluralities of vias in the redistribution lines. Examiner respectfully disagrees because Applicant failed to consider the explicit disclosure in Wu-863 that said vias can be tapered and that the tapering can be controlled. Applicant further ignored that the Instant Application fails to discuss any significance to the claimed relative tapered configuration of the first and second pluralities of vias in the redistribution lines.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK KIELIN whose telephone number is (571)272-1693. The examiner can normally be reached Mon-Fri: 10:00 AM-7:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814