DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 3-5, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura (US 7622366 B2; hereinafter Nakamura) in view of Koyanagi (US 20160013613 A1; hereinafter Koyanagi), and further in view of Umemura et al. (US 20100248404 A1; hereinafter Umemura).
Regarding claim 1, FIGS. 1-13C of Nakamura teach a manufacturing method for a device chip (e.g. FIGS. 1-13C), comprising: a wafer preparation step (FIGS. 1-5B) of preparing a wafer including a base substrate (2), and a device layer (22) being layered on the base substrate (2, col. 5/line 66 to col. 6/line 5) and having devices (22) formed in respective separate regions demarcated by a plurality of crossing division lines (21, col. 4/lines 32-35); a device layer dividing step (e.g. FIG. 2A) of attaching a rear surface of the wafer (2b) to a chuck table (31) using suction means (not shown, col. 4/lines 45-56) forming respective division grooves that divide at least the device layer (22) into individual device chips (22) along the plurality of division lines (21, col. 4/lines 38-45); a transfer member arranging step (e.g. FIGS. 3A-3B) of, after the device layer dividing step (FIG. 2A), attaching a transfer member (71) including a hard material with an adhesive (6) whose adhesion force is reduced by application by an external stimulus (e.g. laser beam set at 355 nm col. 8/lines 9-19) to a back surface of the device layer (2b, col. 5/lines 24-30); and a lift-off step (e.g. FIG. 9) of, after the transfer member arranging step (e.g. FIGS. 6A-6B) is carried out, applying a laser beam (pulsed laser beam) of such a wavelength as to be absorbed in the adhesive layer (6, col. 7/lines 62-65), from the base substrate (2) side (see FIG. 9), and lifting off a device chip (22) from the front surface of the base substrate (2a, col. 8/line 64 to col. 9/line 1).
Nakamura does not explicitly teach the device layer dividing step including attaching a rear surface of the wafer to a tape on a frame, holding the rear surface of the tape on a holding surface of a chuck table.
However, FIG. 8 of Nakamura teaches attaching a rear surface of the wafer (2b) to a tape (T) on a frame (F), holding the rear surface of the tape (surface of T facing 71) on a holding surface of a chuck table (top surface of 71 col. 7/lines 13-24).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device layer dividing step taught by Nakamura with the tape on the frame taught by Nakamura for the purpose of dicing the semiconductor structure.
Nakamura does not teach a laser beam absorbing layer layered on a front surface of the base substrate; attaching a transfer member directly to a front surface of the device layer and holding the transfer member on the holding surface of the chuck table; wherein the lift-off step of, after the transfer member arranging step is carried out, applying a laser beam of such a wavelength as to be absorbed in the laser beam absorbing layer, from the base substrate side, and lifting off a device chip from the front surface of the base substrate.
FIGS. 1A-5 of Koyanagi teach a manufacturing method for a device chip (e.g. FIGS. 1A-5), comprising: a wafer preparation step (FIG. 1B) of preparing a wafer (10) including a base substrate (11), a laser beam absorbing layer (13) layered on a front surface of the base substrate (11a), and a device layer (12) being layered on the laser beam absorbing layer (13) and having devices (16) formed in respective separate regions demarcated by a plurality of crossing division lines (15 ¶ [0026]); a transfer member arranging step (FIGS. 2A-C) of attaching a transfer member (20, 21) directly to a front surface of the device layer (12a ¶ [0028]) and holding the transfer member (20, 21) on the holding surface (top surface of 31) of the chuck table (31); and a lift-off step (FIGS. 3-10B) of, after the transfer member arranging step (FIGS. 2A-C) is carried out, applying a laser beam (pulsed laser beam) of such a wavelength as to be absorbed in the laser beam absorbing layer (13 ¶ [0030]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the manufacturing method for a device chip taught by Nakamura with the lift-off method taught by Koyanagi for the purpose of avoiding damage to the optical device layer during separation of the substrate (¶ [0041]).
Nakamura does not teach attaching a transfer member including a hard material with an adhesive whose adhesion force is reduced by application of an external stimulus
FIGS. 1A-1D of Umemura teach a manufacturing method for a device chip, comprising: a wafer preparation step (prior to FIG. 1A) of preparing a wafer including a base substrate (100), a laser beam absorbing layer (11) layered on a front surface of the base substrate (front surface of 100), and a device layer (12, L represented by broken line) being layered on the laser beam absorbing layer (11) and having devices (10, 130 disposed within respective device areas A’) formed in respective separate regions (A ¶ [0057]-[0058]); a device layer dividing step (prior to FIG. 1A) of forming respective division grooves (tr) that divide at least the device layer (12, L represented by broken line) into individual device chips (chips within A’ ¶ [0057]); a transfer member arranging step (FIGS. 1A-B) of, after the device layer dividing step (prior to FIG. 1A), attaching a transfer member (200) directly to a front surface of the device layer using an adhesive layer (120, 210 ¶ [0014],[0060]-[0061]); and a lift-off step (FIGS. 1C, 2A-B) of, after the transfer member arranging step (FIGS. 1A-B) is carried out, applying a laser beam (LS) of such a wavelength as to be absorbed in the laser beam absorbing layer (11), from the base substrate side (side of 11 close to 100), and lifting off a device chip (an instance of a chip within A’) from the front surface of the base substrate (front surface of 100 ¶ [0062]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the manufacturing method for a device chip taught by Nakamura with the laser-lift off method taught by Umemura for the purpose of reducing stress imposed on the epitaxial layer bonded to the epitaxial growth substrate during laser lift-off (¶ [0043],[0082]).
Regarding claim 3, Nakamura as modified teaches the method according to claim 1.
Nakamura does not teach in sufficient detail for anticipation wherein the lift-off step further includes applying a laser beam to an outermost peripheral edge of the laser beam absorbing layer while moving a focusing point of the laser beam and a chuck table relative to each other so that the focusing point of the laser beam moves in a spiral shape from the outermost peripheral edge to a center of the laser beam absorbing layer.
FIGS. 1A-5 of Koyanagi teach a manufacturing method for a device chip (e.g. FIGS. 1A-5), comprising: a wafer preparation step (FIG. 1B) of preparing a wafer (10) including a base substrate (11), a laser beam absorbing layer (13) layered on a front surface of the base substrate (11a), and a device layer (12) being layered on the laser beam absorbing layer (13) and having devices (16) formed in respective separate regions demarcated by a plurality of crossing division lines (15 ¶ [0026]); a transfer member arranging step (FIGS. 2A-C) of attaching a transfer member (20, 21) to a front surface of the device layer (12a ¶ [0028]); and a lift-off step (FIGS. 3-10B) of, after the transfer member arranging step (FIGS. 2A-C) is carried out, applying a laser beam (pulsed laser beam) of such a wavelength as to be absorbed in the laser beam absorbing layer (13 ¶ [0030]); wherein the lift-off step (FIGS. 3-10B) further includes applying a laser beam (pulsed laser beam) to an outermost peripheral edge of the laser beam absorbing layer (“outermost circumference of the epitaxy substrate 11” which corresponds to 13) while moving a focusing point of the laser beam (“light focus point of the laser beam”) and a chuck table (31 ¶ [0030]) relative to each other so that the focusing point of the laser beam moves in a spiral shape from the outermost peripheral edge to a center of the laser beam absorbing layer (see FIG. 5 ¶ [0031]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the manufacturing method for a device chip taught by Nakamura with the lift-off method taught by Koyanagi for the purpose of avoiding damage to the optical device layer during separation of the substrate (¶ [0041]).
Regarding claim 4, Nakamura as modified teaches the method according to claim 3, and FIGS. 10A-B of Koyanagi further teach wherein the lift-off step (FIGS. 3-10B) further includes peeling off the base substrate (11) from a surface of the device layer (12 ¶ [0040]).
Regarding claim 5, Nakamura as modified teaches the method according to claim 1, and FIGS. 13A-C of Nakamura further teach further comprising a device pick up step (FIGS. 13A-C) of picking up the device chip (22) lifted off the base substrate (2, col. 10/lines 6-11).
Regarding claim 7, Nakamura as modified teaches the method according to claim 1, and Nakamura further teaches wherein the external stimulus includes light irradiation with ultraviolet rays (e.g. laser beam set at 355 nm col. 8/lines 9-19).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura in view of Koyanagi and Umemura, and further in view of Torrents Abad et al. (US 10326040 B1; hereinafter Torrents).
Regarding claim 6, Nakamura as modified teaches the method according to claim 1.
Nakamura as modified does not teach wherein the transfer member is made with glass.
FIGS. 3-9 of Torrents teach a manufacturing method for a device chip, comprising: a transfer member arranging step (FIG. 9) of attaching a transfer member (904a) without an adhesive to a front surface of a device layer (surface of 102 closest to 110) using an adhesive layer (clayer 110, col. 8 lines 39-45); wherein the transfer member (904a) is made of glass (col. 9 lines 15-18).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the manufacturing method for the device chip taught by Nakamura with the transfer member material taught by Torrents for the purpose of forming the adhesive layer without damaging the device layer or the adhesive layer (col. 4 lines 51-57) and since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura in view of Koyanagi and Umemura, and further in view of Motoyama et al. (US 20140124897 A1; hereinafter Motoyama).
Regarding claim 8, Nakamura as modified teaches the method according to claim 1.
Nakamura does not teach wherein the external stimulus includes heating.
FIGS. 16-20 of Motoyama teach a method of manufacturing a semiconductor device (e.g. FIG. 16) including bonding a temporary support substrate (42) against a top-front surface of a device structure (see FIG. 17) using a temporary adhesive agent (41) whose adhesion force is reduced by application of an external stimulus including heat (¶ [0109],[0111]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing the device chip taught by Nakamura with the adhesive agent taught by Motoyama for the purpose of removing the adhesive without the need for a laser.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura in view of Koyanagi and Umemura, and further in view of Tanaka (US 20090244865 A1; hereinafter Tanaka).
Regarding claim 9, Nakamura as modified teaches the method according to claim 1.
Nakamura does not teach wherein the device layer includes an insulation layer, a silicon layer and a rewiring layer having the device chip.
FIGS. 2C-D of Tanaka teaches dicing a device layer (20, 22, 24, 33, 36-38a) including an insulation layer (22 ¶ [0037]), a silicon layer (20 ¶ [0037]-[0038]), and a rewiring layer (36-38a ¶ [0040]-[0041]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing the device chip taught by Nakamura with the device layer taught by Tanaka for the purpose of enhancing the functionality of the device taught by Tanaka by providing a decrease in thickness of the devices resulting from the method of manufacturing taught by Nakamura without sacrificing quality (col. 1/lines 58-67, col. 2/lines 1-4, col. 2/lines 53-58 of Nakamura) since it has been held in KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007), MPEP 2143(I)(A), that examples of rationales that may support a conclusion of obviousness include combining prior art elements according to known methods to yield predictable results, wherein in the instant case the device layer including the insulation layer, silicon layer, and the rewiring layer is/are taught in the art, one having ordinary skill in the art could have combined the device layer including the insulation layer, silicon layer, and the rewiring layer taught by Tanaka with the manufacturing method for the device chip taught by Nakamura with each element performing the same function as it does separately, and one having ordinary skill in the art would have found the combination predictable since the components are commonly used together.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nora T Nix whose telephone number is (571)270-1972. The examiner can normally be reached Monday - Friday 9:00 am - 5:00 pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nora T. Nix/Assistant Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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